1 /********************************************************************************
2 Copyright (C) 2016 Marvell International Ltd.
3
4 SPDX-License-Identifier: BSD-2-Clause-Patent
5
6 *******************************************************************************/
7
8 #ifndef __PP2_DXE_H__
9 #define __PP2_DXE_H__
10
11 #include <Protocol/AdapterInformation.h>
12 #include <Protocol/Cpu.h>
13 #include <Protocol/DevicePath.h>
14 #include <Protocol/DriverBinding.h>
15 #include <Protocol/Ip4.h>
16 #include <Protocol/Ip6.h>
17 #include <Protocol/MvPhy.h>
18 #include <Protocol/SimpleNetwork.h>
19
20 #include <Library/BaseLib.h>
21 #include <Library/BaseMemoryLib.h>
22 #include <Library/DebugLib.h>
23 #include <Library/DmaLib.h>
24 #include <Library/IoLib.h>
25 #include <Library/MemoryAllocationLib.h>
26 #include <Library/NetLib.h>
27 #include <Library/PcdLib.h>
28 #include <Library/UefiBootServicesTableLib.h>
29 #include <Library/UefiLib.h>
30
31 #include "Mvpp2LibHw.h"
32
33 #define MVPP2_MAX_PORT 3
34
35 #define PP2DXE_SIGNATURE SIGNATURE_32('P', 'P', '2', 'D')
36 #define INSTANCE_FROM_AIP(a) CR((a), PP2DXE_CONTEXT, Aip, PP2DXE_SIGNATURE)
37 #define INSTANCE_FROM_SNP(a) CR((a), PP2DXE_CONTEXT, Snp, PP2DXE_SIGNATURE)
38
39 /* OS API */
40 #define Mvpp2Alloc(v) AllocateZeroPool(v)
41 #define Mvpp2Free(p) FreePool(p)
42 #define Mvpp2Memset(a, v, s) SetMem((a), (s), (v))
43 #define Mvpp2Mdelay(t) gBS->Stall((t) * 1000)
44 #define Mvpp2Fls(v) 1
45 #define Mvpp2IsBroadcastEtherAddr(da) 1
46 #define Mvpp2IsMulticastEtherAddr(da) 1
47 #define Mvpp2Prefetch(v) do {} while(0);
48 #define Mvpp2Printf(...) do {} while(0);
49 #define Mvpp2SwapVariables(a,b) do { typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
50 #define Mvpp2SwapBytes16(x) SwapBytes16((x))
51 #define Mvpp2Iphdr EFI_IP4_HEADER
52 #define Mvpp2Ipv6hdr EFI_IP6_HEADER
53 #define MVPP2_ALIGN(x, m) ALIGN_VALUE((x), (m))
54 #define MVPP2_ENOMEM -1
55 #define MVPP2_EINVAL -2
56 #define MVPP2_ERANGE -3
57 #define MVPP2_USEC_PER_SEC 1000000L
58
59 #define DmaAddrT UINTN
60 #define PhysAddrT UINTN
61
62 #define Upper32Bits(n) ((UINT32)(((n) >> 16) >> 16))
63 #define Lower32Bits(n) ((UINT32)(n))
64
65 #define ARCH_DMA_MINALIGN 64
66
67 /* Port speeds */
68 #define MV_PORT_SPEED_10 SPEED_10
69 #define MV_PORT_SPEED_100 SPEED_100
70 #define MV_PORT_SPEED_1000 SPEED_1000
71 #define MV_PORT_SPEED_2500 SPEED_2500
72 #define MV_PORT_SPEED_10000 SPEED_10000
73
74 /* L2 and L3 protocol macros */
75 #define MV_IPPR_TCP 0
76 #define MV_IPPR_UDP 1
77 #define MV_IPPR_IPIP 2
78 #define MV_IPPR_ICMPV6 3
79 #define MV_IPPR_IGMP 4
80 #define MV_ETH_P_IP 5
81 #define MV_ETH_P_IPV6 6
82 #define MV_ETH_P_PPP_SES 7
83 #define MV_ETH_P_ARP 8
84 #define MV_ETH_P_8021Q 9
85 #define MV_ETH_P_8021AD 10
86 #define MV_ETH_P_EDSA 11
87 #define MV_PPP_IP 12
88 #define MV_PPP_IPV6 13
89 #define MV_ETH_ALEN NET_ETHER_ADDR_LEN
90
91 /* PHY modes */
92 #define MV_MODE_SGMII PHY_CONNECTION_SGMII
93 #define MV_MODE_RGMII PHY_CONNECTION_RGMII
94 #define MV_MODE_XAUI PHY_CONNECTION_XAUI
95 #define MV_MODE_RXAUI PHY_CONNECTION_RXAUI
96 #define MV_MODE_SFI PHY_CONNECTION_SFI
97 #define MV_MODE_QSGMII 100
98 #define PP2DXE_MAX_PHY 2
99
100 /* Gop */
101 /* Sets the field located at the specified in data */
102 #define U32_SET_FIELD(data, mask, val) ((data) = (((data) & ~(mask)) | (val)))
103 #define MV_RGMII_TX_FIFO_MIN_TH 0x41
104 #define MV_SGMII_TX_FIFO_MIN_TH 0x5
105 #define MV_SGMII2_5_TX_FIFO_MIN_TH 0xB
106
107 /* BM constants */
108 #define MVPP2_BM_POOLS_NUM 8
109 #define MVPP2_BM_LONG_BUF_NUM 1024
110 #define MVPP2_BM_SHORT_BUF_NUM 2048
111 #define MVPP2_BM_POOL_SIZE_MAX (SIZE_16KB - MVPP2_BM_POOL_PTR_ALIGN/4)
112 #define MVPP2_BM_POOL_PTR_ALIGN 128
113 #define MVPP2_BM_SWF_LONG_POOL(Port) ((Port > 2) ? 2 : Port)
114 #define MVPP2_BM_SWF_SHORT_POOL 3
115 #define MVPP2_BM_POOL 0
116 #define MVPP2_BM_SIZE 64
117
118 /*
119 * BM short pool packet Size
120 * These value assure that for SWF the total number
121 * of bytes allocated for each buffer will be 512
122 */
123 #define MVPP2_BM_SHORT_PKT_SIZE 512
124
125 /*
126 * Page table entries are set to 1MB, or multiples of 1MB
127 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
128 */
129 #define BD_SPACE (1 << 20)
130
131 /* Buffer has to be aligned to 1M */
132 #define MVPP2_BUFFER_ALIGN_SIZE (1 << 20)
133
134 /* RX constants */
135 #define RX_BUFFER_SIZE (ALIGN_VALUE(MTU + WRAP, ARCH_DMA_MINALIGN))
136 #define MVPP2_RXQ_OFFSET 0
137 #define BUFF_HDR_OFFS 32
138 #define BM_ALIGN 32
139 #define ETH_HLEN 14
140
141 /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
142 #define WRAP (2 + ETH_HLEN + 4 + 32)
143 #define MTU 1500
144
145 /*
146 * Maximum retries of checking, wheter HW really sent the packet
147 * after it was done is software.
148 */
149 #define MVPP2_TX_SEND_MAX_POLLING_COUNT 10000
150
151 /* Structures */
152 typedef struct {
153 /* Physical number of this Tx queue */
154 UINT8 Id;
155
156 /* Logical number of this Tx queue */
157 UINT8 LogId;
158
159 /* Number of Tx DMA descriptors in the descriptor ring */
160 INT32 Size;
161
162 /* Number of currently used Tx DMA descriptor in the descriptor ring */
163 INT32 count;
164
165 UINT32 DonePktsCoal;
166
167 /* Virtual address of thex Tx DMA descriptors array */
168 MVPP2_TX_DESC *Descs;
169
170 /* DMA address of the Tx DMA descriptors array */
171 DmaAddrT DescsPhys;
172
173 /* Index of the last Tx DMA descriptor */
174 INT32 LastDesc;
175
176 /* Index of the next Tx DMA descriptor to process */
177 INT32 NextDescToProc;
178 } MVPP2_TX_QUEUE;
179
180 typedef struct {
181 /* RX queue number, in the range 0-31 for physical RXQs */
182 UINT8 Id;
183
184 /* Num of rx descriptors in the rx descriptor ring */
185 INT32 Size;
186
187 UINT32 PktsCoal;
188 UINT32 TimeCoal;
189
190 /* Virtual address of the RX DMA descriptors array */
191 MVPP2_RX_DESC *Descs;
192
193 /* DMA address of the RX DMA descriptors array */
194 DmaAddrT DescsPhys;
195
196 /* Index of the last RX DMA descriptor */
197 INT32 LastDesc;
198
199 /* Index of the next RX DMA descriptor to process */
200 INT32 NextDescToProc;
201
202 /* ID of Port to which physical RXQ is mapped */
203 INT32 Port;
204
205 /* Port's logic RXQ number to which physical RXQ is mapped */
206 INT32 LogicRxq;
207 } MVPP2_RX_QUEUE;
208
209 enum Mvpp2BmType {
210 MVPP2_BM_FREE,
211 MVPP2_BM_SWF_LONG,
212 MVPP2_BM_SWF_SHORT
213 };
214
215 typedef struct {
216 /* Pool number in the range 0-7 */
217 INT32 Id;
218 enum Mvpp2BmType type;
219
220 /* Buffer Pointers Pool External (BPPE) Size */
221 INT32 Size;
222 /* Number of buffers for this pool */
223 INT32 BufNum;
224 /* Pool buffer Size */
225 INT32 BufSize;
226 /* Packet Size */
227 INT32 PktSize;
228
229 /* BPPE virtual base address */
230 UINT32 *VirtAddr;
231 /* BPPE physical base address */
232 DmaAddrT PhysAddr;
233
234 /* Ports using BM pool */
235 UINT32 PortMap;
236 } MVPP2_BMS_POOL;
237
238 typedef struct Pp2DxePort PP2DXE_PORT;
239
240 /* Structure for preallocation for buffer */
241 typedef struct {
242 MVPP2_TX_DESC *TxDescs[MVPP2_MAX_PORT];
243 MVPP2_TX_DESC *AggrTxDescs;
244 MVPP2_RX_DESC *RxDescs[MVPP2_MAX_PORT];
245 DmaAddrT RxBuffers[MVPP2_MAX_PORT];
246 } BUFFER_LOCATION;
247
248 /* Shared Packet Processor resources */
249 typedef struct {
250 /* Shared registers' base addresses */
251 UINT64 Base;
252 UINT64 MpcsBase;
253 UINT64 Rfu1Base;
254 UINT64 SmiBase;
255 UINT64 XpcsBase;
256
257 /* Preallocated buffers */
258 BUFFER_LOCATION BufferLocation;
259
260 /* List of pointers to Port structures */
261 PP2DXE_PORT **PortList;
262
263 /* Aggregated TXQs */
264 MVPP2_TX_QUEUE *AggrTxqs;
265
266 /* BM pools */
267 MVPP2_BMS_POOL *BmPools[MVPP2_MAX_PORT];
268 BOOLEAN BmEnabled;
269
270 /* PRS shadow table */
271 MVPP2_PRS_SHADOW *PrsShadow;
272 /* PRS auxiliary table for double vlan entries control */
273 BOOLEAN *PrsDoubleVlans;
274
275 /* Tclk value */
276 UINT32 Tclk;
277 } MVPP2_SHARED;
278
279 /* Individual Port structure */
280 struct Pp2DxePort {
281 UINT8 Id;
282 UINT8 GopIndex;
283
284 INT32 Irq;
285
286 MVPP2_SHARED *Priv;
287
288 /* Per-Port registers' base address */
289 UINT64 GmacBase;
290 UINT64 XlgBase;
291
292 MVPP2_RX_QUEUE *Rxqs;
293 MVPP2_TX_QUEUE *Txqs;
294
295 INT32 PktSize;
296
297 UINT32 PendingCauseRx;
298
299 /* Flags */
300 UINTN Flags;
301
302 UINT16 TxRingSize;
303 UINT16 RxRingSize;
304
305 INT32 PhyInterface;
306 UINT32 PhyIndex;
307 BOOLEAN Link;
308 BOOLEAN Duplex;
309 BOOLEAN AlwaysUp;
310 PHY_SPEED Speed;
311
312 MVPP2_BMS_POOL *PoolLong;
313 MVPP2_BMS_POOL *PoolShort;
314
315 UINT8 TxpNum;
316
317 /* Index of first Port's physical RXQ */
318 UINT8 FirstRxq;
319 };
320
321 typedef struct {
322 MAC_ADDR_DEVICE_PATH Pp2Mac;
323 EFI_DEVICE_PATH_PROTOCOL End;
324 } PP2_DEVICE_PATH;
325
326 #define QUEUE_DEPTH 64
327 typedef struct {
328 UINT32 Signature;
329 INTN Instance;
330 EFI_HANDLE Controller;
331 EFI_LOCK Lock;
332 EFI_SIMPLE_NETWORK_PROTOCOL Snp;
333 MARVELL_PHY_PROTOCOL *Phy;
334 PHY_DEVICE *PhyDev;
335 PP2DXE_PORT Port;
336 BOOLEAN Initialized;
337 BOOLEAN LateInitialized;
338 VOID *CompletionQueue[QUEUE_DEPTH];
339 UINTN CompletionQueueHead;
340 UINTN CompletionQueueTail;
341 EFI_EVENT EfiExitBootServicesEvent;
342 PP2_DEVICE_PATH *DevicePath;
343 EFI_ADAPTER_INFORMATION_PROTOCOL Aip;
344 } PP2DXE_CONTEXT;
345
346 /* Inline helpers */
347 STATIC
348 inline
349 VOID
Mvpp2Write(IN MVPP2_SHARED * Priv,IN UINT32 Offset,IN UINT32 data)350 Mvpp2Write (
351 IN MVPP2_SHARED *Priv,
352 IN UINT32 Offset,
353 IN UINT32 data
354 )
355 {
356 ASSERT (Priv->Base != 0);
357 MmioWrite32 (Priv->Base + Offset, data);
358 }
359
360 STATIC
361 inline
362 UINT32
Mvpp2Read(IN MVPP2_SHARED * Priv,IN UINT32 Offset)363 Mvpp2Read (
364 IN MVPP2_SHARED *Priv,
365 IN UINT32 Offset
366 )
367 {
368 ASSERT (Priv->Base != 0);
369 return MmioRead32 (Priv->Base + Offset);
370 }
371
372 STATIC
373 inline
374 UINT32
Mvpp2Rfu1Read(IN MVPP2_SHARED * Priv,UINT32 Offset)375 Mvpp2Rfu1Read (
376 IN MVPP2_SHARED *Priv,
377 UINT32 Offset
378 )
379 {
380 ASSERT (Priv->Rfu1Base != 0);
381 return MmioRead32 (Priv->Rfu1Base + Offset);
382 }
383
384 STATIC
385 inline
386 UINT32
Mvpp2Rfu1Write(IN MVPP2_SHARED * Priv,IN UINT32 Offset,IN UINT32 Data)387 Mvpp2Rfu1Write (
388 IN MVPP2_SHARED *Priv,
389 IN UINT32 Offset,
390 IN UINT32 Data
391 )
392 {
393 ASSERT (Priv->Rfu1Base != 0);
394 return MmioWrite32 (Priv->Rfu1Base + Offset, Data);
395 }
396
397 STATIC
398 inline
399 UINT32
Mvpp2SmiRead(IN MVPP2_SHARED * Priv,IN UINT32 Offset)400 Mvpp2SmiRead (
401 IN MVPP2_SHARED *Priv,
402 IN UINT32 Offset
403 )
404 {
405 ASSERT (Priv->SmiBase != 0);
406 return MmioRead32 (Priv->SmiBase + Offset);
407 }
408
409 STATIC
410 inline
411 UINT32
Mvpp2SmiWrite(IN MVPP2_SHARED * Priv,IN UINT32 Offset,IN UINT32 Data)412 Mvpp2SmiWrite (
413 IN MVPP2_SHARED *Priv,
414 IN UINT32 Offset,
415 IN UINT32 Data
416 )
417 {
418 ASSERT (Priv->SmiBase != 0);
419 return MmioWrite32 (Priv->SmiBase + Offset, Data);
420 }
421
422 STATIC
423 inline
424 VOID
Mvpp2GmacWrite(IN PP2DXE_PORT * Port,IN UINT32 Offset,IN UINT32 Data)425 Mvpp2GmacWrite (
426 IN PP2DXE_PORT *Port,
427 IN UINT32 Offset,
428 IN UINT32 Data
429 )
430 {
431 ASSERT (Port->Priv->Base != 0);
432 MmioWrite32 (Port->Priv->Base + Offset, Data);
433 }
434
435 STATIC
436 inline
437 UINT32
Mvpp2GmacRead(IN PP2DXE_PORT * Port,IN UINT32 Offset)438 Mvpp2GmacRead (
439 IN PP2DXE_PORT *Port,
440 IN UINT32 Offset
441 )
442 {
443 ASSERT (Port->Priv->Base != 0);
444 return MmioRead32 (Port->Priv->Base + Offset);
445 }
446
447 STATIC
448 inline
449 VOID
MvGop110GmacWrite(IN PP2DXE_PORT * Port,IN UINT32 Offset,IN UINT32 Data)450 MvGop110GmacWrite (
451 IN PP2DXE_PORT *Port,
452 IN UINT32 Offset,
453 IN UINT32 Data
454 )
455 {
456 ASSERT (Port->GmacBase != 0);
457 MmioWrite32 (Port->GmacBase + Offset, Data);
458 }
459
460 STATIC
461 inline
462 UINT32
MvGop110GmacRead(IN PP2DXE_PORT * Port,IN UINT32 Offset)463 MvGop110GmacRead (
464 IN PP2DXE_PORT *Port,
465 IN UINT32 Offset
466 )
467 {
468 ASSERT (Port->GmacBase != 0);
469 return MmioRead32 (Port->GmacBase + Offset);
470 }
471
472 STATIC
473 inline
474 VOID
Mvpp2XlgWrite(IN PP2DXE_PORT * Port,IN UINT32 Offset,IN UINT32 Data)475 Mvpp2XlgWrite (
476 IN PP2DXE_PORT *Port,
477 IN UINT32 Offset,
478 IN UINT32 Data
479 )
480 {
481 ASSERT (Port->XlgBase != 0);
482 MmioWrite32 (Port->XlgBase + Offset, Data);
483 }
484
485 STATIC
486 inline
487 UINT32
Mvpp2XlgRead(IN PP2DXE_PORT * Port,IN UINT32 Offset)488 Mvpp2XlgRead (
489 IN PP2DXE_PORT *Port,
490 IN UINT32 Offset
491 )
492 {
493 ASSERT (Port->XlgBase != 0);
494 return MmioRead32 (Port->XlgBase + Offset);
495 }
496
497 /* SNP callbacks */
498 EFI_STATUS
499 EFIAPI
500 Pp2SnpStart (
501 IN EFI_SIMPLE_NETWORK_PROTOCOL *This
502 );
503
504 EFI_STATUS
505 EFIAPI
506 Pp2SnpStop (
507 IN EFI_SIMPLE_NETWORK_PROTOCOL *This
508 );
509
510 EFI_STATUS
511 EFIAPI
512 Pp2DxeSnpInitialize (
513 IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
514 IN UINTN ExtraRxBufferSize OPTIONAL,
515 IN UINTN ExtraTxBufferSize OPTIONAL
516 );
517
518 EFI_STATUS
519 EFIAPI
520 Pp2SnpReset (
521 IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
522 IN BOOLEAN ExtendedVerification
523 );
524
525 EFI_STATUS
526 EFIAPI
527 Pp2SnpShutdown (
528 IN EFI_SIMPLE_NETWORK_PROTOCOL *This
529 );
530
531 EFI_STATUS
532 EFIAPI
533 Pp2SnpReceiveFilters (
534 IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
535 IN UINT32 Enable,
536 IN UINT32 Disable,
537 IN BOOLEAN ResetMCastFilter,
538 IN UINTN MCastFilterCnt OPTIONAL,
539 IN EFI_MAC_ADDRESS *MCastFilter OPTIONAL
540 );
541
542 EFI_STATUS
543 EFIAPI
544 Pp2SnpStationAddress (
545 IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
546 IN BOOLEAN Reset,
547 IN EFI_MAC_ADDRESS *NewMac
548 );
549
550 EFI_STATUS
551 EFIAPI
552 Pp2SnpNetStat (
553 IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
554 IN BOOLEAN Reset,
555 IN OUT UINTN *StatisticsSize OPTIONAL,
556 OUT EFI_NETWORK_STATISTICS *StatisticsTable OPTIONAL
557 );
558
559 EFI_STATUS
560 EFIAPI
561 Pp2SnpIpToMac (
562 IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
563 IN BOOLEAN IPv6,
564 IN EFI_IP_ADDRESS *IP,
565 OUT EFI_MAC_ADDRESS *MAC
566 );
567
568 EFI_STATUS
569 EFIAPI
570 Pp2SnpGetStatus (
571 IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp,
572 OUT UINT32 *InterruptStatus OPTIONAL,
573 OUT VOID **TxBuf OPTIONAL
574 );
575
576 EFI_STATUS
577 EFIAPI
578 Pp2SnpTransmit (
579 IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
580 IN UINTN HeaderSize,
581 IN UINTN BufferSize,
582 IN VOID *Buffer,
583 IN EFI_MAC_ADDRESS *SrcAddr OPTIONAL,
584 IN EFI_MAC_ADDRESS *DestAddr OPTIONAL,
585 IN UINT16 *EtherTypePtr OPTIONAL
586 );
587
588 EFI_STATUS
589 EFIAPI
590 Pp2SnpReceive (
591 IN EFI_SIMPLE_NETWORK_PROTOCOL *This,
592 OUT UINTN *HeaderSize OPTIONAL,
593 IN OUT UINTN *BufferSize,
594 OUT VOID *Buffer,
595 OUT EFI_MAC_ADDRESS *SrcAddr OPTIONAL,
596 OUT EFI_MAC_ADDRESS *DstAddr OPTIONAL,
597 OUT UINT16 *EtherType OPTIONAL
598 );
599 #endif
600