1 /** @file 2 Socionext FIP006 Register List 3 4 Copyright (c) 2017, Socionext Inc. All rights reserved.<BR> 5 Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR> 6 7 SPDX-License-Identifier: BSD-2-Clause-Patent 8 9 **/ 10 11 #ifndef __EFI_FIP006_REG_H__ 12 #define __EFI_FIP006_REG_H__ 13 14 #define FIP006_REG_MCTRL 0x00 // Module Control 15 typedef union { 16 UINT32 Raw : 32; 17 struct { 18 BOOLEAN MEN : 1; 19 BOOLEAN CSEN : 1; 20 #define MCTRL_CSEN_DIRECT 0 21 #define MCTRL_CSEN_CS 1 22 BOOLEAN CDSS : 1; 23 #define MCTRL_CDSS_IHCLK 0 24 #define MCTRL_CDSS_IPCLK 1 25 BOOLEAN MES : 1; 26 #define MCTRL_MES_READY 1 27 UINT8 : 4; 28 UINT8 : 8; 29 UINT8 : 8; 30 UINT8 : 8; 31 }; 32 } FIP006_MCTRL; 33 34 #define FIP006_REG_PCC0 0x04 // Peripheral Communication Control 0 35 #define FIP006_REG_PCC1 0x08 // Peripheral Communication Control 1 36 #define FIP006_REG_PCC2 0x0C // Peripheral Communication Control 2 37 #define FIP006_REG_PCC3 0x10 // Peripheral Communication Control 3 38 typedef union { 39 UINT32 Raw : 32; 40 struct { 41 BOOLEAN CPHA : 1; 42 BOOLEAN CPOL : 1; 43 BOOLEAN ACES : 1; 44 BOOLEAN RTM : 1; 45 BOOLEAN SSPOL : 1; 46 UINT8 SS2CD : 2; 47 BOOLEAN SDIR : 1; 48 #define PCC_SDIR_MS_BIT 0 49 #define PCC_SDIR_LS_BIT 1 50 BOOLEAN SENDIAN : 1; 51 #define PCC_SENDIAN_BIG 0 52 #define PCC_SENDIAN_LITTLE 1 53 UINT8 CDRS : 7; 54 BOOLEAN SAFESYNC : 1; 55 UINT8 WRDSEL : 4; 56 UINT8 RDDSEL : 2; 57 UINT8 : 1; 58 UINT8 : 8; 59 } Reg; 60 } FIP006_PCC; 61 typedef FIP006_PCC FIP006_PCC0, FIP006_PCC1, FIP006_PCC2, FIP006_PCC3; 62 63 #define FIP006_REG_TXF 0x14 // Tx Interrupt Flag 64 #define TXF_TSSRS BIT6 65 #define TXF_TFMTS BIT5 66 #define TXF_TFLETS BIT4 67 #define TXF_TFUS BIT3 68 #define TXF_TFOS BIT2 69 #define TXF_TFES BIT1 70 #define TXF_TFFS BIT0 71 72 #define FIP006_REG_TXE 0x18 // Tx Interrupt Enable 73 #define TXE_TSSRE BIT6 74 #define TXE_TFMTE BIT5 75 #define TXE_TFLETE BIT4 76 #define TXE_TFUE BIT3 77 #define TXE_TFOE BIT2 78 #define TXE_TFEE BIT1 79 #define TXE_TFFE BIT0 80 81 #define FIP006_REG_TXC 0x1C // Tx Interrupt Clear 82 #define TXC_TSSRC BIT6 83 #define TXC_TFMTC BIT5 84 #define TXC_TFLETC BIT4 85 #define TXC_TFUC BIT3 86 #define TXC_TFOC BIT2 87 #define TXC_TFEC BIT1 88 #define TXC_TFFC BIT0 89 90 #define FIP006_REG_RXF 0x20 // Rx Interrupt Flag 91 #define RXF_RSSRS BIT6 92 #define RXF_RFMTS BIT5 93 #define RXF_RFLETS BIT4 94 #define RXF_RFUS BIT3 95 #define RXF_RFOS BIT2 96 #define RXF_RFES BIT1 97 #define RXF_RFFS BIT0 98 99 #define FIP006_REG_RXE 0x24 // Rx Interrupt Enable 100 #define RXE_RSSRE BIT6 101 #define RXE_RFMTE BIT5 102 #define RXE_RFLETE BIT4 103 #define RXE_RFUE BIT3 104 #define RXE_RFOE BIT2 105 #define RXE_RFEE BIT1 106 #define RXE_RFFE BIT0 107 108 #define FIP006_REG_RXC 0x28 // Rx Interrupt Clear 109 #define RXC_RSSRC BIT6 110 #define RXC_RFMTC BIT5 111 #define RXC_RFLETC BIT4 112 #define RXC_RFUC BIT3 113 #define RXC_RFOC BIT2 114 #define RXC_RFEC BIT1 115 #define RXC_RFFC BIT0 116 117 #define FIP006_REG_FAULTF 0x2C // Error Interrupt Status 118 #define FAULTF_DRCBSFS BIT4 119 #define FAULTF_DWCBSFS BIT3 120 #define FAULTF_PVFS BIT2 121 #define FAULTF_WAFS BIT1 122 #define FAULTF_UMAFS BIT0 123 124 #define FIP006_REG_FAULTC 0x30 // Error Interrupt Clear 125 #define FAULTC_DRCBSFC BIT4 126 #define FAULTC_DWCBSFC BIT3 127 #define FAULTC_PVFC BIT2 128 #define FAULTC_WAFC BIT1 129 #define FAULTC_UMAFC BIT0 130 131 #define FIP006_REG_DM_CFG 0x34 // Direct Mode DMA Configuration 132 #define DM_CFG_MSTARTEN BIT2 133 #define DM_CFG_SSDC BIT1 134 135 #define FIP006_REG_DM_DMA 0x35 // Direct Mode DMA Enable 136 #define DM_DMA_TXDMAEN BIT1 137 #define DM_DMA_RXDMAEN BIT0 138 139 #define FIP006_REG_DM_START 0x38 // Direct Mode Start Transmission 140 #define DM_START BIT0 141 #define FIP006_REG_DM_STOP 0x39 // Direct Mode Stop Transmission 142 #define DM_STOP BIT0 143 144 #define FIP006_REG_DM_PSEL 0x3A // Direct Mode Peripheral Select 145 #define DM_PSEL (BIT1 | BIT0) 146 147 #define FIP006_REG_DM_TRP 0x3B // Direct Mode Transmission Protocol 148 #define DM_TRP (BIT3 | BIT2 | BIT1 | BIT0) 149 150 #define FIP006_REG_DM_BCC 0x3C // Direct Mode Byte Count Control 151 #define FIP006_REG_DM_BCS 0x3E // Direct Mode Byte Count Status 152 153 #define FIP006_REG_DM_STATUS 0x40 // Direct Mode Status 154 #define DM_STATUS_TXFLEVEL (BIT20 | BIT19 | BIT18 | BIT17 | BIT16) 155 #define DM_STATUS_RXFLEVEL (BIT20 | BIT19 | BIT18 | BIT17 | BIT16) 156 #define DM_STATUS_TXACTIVE BIT1 157 #define DM_STATUS_RXACTIVE BIT0 158 159 #define FIP006_REG_FIFO_CFG 0x4C // FIFO Configuration 160 #define FIFO_CFG_TXFLSH BIT12 161 #define FIFO_CFG_RXFLSH BIT11 162 #define FIFO_CFG_TXCTRL BIT10 163 #define FIFO_CFG_FWIDTH (BIT9 | BIT8) 164 #define FIFO_CFG_TXFTH (BIT7 | BIT6 | BIT5 | BIT4) 165 #define FIFO_CFG_RXFTH (BIT3 | BIT2 | BIT1 | BIT0) 166 167 #define FIP006_REG_FIFO_TX 0x50 // 16 32-bit Tx FIFO 168 #define FIP006_REG_FIFO_RX 0x90 // 16 32-bit Rx FIFO 169 170 #define FIP006_REG_CS_CFG 0xD0 // Command Sequencer Configuration 171 typedef union { 172 UINT32 Raw : 32; 173 struct { 174 BOOLEAN SRAM : 1; 175 #define CS_CFG_SRAM_RO 0 176 #define CS_CFG_SRAM_RW 1 177 UINT8 MBM : 2; 178 #define CS_CFG_MBM_SINGLE 0 179 #define CS_CFG_MBM_DUAL 1 180 #define CS_CFG_MBM_QUAD 2 181 BOOLEAN SPICHNG : 1; 182 BOOLEAN BOOTEN : 1; 183 BOOLEAN BSEL : 1; 184 UINT8 : 2; 185 BOOLEAN SSEL0EN : 1; 186 BOOLEAN SSEL1EN : 1; 187 BOOLEAN SSEL2EN : 1; 188 BOOLEAN SSEL3EN : 1; 189 UINT8 : 4; 190 BOOLEAN MSEL : 4; 191 UINT8 : 4; 192 UINT8 : 8; 193 } Reg; 194 } FIP006_CS_CFG; 195 196 #define FIP006_REG_CS_ITIME 0xD4 // Command Sequencer Idle Timer 197 typedef union { 198 UINT32 Raw : 32; 199 struct { 200 UINT16 ITIME : 16; 201 UINT16 : 16; 202 } Reg; 203 } FIP006_CS_ITIME; 204 #define FIP006_REG_CS_AEXT 0xD8 // Command Sequencer Address Extension 205 typedef union { 206 UINT32 Raw : 32; 207 struct { 208 UINT16 : 13; 209 UINT32 AEXT : 19; 210 } Reg; 211 } FIP006_CS_AEXT; 212 213 #define FIP006_REG_CS_RD 0xDC // Command Sequencer Read Control 214 #define CS_RD_DEPTH 8 215 #define FIP006_REG_CS_WR 0xEC // Command Sequencer Write Control 216 #define CS_WR_DEPTH 8 217 typedef union { 218 UINT16 Raw : 16; 219 struct { 220 BOOLEAN DEC : 1; 221 UINT8 TRP : 2; 222 BOOLEAN CONT : 1; 223 UINT8 : 4; 224 union { 225 UINT8 Data : 8; 226 struct { 227 UINT8 Data : 3; 228 UINT8 : 5; 229 } Cmd; 230 } Payload; 231 } Reg; 232 } FIP006_CS_CMD; 233 typedef FIP006_CS_CMD FIP006_CS_RD, FIP006_CS_WR; 234 235 #define FIP006_REG_MID 0xFC // Command Sequencer Module ID 236 typedef UINT32 FIP006_MID; 237 238 #endif 239