1 /*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2010 Carl-Daniel Hailfinger
5 * Copyright (C) 2010 Idwer Vollering
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 /*
18 * Datasheets:
19 * PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual
20 * 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx
21 * http://www.intel.com/content/www/us/en/ethernet-controllers/pci-pci-x-family-gbe-controllers-software-dev-manual.html
22 *
23 * PCIe GbE Controllers Open Source Software Developer's Manual
24 * http://www.intel.com/content/www/us/en/ethernet-controllers/pcie-gbe-controllers-open-source-manual.html
25 *
26 * Intel 82574 Gigabit Ethernet Controller Family Datasheet
27 * http://www.intel.com/content/www/us/en/ethernet-controllers/82574l-gbe-controller-datasheet.html
28 *
29 * Intel 82599 10 GbE Controller Datasheet (331520)
30 * http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/82599-10-gbe-controller-datasheet.pdf
31 */
32
33 #include <stdlib.h>
34 #include <unistd.h>
35 #include "flash.h"
36 #include "programmer.h"
37 #include "hwaccess.h"
38
39 #define PCI_VENDOR_ID_INTEL 0x8086
40 #define MEMMAP_SIZE getpagesize()
41
42 /* EEPROM/Flash Control & Data Register */
43 #define EECD 0x10
44 /* Flash Access Register */
45 #define FLA 0x1c
46
47 /*
48 * Register bits of EECD.
49 * Table 13-6
50 *
51 * Bit 04, 05: FWE (Flash Write Enable Control)
52 * 00b = not allowed (on some cards this sends an erase command if bit 31 (FL_ER) of FLA is set)
53 * 01b = flash writes disabled
54 * 10b = flash writes enabled
55 * 11b = not allowed
56 */
57 #define FLASH_WRITES_DISABLED 0x10 /* FWE: 10000b */
58 #define FLASH_WRITES_ENABLED 0x20 /* FWE: 100000b */
59
60 /* Flash Access register bits
61 * Table 13-9
62 */
63 #define FL_SCK 0
64 #define FL_CS 1
65 #define FL_SI 2
66 #define FL_SO 3
67 #define FL_REQ 4
68 #define FL_GNT 5
69 #define FL_LOCKED 6
70 #define FL_ABORT 7
71 #define FL_CLR_ERR 8
72 /* Currently unused */
73 // #define FL_BUSY 30
74 // #define FL_ER 31
75
76 #define BIT(x) (1<<(x))
77
78 static uint8_t *nicintel_spibar;
79
80 const struct dev_entry nics_intel_spi[] = {
81 {PCI_VENDOR_ID_INTEL, 0x105e, OK, "Intel", "82571EB Gigabit Ethernet Controller"},
82 {PCI_VENDOR_ID_INTEL, 0x1076, OK, "Intel", "82541GI Gigabit Ethernet Controller"},
83 {PCI_VENDOR_ID_INTEL, 0x107c, OK, "Intel", "82541PI Gigabit Ethernet Controller"},
84 {PCI_VENDOR_ID_INTEL, 0x10b9, OK, "Intel", "82572EI Gigabit Ethernet Controller"},
85 {PCI_VENDOR_ID_INTEL, 0x10d3, OK, "Intel", "82574L Gigabit Ethernet Controller"},
86
87 {PCI_VENDOR_ID_INTEL, 0x10d8, NT, "Intel", "82599 10 Gigabit Unprogrammed Network Controller"},
88 {PCI_VENDOR_ID_INTEL, 0x10f7, NT, "Intel", "82599 10 Gigabit KX4 Dual Port Network Controller"},
89 {PCI_VENDOR_ID_INTEL, 0x10f8, NT, "Intel", "82599 10 Gigabit Dual Port Backplane Controller"},
90 {PCI_VENDOR_ID_INTEL, 0x10f9, NT, "Intel", "82599 10 Gigabit CX4 Dual Port Network Controller"},
91 {PCI_VENDOR_ID_INTEL, 0x10fb, NT, "Intel", "82599 10-Gigabit SFI/SFP+ Network Controller"},
92 {PCI_VENDOR_ID_INTEL, 0x10fc, OK, "Intel", "82599 10 Gigabit XAUI/BX4 Dual Port Network Controller"},
93 {PCI_VENDOR_ID_INTEL, 0x1517, NT, "Intel", "82599 10 Gigabit KR Network Controller"},
94 {PCI_VENDOR_ID_INTEL, 0x151c, NT, "Intel", "82599 10 Gigabit TN Network Controller"},
95 {PCI_VENDOR_ID_INTEL, 0x1529, NT, "Intel", "82599 10 Gigabit Dual Port Network Controller with FCoE"},
96 {PCI_VENDOR_ID_INTEL, 0x152a, NT, "Intel", "82599 10 Gigabit Dual Port Backplane Controller with FCoE"},
97 {PCI_VENDOR_ID_INTEL, 0x1557, NT, "Intel", "82599 10 Gigabit SFI Network Controller"},
98
99 {PCI_VENDOR_ID_INTEL, 0x1531, OK, "Intel", "I210 Gigabit Network Connection Unprogrammed"},
100 {PCI_VENDOR_ID_INTEL, 0x1532, NT, "Intel", "I211 Gigabit Network Connection Unprogrammed"},
101 {PCI_VENDOR_ID_INTEL, 0x1533, NT, "Intel", "I210 Gigabit Network Connection"},
102 {PCI_VENDOR_ID_INTEL, 0x1536, NT, "Intel", "I210 Gigabit Network Connection SERDES Fiber"},
103 {PCI_VENDOR_ID_INTEL, 0x1537, NT, "Intel", "I210 Gigabit Network Connection SERDES Backplane"},
104 {PCI_VENDOR_ID_INTEL, 0x1538, NT, "Intel", "I210 Gigabit Network Connection SGMII"},
105 {PCI_VENDOR_ID_INTEL, 0x1539, NT, "Intel", "I211 Gigabit Network Connection"},
106
107 {0},
108 };
109
nicintel_request_spibus(void)110 static void nicintel_request_spibus(void)
111 {
112 uint32_t tmp;
113
114 tmp = pci_mmio_readl(nicintel_spibar + FLA);
115 tmp |= BIT(FL_REQ);
116 pci_mmio_writel(tmp, nicintel_spibar + FLA);
117
118 /* Wait until we are allowed to use the SPI bus. */
119 while (!(pci_mmio_readl(nicintel_spibar + FLA) & BIT(FL_GNT))) ;
120 }
121
nicintel_release_spibus(void)122 static void nicintel_release_spibus(void)
123 {
124 uint32_t tmp;
125
126 tmp = pci_mmio_readl(nicintel_spibar + FLA);
127 tmp &= ~BIT(FL_REQ);
128 pci_mmio_writel(tmp, nicintel_spibar + FLA);
129 }
130
nicintel_bitbang_set_cs(int val)131 static void nicintel_bitbang_set_cs(int val)
132 {
133 uint32_t tmp;
134
135 tmp = pci_mmio_readl(nicintel_spibar + FLA);
136 tmp &= ~BIT(FL_CS);
137 tmp |= (val << FL_CS);
138 pci_mmio_writel(tmp, nicintel_spibar + FLA);
139 }
140
nicintel_bitbang_set_sck(int val)141 static void nicintel_bitbang_set_sck(int val)
142 {
143 uint32_t tmp;
144
145 tmp = pci_mmio_readl(nicintel_spibar + FLA);
146 tmp &= ~BIT(FL_SCK);
147 tmp |= (val << FL_SCK);
148 pci_mmio_writel(tmp, nicintel_spibar + FLA);
149 }
150
nicintel_bitbang_set_mosi(int val)151 static void nicintel_bitbang_set_mosi(int val)
152 {
153 uint32_t tmp;
154
155 tmp = pci_mmio_readl(nicintel_spibar + FLA);
156 tmp &= ~BIT(FL_SI);
157 tmp |= (val << FL_SI);
158 pci_mmio_writel(tmp, nicintel_spibar + FLA);
159 }
160
nicintel_bitbang_get_miso(void)161 static int nicintel_bitbang_get_miso(void)
162 {
163 uint32_t tmp;
164
165 tmp = pci_mmio_readl(nicintel_spibar + FLA);
166 tmp = (tmp >> FL_SO) & 0x1;
167 return tmp;
168 }
169
170 static const struct bitbang_spi_master bitbang_spi_master_nicintel = {
171 .set_cs = nicintel_bitbang_set_cs,
172 .set_sck = nicintel_bitbang_set_sck,
173 .set_mosi = nicintel_bitbang_set_mosi,
174 .get_miso = nicintel_bitbang_get_miso,
175 .request_bus = nicintel_request_spibus,
176 .release_bus = nicintel_release_spibus,
177 .half_period = 1,
178 };
179
nicintel_spi_shutdown(void * data)180 static int nicintel_spi_shutdown(void *data)
181 {
182 uint32_t tmp;
183
184 /* Disable writes manually. See the comment about EECD in nicintel_spi_init() for details. */
185 tmp = pci_mmio_readl(nicintel_spibar + EECD);
186 tmp &= ~FLASH_WRITES_ENABLED;
187 tmp |= FLASH_WRITES_DISABLED;
188 pci_mmio_writel(tmp, nicintel_spibar + EECD);
189
190 return 0;
191 }
192
nicintel_spi_82599_enable_flash(void)193 static int nicintel_spi_82599_enable_flash(void)
194 {
195 uint32_t tmp;
196
197 /* Automatic restore of EECD on shutdown is not possible because EECD
198 * does not only contain FLASH_WRITES_DISABLED|FLASH_WRITES_ENABLED,
199 * but other bits with side effects as well. Those other bits must be
200 * left untouched.
201 */
202 tmp = pci_mmio_readl(nicintel_spibar + EECD);
203 tmp &= ~FLASH_WRITES_DISABLED;
204 tmp |= FLASH_WRITES_ENABLED;
205 pci_mmio_writel(tmp, nicintel_spibar + EECD);
206
207 /* test if FWE is really set to allow writes */
208 tmp = pci_mmio_readl(nicintel_spibar + EECD);
209 if ( (tmp & FLASH_WRITES_DISABLED) || !(tmp & FLASH_WRITES_ENABLED) ) {
210 msg_perr("Enabling flash write access failed.\n");
211 return 1;
212 }
213
214 if (register_shutdown(nicintel_spi_shutdown, NULL))
215 return 1;
216
217 return 0;
218 }
219
nicintel_spi_i210_enable_flash(void)220 static int nicintel_spi_i210_enable_flash(void)
221 {
222 uint32_t tmp;
223
224 tmp = pci_mmio_readl(nicintel_spibar + FLA);
225 if (tmp & BIT(FL_LOCKED)) {
226 msg_perr("Flash is in Secure Mode. Abort.\n");
227 return 1;
228 }
229
230 if (!(tmp & BIT(FL_ABORT)))
231 return 0;
232
233 tmp |= BIT(FL_CLR_ERR);
234 pci_mmio_writel(tmp, nicintel_spibar + FLA);
235 tmp = pci_mmio_readl(nicintel_spibar + FLA);
236 if (!(tmp & BIT(FL_ABORT))) {
237 msg_perr("Unable to clear Flash Access Error. Abort\n");
238 return 1;
239 }
240
241 return 0;
242 }
243
nicintel_spi_init(void)244 int nicintel_spi_init(void)
245 {
246 struct pci_dev *dev = NULL;
247
248 if (rget_io_perms())
249 return 1;
250
251 dev = pcidev_init(nics_intel_spi, PCI_BASE_ADDRESS_0);
252 if (!dev)
253 return 1;
254
255 uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
256 if (!io_base_addr)
257 return 1;
258
259 if ((dev->device_id & 0xfff0) == 0x1530) {
260 nicintel_spibar = rphysmap("Intel I210 Gigabit w/ SPI flash", io_base_addr + 0x12000,
261 MEMMAP_SIZE);
262 if (!nicintel_spibar || nicintel_spi_i210_enable_flash())
263 return 1;
264 } else if (dev->device_id < 0x10d8) {
265 nicintel_spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr,
266 MEMMAP_SIZE);
267 if (!nicintel_spibar || nicintel_spi_82599_enable_flash())
268 return 1;
269 } else {
270 nicintel_spibar = rphysmap("Intel 10 Gigabit NIC w/ SPI flash", io_base_addr + 0x10000,
271 MEMMAP_SIZE);
272 if (!nicintel_spibar || nicintel_spi_82599_enable_flash())
273 return 1;
274 }
275
276 if (register_spi_bitbang_master(&bitbang_spi_master_nicintel))
277 return 1;
278
279 return 0;
280 }
281