1 /*
2 * Copyright 2008 Veselin Georgiev,
3 * anrieffNOSPAM @ mgail_DOT.com (convert to gmail)
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <stdio.h>
28 #include <string.h>
29 #include <ctype.h>
30 #include "libcpuid.h"
31 #include "libcpuid_util.h"
32 #include "libcpuid_internal.h"
33 #include "recog_amd.h"
34
35 const struct amd_code_str { amd_code_t code; char *str; } amd_code_str[] = {
36 #define CODE(x) { x, #x }
37 #define CODE2(x, y) CODE(x)
38 #include "amd_code_t.h"
39 #undef CODE
40 };
41
42 struct amd_code_and_bits_t {
43 int code;
44 uint64_t bits;
45 };
46
47
48 const struct match_entry_t cpudb_amd[] = {
49 // F M S EF EM #cores L2$ L3$ BC ModelBits ModelCode Name
50 { -1, -1, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Unknown AMD CPU" },
51
52 /* 486 and the likes */
53 { 4, -1, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Unknown AMD 486" },
54 { 4, 3, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "AMD 486DX2" },
55 { 4, 7, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "AMD 486DX2WB" },
56 { 4, 8, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "AMD 486DX4" },
57 { 4, 9, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "AMD 486DX4WB" },
58
59 /* Pentia clones */
60 { 5, -1, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Unknown AMD 586" },
61 { 5, 0, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "K5" },
62 { 5, 1, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "K5" },
63 { 5, 2, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "K5" },
64 { 5, 3, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "K5" },
65
66 /* The K6 */
67 { 5, 6, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "K6" },
68 { 5, 7, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "K6" },
69
70 { 5, 8, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "K6-2" },
71 { 5, 9, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "K6-III" },
72 { 5, 10, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Unknown K6" },
73 { 5, 11, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Unknown K6" },
74 { 5, 12, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Unknown K6" },
75 { 5, 13, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "K6-2+" },
76
77 /* Athlon et al. */
78 { 6, 1, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Athlon (Slot-A)" },
79 { 6, 2, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Athlon (Slot-A)" },
80 { 6, 3, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Duron (Spitfire)" },
81 { 6, 4, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Athlon (ThunderBird)" },
82
83 { 6, 6, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Unknown Athlon" },
84 { 6, 6, -1, -1, -1, 1, -1, -1, NC, ATHLON_ , 0, "Athlon (Palomino)" },
85 { 6, 6, -1, -1, -1, 1, -1, -1, NC, ATHLON_|_MP_ , 0, "Athlon MP (Palomino)" },
86 { 6, 6, -1, -1, -1, 1, -1, -1, NC, DURON_ , 0, "Duron (Palomino)" },
87 { 6, 6, -1, -1, -1, 1, -1, -1, NC, ATHLON_|_XP_ , 0, "Athlon XP" },
88
89 { 6, 7, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Unknown Athlon XP" },
90 { 6, 7, -1, -1, -1, 1, -1, -1, NC, DURON_ , 0, "Duron (Morgan)" },
91
92 { 6, 8, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Athlon XP" },
93 { 6, 8, -1, -1, -1, 1, -1, -1, NC, ATHLON_ , 0, "Athlon XP (Thoroughbred)" },
94 { 6, 8, -1, -1, -1, 1, -1, -1, NC, ATHLON_|_XP_ , 0, "Athlon XP (Thoroughbred)" },
95 { 6, 8, -1, -1, -1, 1, -1, -1, NC, DURON_ , 0, "Duron (Applebred)" },
96 { 6, 8, -1, -1, -1, 1, -1, -1, NC, SEMPRON_ , 0, "Sempron (Thoroughbred)" },
97 { 6, 8, -1, -1, -1, 1, 128, -1, NC, SEMPRON_ , 0, "Sempron (Thoroughbred)" },
98 { 6, 8, -1, -1, -1, 1, 256, -1, NC, SEMPRON_ , 0, "Sempron (Thoroughbred)" },
99 { 6, 8, -1, -1, -1, 1, -1, -1, NC, ATHLON_|_MP_ , 0, "Athlon MP (Thoroughbred)" },
100 { 6, 8, -1, -1, -1, 1, -1, -1, NC, ATHLON_|_XP_|_M_ , 0, "Mobile Athlon (T-Bred)" },
101 { 6, 8, -1, -1, -1, 1, -1, -1, NC, ATHLON_|_XP_|_M_|_LV_, 0, "Mobile Athlon (T-Bred)" },
102
103 { 6, 10, -1, -1, -1, 1, -1, -1, NC, 0 , 0, "Athlon XP (Barton)" },
104 { 6, 10, -1, -1, -1, 1, 512, -1, NC, ATHLON_|_XP_ , 0, "Athlon XP (Barton)" },
105 { 6, 10, -1, -1, -1, 1, 512, -1, NC, SEMPRON_ , 0, "Sempron (Barton)" },
106 { 6, 10, -1, -1, -1, 1, 256, -1, NC, SEMPRON_ , 0, "Sempron (Thorton)" },
107 { 6, 10, -1, -1, -1, 1, 256, -1, NC, ATHLON_|_XP_ , 0, "Athlon XP (Thorton)" },
108 { 6, 10, -1, -1, -1, 1, -1, -1, NC, ATHLON_|_MP_ , 0, "Athlon MP (Barton)" },
109 { 6, 10, -1, -1, -1, 1, -1, -1, NC, ATHLON_|_XP_|_M_ , 0, "Mobile Athlon (Barton)" },
110 { 6, 10, -1, -1, -1, 1, -1, -1, NC, ATHLON_|_XP_|_M_|_LV_, 0, "Mobile Athlon (Barton)" },
111
112 /* K8 Architecture */
113 { 15, -1, -1, 15, -1, 1, -1, -1, NC, 0 , 0, "Unknown K8" },
114 { 15, -1, -1, 16, -1, 1, -1, -1, NC, 0 , 0, "Unknown K9" },
115
116 { 15, -1, -1, 15, -1, 1, -1, -1, NC, 0 , 0, "Unknown A64" },
117 { 15, -1, -1, 15, -1, 1, -1, -1, NC, OPTERON_ , 0, "Opteron" },
118 { 15, -1, -1, 15, -1, 2, -1, -1, NC, OPTERON_|_X2 , 0, "Opteron (Dual Core)" },
119 { 15, 3, -1, 15, -1, 1, -1, -1, NC, OPTERON_ , 0, "Opteron" },
120 { 15, 3, -1, 15, -1, 2, -1, -1, NC, OPTERON_|_X2 , 0, "Opteron (Dual Core)" },
121 { 15, -1, -1, 15, -1, 1, 512, -1, NC, ATHLON_|_64_ , 0, "Athlon 64 (512K)" },
122 { 15, -1, -1, 15, -1, 1, 1024, -1, NC, ATHLON_|_64_ , 0, "Athlon 64 (1024K)" },
123 { 15, -1, -1, 15, -1, 1, -1, -1, NC, ATHLON_|_FX , 0, "Athlon FX" },
124 { 15, -1, -1, 15, -1, 1, -1, -1, NC, ATHLON_|_64_|_FX , 0, "Athlon 64 FX" },
125 { 15, 3, -1, 15, 35, 2, -1, -1, NC, ATHLON_|_64_|_FX , 0, "Athlon 64 FX X2 (Toledo)" },
126 { 15, -1, -1, 15, -1, 2, 512, -1, NC, ATHLON_|_64_|_X2 , 0, "Athlon 64 X2 (512K)" },
127 { 15, -1, -1, 15, -1, 2, 1024, -1, NC, ATHLON_|_64_|_X2 , 0, "Athlon 64 X2 (1024K)" },
128 { 15, -1, -1, 15, -1, 1, 512, -1, NC, TURION_|_64_ , 0, "Turion 64 (512K)" },
129 { 15, -1, -1, 15, -1, 1, 1024, -1, NC, TURION_|_64_ , 0, "Turion 64 (1024K)" },
130 { 15, -1, -1, 15, -1, 2, 512, -1, NC, TURION_|_X2 , 0, "Turion 64 X2 (512K)" },
131 { 15, -1, -1, 15, -1, 2, 1024, -1, NC, TURION_|_X2 , 0, "Turion 64 X2 (1024K)" },
132 { 15, -1, -1, 15, -1, 1, 128, -1, NC, SEMPRON_ , 0, "A64 Sempron (128K)" },
133 { 15, -1, -1, 15, -1, 1, 256, -1, NC, SEMPRON_ , 0, "A64 Sempron (256K)" },
134 { 15, -1, -1, 15, -1, 1, 512, -1, NC, SEMPRON_ , 0, "A64 Sempron (512K)" },
135 { 15, -1, -1, 15, 0x4f, 1, 512, -1, NC, ATHLON_|_64_ , 0, "Athlon 64 (Orleans/512K)" },
136 { 15, -1, -1, 15, 0x5f, 1, 512, -1, NC, ATHLON_|_64_ , 0, "Athlon 64 (Orleans/512K)" },
137 { 15, -1, -1, 15, 0x2f, 1, 512, -1, NC, ATHLON_|_64_ , 0, "Athlon 64 (Venice/512K)" },
138 { 15, -1, -1, 15, 0x2c, 1, 512, -1, NC, ATHLON_|_64_ , 0, "Athlon 64 (Venice/512K)" },
139 { 15, -1, -1, 15, 0x1f, 1, 512, -1, NC, ATHLON_|_64_ , 0, "Athlon 64 (Winchester/512K)" },
140 { 15, -1, -1, 15, 0x0c, 1, 512, -1, NC, ATHLON_|_64_ , 0, "Athlon 64 (Newcastle/512K)" },
141 { 15, -1, -1, 15, 0x27, 1, 512, -1, NC, ATHLON_|_64_ , 0, "Athlon 64 (San Diego/512K)" },
142 { 15, -1, -1, 15, 0x37, 1, 512, -1, NC, ATHLON_|_64_ , 0, "Athlon 64 (San Diego/512K)" },
143 { 15, -1, -1, 15, 0x04, 1, 512, -1, NC, ATHLON_|_64_ , 0, "Athlon 64 (ClawHammer/512K)" },
144
145 { 15, -1, -1, 15, 0x5f, 1, 1024, -1, NC, ATHLON_|_64_ , 0, "Athlon 64 (Orleans/1024K)" },
146 { 15, -1, -1, 15, 0x27, 1, 1024, -1, NC, ATHLON_|_64_ , 0, "Athlon 64 (San Diego/1024K)" },
147 { 15, -1, -1, 15, 0x04, 1, 1024, -1, NC, ATHLON_|_64_ , 0, "Athlon 64 (ClawHammer/1024K)" },
148
149 { 15, -1, -1, 15, 0x4b, 2, 256, -1, NC, SEMPRON_ , 0, "Athlon 64 X2 (Windsor/256K)" },
150
151 { 15, -1, -1, 15, 0x23, 2, 512, -1, NC, ATHLON_|_64_|_X2 , 0, "Athlon 64 X2 (Toledo/512K)" },
152 { 15, -1, -1, 15, 0x4b, 2, 512, -1, NC, ATHLON_|_64_|_X2 , 0, "Athlon 64 X2 (Windsor/512K)" },
153 { 15, -1, -1, 15, 0x43, 2, 512, -1, NC, ATHLON_|_64_|_X2 , 0, "Athlon 64 X2 (Windsor/512K)" },
154 { 15, -1, -1, 15, 0x6b, 2, 512, -1, NC, ATHLON_|_64_|_X2 , 0, "Athlon 64 X2 (Brisbane/512K)" },
155 { 15, -1, -1, 15, 0x2b, 2, 512, -1, NC, ATHLON_|_64_|_X2 , 0, "Athlon 64 X2 (Manchester/512K)"},
156
157 { 15, -1, -1, 15, 0x23, 2, 1024, -1, NC, ATHLON_|_64_|_X2 , 0, "Athlon 64 X2 (Toledo/1024K)" },
158 { 15, -1, -1, 15, 0x43, 2, 1024, -1, NC, ATHLON_|_64_|_X2 , 0, "Athlon 64 X2 (Windsor/1024K)" },
159
160 { 15, -1, -1, 15, 0x08, 1, 128, -1, NC, MOBILE_|SEMPRON_ , 0, "Mobile Sempron 64 (Dublin/128K)"},
161 { 15, -1, -1, 15, 0x08, 1, 256, -1, NC, MOBILE_|SEMPRON_ , 0, "Mobile Sempron 64 (Dublin/256K)"},
162 { 15, -1, -1, 15, 0x0c, 1, 256, -1, NC, SEMPRON_ , 0, "Sempron 64 (Paris)" },
163 { 15, -1, -1, 15, 0x1c, 1, 128, -1, NC, SEMPRON_ , 0, "Sempron 64 (Palermo/128K)" },
164 { 15, -1, -1, 15, 0x1c, 1, 256, -1, NC, SEMPRON_ , 0, "Sempron 64 (Palermo/256K)" },
165 { 15, -1, -1, 15, 0x1c, 1, 128, -1, NC, MOBILE_| SEMPRON_ , 0, "Mobile Sempron 64 (Sonora/128K)"},
166 { 15, -1, -1, 15, 0x1c, 1, 256, -1, NC, MOBILE_| SEMPRON_ , 0, "Mobile Sempron 64 (Sonora/256K)"},
167 { 15, -1, -1, 15, 0x2c, 1, 128, -1, NC, SEMPRON_ , 0, "Sempron 64 (Palermo/128K)" },
168 { 15, -1, -1, 15, 0x2c, 1, 256, -1, NC, SEMPRON_ , 0, "Sempron 64 (Palermo/256K)" },
169 { 15, -1, -1, 15, 0x2c, 1, 128, -1, NC, MOBILE_| SEMPRON_ , 0, "Mobile Sempron 64 (Albany/128K)"},
170 { 15, -1, -1, 15, 0x2c, 1, 256, -1, NC, MOBILE_| SEMPRON_ , 0, "Mobile Sempron 64 (Albany/256K)"},
171 { 15, -1, -1, 15, 0x2f, 1, 128, -1, NC, SEMPRON_ , 0, "Sempron 64 (Palermo/128K)" },
172 { 15, -1, -1, 15, 0x2f, 1, 256, -1, NC, SEMPRON_ , 0, "Sempron 64 (Palermo/256K)" },
173 { 15, -1, -1, 15, 0x4f, 1, 128, -1, NC, SEMPRON_ , 0, "Sempron 64 (Manila/128K)" },
174 { 15, -1, -1, 15, 0x4f, 1, 256, -1, NC, SEMPRON_ , 0, "Sempron 64 (Manila/256K)" },
175 { 15, -1, -1, 15, 0x5f, 1, 128, -1, NC, SEMPRON_ , 0, "Sempron 64 (Manila/128K)" },
176 { 15, -1, -1, 15, 0x5f, 1, 256, -1, NC, SEMPRON_ , 0, "Sempron 64 (Manila/256K)" },
177 { 15, -1, -1, 15, 0x6b, 2, 256, -1, NC, SEMPRON_ , 0, "Sempron 64 Dual (Sherman/256K)"},
178 { 15, -1, -1, 15, 0x6b, 2, 512, -1, NC, SEMPRON_ , 0, "Sempron 64 Dual (Sherman/512K)"},
179 { 15, -1, -1, 15, 0x7f, 1, 256, -1, NC, SEMPRON_ , 0, "Sempron 64 (Sparta/256K)" },
180 { 15, -1, -1, 15, 0x7f, 1, 512, -1, NC, SEMPRON_ , 0, "Sempron 64 (Sparta/512K)" },
181 { 15, -1, -1, 15, 0x4c, 1, 256, -1, NC, MOBILE_| SEMPRON_ , 0, "Mobile Sempron 64 (Keene/256K)"},
182 { 15, -1, -1, 15, 0x4c, 1, 512, -1, NC, MOBILE_| SEMPRON_ , 0, "Mobile Sempron 64 (Keene/512K)"},
183 { 15, -1, -1, 15, -1, 2, -1, -1, NC, SEMPRON_ , 0, "Sempron Dual Core" },
184
185 { 15, -1, -1, 15, 0x24, 1, 512, -1, NC, TURION_|_64_ , 0, "Turion 64 (Lancaster/512K)" },
186 { 15, -1, -1, 15, 0x24, 1, 1024, -1, NC, TURION_|_64_ , 0, "Turion 64 (Lancaster/1024K)" },
187 { 15, -1, -1, 15, 0x48, 2, 256, -1, NC, TURION_|_X2 , 0, "Turion X2 (Taylor)" },
188 { 15, -1, -1, 15, 0x48, 2, 512, -1, NC, TURION_|_X2 , 0, "Turion X2 (Trinidad)" },
189 { 15, -1, -1, 15, 0x4c, 1, 512, -1, NC, TURION_|_64_ , 0, "Turion 64 (Richmond)" },
190 { 15, -1, -1, 15, 0x68, 2, 256, -1, NC, TURION_|_X2 , 0, "Turion X2 (Tyler/256K)" },
191 { 15, -1, -1, 15, 0x68, 2, 512, -1, NC, TURION_|_X2 , 0, "Turion X2 (Tyler/512K)" },
192 { 15, -1, -1, 17, 3, 2, 512, -1, NC, TURION_|_X2 , 0, "Turion X2 (Griffin/512K)" },
193 { 15, -1, -1, 17, 3, 2, 1024, -1, NC, TURION_|_X2 , 0, "Turion X2 (Griffin/1024K)" },
194
195 /* K10 Architecture (2007) */
196 { 15, -1, -1, 16, -1, 1, -1, -1, PHENOM, 0 , 0, "Unknown AMD Phenom" },
197 { 15, 2, -1, 16, -1, 1, -1, -1, PHENOM, 0 , 0, "Phenom" },
198 { 15, 2, -1, 16, -1, 3, -1, -1, PHENOM, 0 , 0, "Phenom X3 (Toliman)" },
199 { 15, 2, -1, 16, -1, 4, -1, -1, PHENOM, 0 , 0, "Phenom X4 (Agena)" },
200 { 15, 2, -1, 16, -1, 3, 512, -1, PHENOM, 0 , 0, "Phenom X3 (Toliman/256K)" },
201 { 15, 2, -1, 16, -1, 3, 512, -1, PHENOM, 0 , 0, "Phenom X3 (Toliman/512K)" },
202 { 15, 2, -1, 16, -1, 4, 128, -1, PHENOM, 0 , 0, "Phenom X4 (Agena/128K)" },
203 { 15, 2, -1, 16, -1, 4, 256, -1, PHENOM, 0 , 0, "Phenom X4 (Agena/256K)" },
204 { 15, 2, -1, 16, -1, 4, 512, -1, PHENOM, 0 , 0, "Phenom X4 (Agena/512K)" },
205 { 15, 2, -1, 16, -1, 2, 512, -1, NC, ATHLON_|_64_|_X2 , 0, "Athlon X2 (Kuma)" },
206 /* Phenom II derivates: */
207 { 15, 4, -1, 16, -1, 4, -1, -1, NC, 0 , 0, "Phenom (Deneb-based)" },
208 { 15, 4, -1, 16, -1, 1, 1024, -1, NC, SEMPRON_ , 0, "Sempron (Sargas)" },
209 { 15, 4, -1, 16, -1, 2, 512, -1, PHENOM2, 0 , 0, "Phenom II X2 (Callisto)" },
210 { 15, 4, -1, 16, -1, 3, 512, -1, PHENOM2, 0 , 0, "Phenom II X3 (Heka)" },
211 { 15, 4, -1, 16, -1, 4, 512, -1, PHENOM2, 0 , 0, "Phenom II X4" },
212 { 15, 4, -1, 16, 4, 4, 512, -1, PHENOM2, 0 , 0, "Phenom II X4 (Deneb)" },
213 { 15, 5, -1, 16, 5, 4, 512, -1, PHENOM2, 0 , 0, "Phenom II X4 (Deneb)" },
214 { 15, 4, -1, 16, 10, 4, 512, -1, PHENOM2, 0 , 0, "Phenom II X4 (Zosma)" },
215 { 15, 4, -1, 16, 10, 6, 512, -1, PHENOM2, 0 , 0, "Phenom II X6 (Thuban)" },
216 /* Athlon II derivates: */
217 { 15, 6, -1, 16, 6, 2, 512, -1, NC, ATHLON_|_X2 , 0, "Athlon II (Champlain)" },
218 { 15, 6, -1, 16, 6, 2, 512, -1, NC, ATHLON_|_64_|_X2 , 0, "Athlon II X2 (Regor)" },
219 { 15, 6, -1, 16, 6, 2, 1024, -1, NC, ATHLON_|_64_|_X2 , 0, "Athlon II X2 (Regor)" },
220 { 15, 5, -1, 16, 5, 3, 512, -1, NC, ATHLON_|_64_|_X3 , 0, "Athlon II X3 (Rana)" },
221 { 15, 5, -1, 16, 5, 4, 512, -1, NC, ATHLON_|_64_|_X4 , 0, "Athlon II X4 (Propus)" },
222 /* Llano APUs (2011): */
223 { 15, 1, -1, 18, 1, 2, -1, -1, FUSION_EA, 0 , 0, "Llano X2" },
224 { 15, 1, -1, 18, 1, 3, -1, -1, FUSION_EA, 0 , 0, "Llano X3" },
225 { 15, 1, -1, 18, 1, 4, -1, -1, FUSION_EA, 0 , 0, "Llano X4" },
226
227 /* Family 14h: Bobcat Architecture (2011) */
228 { 15, 2, -1, 20, -1, 1, -1, -1, FUSION_C, 0 , 0, "Brazos Ontario" },
229 { 15, 2, -1, 20, -1, 2, -1, -1, FUSION_C, 0 , 0, "Brazos Ontario (Dual-core)" },
230 { 15, 1, -1, 20, -1, 1, -1, -1, FUSION_E, 0 , 0, "Brazos Zacate" },
231 { 15, 1, -1, 20, -1, 2, -1, -1, FUSION_E, 0 , 0, "Brazos Zacate (Dual-core)" },
232 { 15, 2, -1, 20, -1, 2, -1, -1, FUSION_Z, 0 , 0, "Brazos Desna (Dual-core)" },
233
234 /* Family 15h: Bulldozer Architecture (2011) */
235 { 15, -1, -1, 21, 0, 4, -1, -1, NC, 0 , 0, "Bulldozer X2" },
236 { 15, -1, -1, 21, 1, 4, -1, -1, NC, 0 , 0, "Bulldozer X2" },
237 { 15, -1, -1, 21, 1, 6, -1, -1, NC, 0 , 0, "Bulldozer X3" },
238 { 15, -1, -1, 21, 1, 8, -1, -1, NC, 0 , 0, "Bulldozer X4" },
239 /* 2nd-gen, Piledriver core (2012): */
240 { 15, -1, -1, 21, 2, 4, -1, -1, NC, 0 , 0, "Vishera X2" },
241 { 15, -1, -1, 21, 2, 6, -1, -1, NC, 0 , 0, "Vishera X3" },
242 { 15, -1, -1, 21, 2, 8, -1, -1, NC, 0 , 0, "Vishera X4" },
243 { 15, 0, -1, 21, 16, 2, -1, -1, FUSION_A, 0 , 0, "Trinity X2" },
244 { 15, 0, -1, 21, 16, 4, -1, -1, FUSION_A, 0 , 0, "Trinity X4" },
245 { 15, 3, -1, 21, 19, 2, -1, -1, FUSION_A, 0 , 0, "Richland X2" },
246 { 15, 3, -1, 21, 19, 4, -1, -1, FUSION_A, 0 , 0, "Richland X4" },
247 /* 3rd-gen, Steamroller core (2014): */
248 { 15, 0, -1, 21, 48, 2, -1, -1, FUSION_A, 0 , 0, "Kaveri X2" },
249 { 15, 0, -1, 21, 48, 4, -1, -1, FUSION_A, 0 , 0, "Kaveri X4" },
250 { 15, 8, -1, 21, 56, 4, -1, -1, FUSION_A, 0 , 0, "Godavari X4" },
251 /* 4th-gen, Excavator core (2015): */
252 { 15, 1, -1, 21, 96, 2, -1, -1, FUSION_A, 0 , 0, "Carrizo X2" },
253 { 15, 1, -1, 21, 96, 4, -1, -1, FUSION_A, 0 , 0, "Carrizo X4" },
254 { 15, 5, -1, 21, 101, 2, -1, -1, FUSION_A, 0 , 0, "Bristol Ridge X2" },
255 { 15, 5, -1, 21, 101, 4, -1, -1, FUSION_A, 0 , 0, "Bristol Ridge X4" },
256 { 15, 0, -1, 21, 112, 2, -1, -1, FUSION_A, 0 , 0, "Stoney Ridge X2" },
257 { 15, 0, -1, 21, 112, 2, -1, -1, FUSION_E, 0 , 0, "Stoney Ridge X2" },
258
259 /* Family 16h: Jaguar Architecture (2013) */
260 { 15, 0, -1, 22, 0, 2, -1, -1, FUSION_A, 0 , 0, "Kabini X2" },
261 { 15, 0, -1, 22, 0, 4, -1, -1, FUSION_A, 0 , 0, "Kabini X4" },
262 /* 2nd-gen, Puma core (2013): */
263 { 15, 0, -1, 22, 48, 2, -1, -1, FUSION_E, 0 , 0, "Mullins X2" },
264 { 15, 0, -1, 22, 48, 4, -1, -1, FUSION_A, 0 , 0, "Mullins X4" },
265
266 /* Family 17h: Zen Architecture (2017) => https://en.wikichip.org/wiki/amd/microarchitectures/zen */
267 { 15, -1, -1, 23, 1, -1, -1, -1, NC, EPYC_ , 0, "EPYC (Naples)" },
268 { 15, -1, -1, 23, 1, -1, -1, -1, NC, RYZEN_TR_ , 0, "Threadripper (Whitehaven)" },
269 { 15, -1, -1, 23, 1, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Summit Ridge)" },
270 { 15, -1, -1, 23, 1, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Summit Ridge)" },
271 { 15, -1, -1, 23, 1, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Summit Ridge)" },
272 { 15, -1, -1, 23, 17, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Raven Ridge)" },
273 { 15, -1, -1, 23, 17, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Raven Ridge)" },
274 { 15, -1, -1, 23, 17, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Raven Ridge)" },
275 { 15, -1, -1, 23, 17, -1, -1, -1, NC, ATHLON_ , 0, "Athlon (Raven Ridge)" },
276 /* Zen+ (2018) => https://en.wikichip.org/wiki/amd/microarchitectures/zen%2B */
277 { 15, -1, -1, 23, 8, -1, -1, -1, NC, RYZEN_TR_ , 0, "Threadripper (Colfax)" },
278 { 15, -1, -1, 23, 8, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Pinnacle Ridge)" },
279 { 15, -1, -1, 23, 8, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Pinnacle Ridge)" },
280 { 15, -1, -1, 23, 8, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Pinnacle Ridge)" },
281 { 15, -1, -1, 23, 24, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Picasso)" },
282 { 15, -1, -1, 23, 24, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Picasso)" },
283 { 15, -1, -1, 23, 24, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Picasso)" },
284 { 15, -1, -1, 23, 24, -1, -1, -1, NC, ATHLON_ , 0, "Athlon (Picasso)" },
285 /* Zen 2 (2019) => https://en.wikichip.org/wiki/amd/microarchitectures/zen_2 */
286 { 15, -1, -1, 23, 49, -1, -1, -1, NC, EPYC_ , 0, "EPYC (Rome)" },
287 { 15, -1, -1, 23, 49, -1, -1, -1, NC, RYZEN_TR_ , 0, "Threadripper (Castle Peak)" },
288 { 15, -1, -1, 23, 113, -1, -1, -1, NC, RYZEN_|_9 , 0, "Ryzen 9 (Matisse)" },
289 { 15, -1, -1, 23, 113, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Matisse)" },
290 { 15, -1, -1, 23, 113, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Matisse)" },
291 { 15, -1, -1, 23, 113, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Matisse)" },
292 { 15, -1, -1, 23, 96, -1, -1, -1, NC, RYZEN_|_9 , 0, "Ryzen 9 (Renoir)" },
293 { 15, -1, -1, 23, 96, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Renoir)" },
294 { 15, -1, -1, 23, 96, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Renoir)" },
295 { 15, -1, -1, 23, 96, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Renoir)" },
296 /* Zen 3 (2020) => https://en.wikichip.org/wiki/amd/microarchitectures/zen_3 */
297 { 15, -1, -1, 25, 1, -1, -1, -1, NC, EPYC_ , 0, "EPYC (Milan)" },
298 { 15, -1, -1, 25, 33, -1, -1, -1, NC, RYZEN_|_9 , 0, "Ryzen 9 (Vermeer)" },
299 { 15, -1, -1, 25, 33, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Vermeer)" },
300 { 15, -1, -1, 25, 33, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Vermeer)" },
301 { 15, -1, -1, 25, 33, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Vermeer)" },
302 { 15, -1, -1, 25, 80, -1, -1, -1, NC, RYZEN_|_9 , 0, "Ryzen 9 (Cezanne)" },
303 { 15, -1, -1, 25, 80, -1, -1, -1, NC, RYZEN_|_7 , 0, "Ryzen 7 (Cezanne)" },
304 { 15, -1, -1, 25, 80, -1, -1, -1, NC, RYZEN_|_5 , 0, "Ryzen 5 (Cezanne)" },
305 { 15, -1, -1, 25, 80, -1, -1, -1, NC, RYZEN_|_3 , 0, "Ryzen 3 (Cezanne)" },
306 /* F M S EF EM #cores L2$ L3$ BC ModelBits ModelCode Name */
307
308 { 15, -1, -1, 24, 0, -1, -1, -1, NC, C86_|_7 , 0, "C86 7 (Dhyana)" },
309 { 15, -1, -1, 24, 0, -1, -1, -1, NC, C86_|_5 , 0, "C86 5 (Dhyana)" },
310 { 15, -1, -1, 24, 0, -1, -1, -1, NC, C86_|_3 , 0, "C86 3 (Dhyana)" },
311
312
313 /* Newer Opterons: */
314 { 15, 9, -1, 22, 9, 8, -1, -1, NC, OPTERON_ , 0, "Magny-Cours Opteron" },
315 };
316
317
load_amd_features(struct cpu_raw_data_t * raw,struct cpu_id_t * data)318 static void load_amd_features(struct cpu_raw_data_t* raw, struct cpu_id_t* data)
319 {
320 const struct feature_map_t matchtable_edx81[] = {
321 { 20, CPU_FEATURE_NX },
322 { 22, CPU_FEATURE_MMXEXT },
323 { 25, CPU_FEATURE_FXSR_OPT },
324 { 30, CPU_FEATURE_3DNOWEXT },
325 { 31, CPU_FEATURE_3DNOW },
326 };
327 const struct feature_map_t matchtable_ecx81[] = {
328 { 1, CPU_FEATURE_CMP_LEGACY },
329 { 2, CPU_FEATURE_SVM },
330 /* id 5 is handled in common */
331 { 6, CPU_FEATURE_SSE4A },
332 { 7, CPU_FEATURE_MISALIGNSSE },
333 { 8, CPU_FEATURE_3DNOWPREFETCH },
334 { 9, CPU_FEATURE_OSVW },
335 { 10, CPU_FEATURE_IBS },
336 { 11, CPU_FEATURE_XOP },
337 { 12, CPU_FEATURE_SKINIT },
338 { 13, CPU_FEATURE_WDT },
339 { 16, CPU_FEATURE_FMA4 },
340 { 21, CPU_FEATURE_TBM },
341 };
342 const struct feature_map_t matchtable_edx87[] = {
343 { 0, CPU_FEATURE_TS },
344 { 1, CPU_FEATURE_FID },
345 { 2, CPU_FEATURE_VID },
346 { 3, CPU_FEATURE_TTP },
347 { 4, CPU_FEATURE_TM_AMD },
348 { 5, CPU_FEATURE_STC },
349 { 6, CPU_FEATURE_100MHZSTEPS },
350 { 7, CPU_FEATURE_HWPSTATE },
351 /* id 8 is handled in common */
352 { 9, CPU_FEATURE_CPB },
353 { 10, CPU_FEATURE_APERFMPERF },
354 { 11, CPU_FEATURE_PFI },
355 { 12, CPU_FEATURE_PA },
356 };
357 if (raw->ext_cpuid[0][EAX] >= 0x80000001) {
358 match_features(matchtable_edx81, COUNT_OF(matchtable_edx81), raw->ext_cpuid[1][EDX], data);
359 match_features(matchtable_ecx81, COUNT_OF(matchtable_ecx81), raw->ext_cpuid[1][ECX], data);
360 }
361 if (raw->ext_cpuid[0][EAX] >= 0x80000007)
362 match_features(matchtable_edx87, COUNT_OF(matchtable_edx87), raw->ext_cpuid[7][EDX], data);
363 if (raw->ext_cpuid[0][EAX] >= 0x8000001a) {
364 /* We have the extended info about SSE unit size
365 Extracted from BKDG, about CPUID_Fn8000001A_EAX [Performance Optimization Identifiers] (Core::X86::Cpuid::PerfOptId):
366 - bit 2: FP256
367 - bit 1: MOVU
368 - bit 0: FP128 */
369 data->detection_hints[CPU_HINT_SSE_SIZE_AUTH] = 1;
370 if ((raw->ext_cpuid[0x1a][EAX] >> 2) & 1)
371 data->sse_size = 256;
372 else if ((raw->ext_cpuid[0x1a][EAX]) & 1)
373 data->sse_size = 128;
374 else
375 data->sse_size = 64;
376 }
377 }
378
decode_amd_cache_info(struct cpu_raw_data_t * raw,struct cpu_id_t * data)379 static void decode_amd_cache_info(struct cpu_raw_data_t* raw, struct cpu_id_t* data)
380 {
381 int l3_result, l3_assoc;
382 const int assoc_table[16] = {
383 0, 1, 2, 0, 4, 0, 8, 0, 16, 16, 32, 48, 64, 96, 128, 255
384 };
385 unsigned n = raw->ext_cpuid[0][EAX];
386
387 if (n >= 0x80000005) {
388 /* L1 Data Cache */
389 data->l1_data_cache = EXTRACTS_BITS(raw->ext_cpuid[5][ECX], 31, 24); // L1DcSize
390 data->l1_data_assoc = EXTRACTS_BITS(raw->ext_cpuid[5][ECX], 23, 16); // L1DcAssoc
391 data->l1_data_cacheline = EXTRACTS_BITS(raw->ext_cpuid[5][ECX], 7, 0); // L1DcLineSize
392
393 /* L1 Instruction Cache */
394 data->l1_instruction_cache = EXTRACTS_BITS(raw->ext_cpuid[5][EDX], 31, 24); // L1IcSize
395 data->l1_instruction_assoc = EXTRACTS_BITS(raw->ext_cpuid[5][EDX], 23, 16); // L1IcAssoc
396 data->l1_instruction_cacheline = EXTRACTS_BITS(raw->ext_cpuid[5][EDX], 7, 0); // L1IcLineSize
397 }
398 if (n >= 0x80000006) {
399 data->l2_cache = (raw->ext_cpuid[6][ECX] >> 16) & 0xffff;
400 data->l2_assoc = assoc_table[(raw->ext_cpuid[6][ECX] >> 12) & 0xf];
401 data->l2_cacheline = (raw->ext_cpuid[6][ECX]) & 0xff;
402
403 l3_result = (raw->ext_cpuid[6][EDX] >> 18);
404 if (l3_result > 0) {
405 l3_result = 512 * l3_result; /* AMD spec says it's a range,
406 but we take the lower bound */
407 l3_assoc = (raw->ext_cpuid[6][EDX] >> 12) & 0xf;
408 data->l3_cache = l3_result;
409
410 if(l3_assoc == 0x9) {
411 /* Since Zen 2, CPUID_Fn80000006_EDX[15:12] is invalid (0x9)
412 According to page 74 on
413 Processor Programming Reference (PPR) for AMD Family 17h Model 71h, Revision B0 Processors:
414 "There are insufficient available encodings to represent all possible L3
415 associativities. Please refer to Core::X86::Cpuid::CachePropEbx3[CacheNumWays]."
416 Note: we do not read CPUID_Fn80000001_ECX[22] (AKA TopologyExtensions) to allow backward compatibility with existing tests */
417 data->l3_assoc = EXTRACTS_BITS(raw->amd_fn8000001dh[0x3][EBX], 31, 22) + 1; // Cache number of ways is CacheNumWays + 1
418 data->l3_cacheline = EXTRACTS_BITS(raw->amd_fn8000001dh[0x3][EBX], 11, 0) + 1; // Cache line size in bytes is CacheLineSize + 1
419 } else {
420 data->l3_assoc = assoc_table[l3_assoc];
421 data->l3_cacheline = (raw->ext_cpuid[6][EDX]) & 0xff;
422 }
423 } else {
424 data->l3_cache = 0;
425 }
426 }
427 }
428
decode_amd_number_of_cores(struct cpu_raw_data_t * raw,struct cpu_id_t * data)429 static void decode_amd_number_of_cores(struct cpu_raw_data_t* raw, struct cpu_id_t* data)
430 {
431 int logical_cpus = -1, num_cores = -1;
432
433 if (raw->basic_cpuid[0][EAX] >= 1) {
434 logical_cpus = (raw->basic_cpuid[1][EBX] >> 16) & 0xff;
435 if (raw->ext_cpuid[0][EAX] >= 8) {
436 num_cores = 1 + (raw->ext_cpuid[8][ECX] & 0xff);
437 }
438 }
439 if (data->flags[CPU_FEATURE_HT]) {
440 if (num_cores > 1) {
441 if ((data->ext_family >= 23) && (raw->ext_cpuid[0][EAX] >= 30))
442 /* Ryzen 3 has SMT flag, but in fact cores count is equal to threads count.
443 Ryzen 5/7 reports twice as many "real" cores (e.g. 16 cores instead of 8) because of SMT. */
444 /* On PPR 17h, page 82:
445 CPUID_Fn8000001E_EBX [Core Identifiers][15:8] is ThreadsPerCore
446 ThreadsPerCore: [...] The number of threads per core is ThreadsPerCore+1 */
447 num_cores /= ((raw->ext_cpuid[30][EBX] >> 8) & 0xff) + 1;
448 data->num_cores = num_cores;
449 data->num_logical_cpus = logical_cpus;
450 } else {
451 data->num_cores = 1;
452 data->num_logical_cpus = (logical_cpus >= 2 ? logical_cpus : 2);
453 }
454 } else {
455 data->num_cores = data->num_logical_cpus = 1;
456 }
457 }
458
amd_has_turion_modelname(const char * bs)459 static int amd_has_turion_modelname(const char *bs)
460 {
461 /* We search for something like TL-60. Ahh, I miss regexes...*/
462 int i, l, k;
463 char code[3] = {0};
464 const char* codes[] = { "ML", "MT", "MK", "TK", "TL", "RM", "ZM", "" };
465 l = (int) strlen(bs);
466 for (i = 3; i < l - 2; i++) {
467 if (bs[i] == '-' &&
468 isupper(bs[i-1]) && isupper(bs[i-2]) && !isupper(bs[i-3]) &&
469 isdigit(bs[i+1]) && isdigit(bs[i+2]) && !isdigit(bs[i+3]))
470 {
471 code[0] = bs[i-2];
472 code[1] = bs[i-1];
473 for (k = 0; codes[k][0]; k++)
474 if (!strcmp(codes[k], code)) return 1;
475 }
476 }
477 return 0;
478 }
479
decode_amd_codename_part1(const char * bs)480 static struct amd_code_and_bits_t decode_amd_codename_part1(const char *bs)
481 {
482 amd_code_t code = (amd_code_t) NC;
483 struct amd_code_and_bits_t result;
484 uint64_t bits = 0;
485 int i = 0;
486
487 const struct { amd_code_t c; const char *search; } code_matchtable[] = {
488 { PHENOM2, "Phenom(tm) II" },
489 { PHENOM, "Phenom(tm)" },
490 { FUSION_C, "C-##" },
491 { FUSION_E, "E-###" },
492 { FUSION_Z, "Z-##" },
493 { FUSION_EA, "[EA]#-####" },
494 };
495
496 const struct { uint64_t bit; const char *search; } bit_matchtable[] = {
497 { _X2, "Dual[- ]Core" },
498 { _X2, " X2 " },
499 { _X3, " X3 " },
500 { _X4, " X4 " },
501 { OPTERON_, "Opteron" },
502 { ATHLON_, "Athlon" },
503 { SEMPRON_, "Sempron(tm)" },
504 { DURON_, "Duron" },
505 { _64_, " 64 " },
506 { _FX, " FX" },
507 { _MP_, " MP" },
508 { ATHLON_|_64_, "Athlon(tm) 64" },
509 { ATHLON_|_64_, "Athlon(tm) II X" },
510 { ATHLON_|_64_, "Athlon(tm) X#" },
511 { TURION_, "Turion" },
512 { MOBILE_, "[mM]obile" },
513 { _XP_, "XP" },
514 { _M_, "XP-M" },
515 { _LV_, "(LV)" },
516 { _APU_, " APU " },
517 { EPYC_, "EPYC" },
518 { RYZEN_TR_, "Ryzen Threadripper" },
519 { C86_, "C86" },
520 };
521
522 for (i = 0; i < COUNT_OF(bit_matchtable); i++) {
523 if (match_pattern(bs, bit_matchtable[i].search))
524 bits |= bit_matchtable[i].bit;
525 }
526 if (amd_has_turion_modelname(bs)) {
527 bits |= TURION_;
528 }
529 if ((i = match_pattern(bs, "Ryzen [3579]")) != 0) {
530 bits |= RYZEN_;
531 i--;
532 switch (bs[i + 6]) {
533 case '3': bits |= _3; break;
534 case '5': bits |= _5; break;
535 case '7': bits |= _7; break;
536 case '9': bits |= _9; break;
537 }
538 }
539
540 if ((i = match_pattern(bs, "C86 [357]")) != 0) {
541 bits |= C86_;
542 i--;
543 switch (bs[i + 6]) {
544 case '3': bits |= _3; break;
545 case '5': bits |= _5; break;
546 case '7': bits |= _7; break;
547 }
548 }
549
550 for (i = 0; i < COUNT_OF(code_matchtable); i++)
551 if (match_pattern(bs, code_matchtable[i].search)) {
552 code = code_matchtable[i].c;
553 break;
554 }
555
556 result.code = code;
557 result.bits = bits;
558 return result;
559 }
560
decode_amd_codename(struct cpu_raw_data_t * raw,struct cpu_id_t * data,struct internal_id_info_t * internal)561 static void decode_amd_codename(struct cpu_raw_data_t* raw, struct cpu_id_t* data, struct internal_id_info_t* internal)
562 {
563 struct amd_code_and_bits_t code_and_bits = decode_amd_codename_part1(data->brand_str);
564 int i = 0;
565 char* code_str = NULL;
566 int model_code = 0;
567
568 for (i = 0; i < COUNT_OF(amd_code_str); i++) {
569 if (code_and_bits.code == amd_code_str[i].code) {
570 code_str = amd_code_str[i].str;
571 break;
572 }
573 }
574 if (/*code == ATHLON_64_X2*/ match_all(code_and_bits.bits, ATHLON_|_64_|_X2) && data->l2_cache < 512) {
575 code_and_bits.bits &= ~(ATHLON_ | _64_);
576 code_and_bits.bits |= SEMPRON_;
577 }
578 if (code_str)
579 debugf(2, "Detected AMD brand code: %d (%s)\n", code_and_bits.code, code_str);
580 else
581 debugf(2, "Detected AMD brand code: %d\n", code_and_bits.code);
582
583 if (code_and_bits.bits) {
584 debugf(2, "Detected AMD bits: ");
585 debug_print_lbits(2, code_and_bits.bits);
586 }
587
588 internal->code.amd = code_and_bits.code;
589 internal->bits = code_and_bits.bits;
590 internal->score = match_cpu_codename(cpudb_amd, COUNT_OF(cpudb_amd), data, code_and_bits.code,
591 code_and_bits.bits, model_code);
592 }
593
cpuid_identify_amd(struct cpu_raw_data_t * raw,struct cpu_id_t * data,struct internal_id_info_t * internal)594 int cpuid_identify_amd(struct cpu_raw_data_t* raw, struct cpu_id_t* data, struct internal_id_info_t* internal)
595 {
596 load_amd_features(raw, data);
597 decode_amd_cache_info(raw, data);
598 decode_amd_number_of_cores(raw, data);
599 decode_amd_codename(raw, data, internal);
600 return 0;
601 }
602
cpuid_get_list_amd(struct cpu_list_t * list)603 void cpuid_get_list_amd(struct cpu_list_t* list)
604 {
605 generic_get_cpu_list(cpudb_amd, COUNT_OF(cpudb_amd), list);
606 }
607