1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2009
4 * Graeme Russ, <graeme.russ@gmail.com>
5 *
6 * (C) Copyright 2002
7 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
8 */
9
10 /*
11 * This file provides the interrupt handling functionality for systems
12 * based on the standard PC/AT architecture using two cascaded i8259
13 * Programmable Interrupt Controllers.
14 */
15
16 #include <common.h>
17 #include <log.h>
18 #include <asm/io.h>
19 #include <asm/i8259.h>
20 #include <asm/ibmpc.h>
21 #include <asm/interrupt.h>
22
i8259_init(void)23 int i8259_init(void)
24 {
25 u8 i;
26
27 /* Mask all interrupts */
28 outb(0xff, MASTER_PIC + IMR);
29 outb(0xff, SLAVE_PIC + IMR);
30
31 /*
32 * Master PIC
33 * Place master PIC interrupts at INT20
34 */
35 outb(ICW1_SEL | ICW1_EICW4, MASTER_PIC + ICW1);
36 outb(0x20, MASTER_PIC + ICW2);
37 outb(IR2, MASTER_PIC + ICW3);
38 outb(ICW4_PM, MASTER_PIC + ICW4);
39
40 for (i = 0; i < 8; i++)
41 outb(OCW2_SEOI | i, MASTER_PIC + OCW2);
42
43 /*
44 * Slave PIC
45 * Place slave PIC interrupts at INT28
46 */
47 outb(ICW1_SEL | ICW1_EICW4, SLAVE_PIC + ICW1);
48 outb(0x28, SLAVE_PIC + ICW2);
49 outb(0x02, SLAVE_PIC + ICW3);
50 outb(ICW4_PM, SLAVE_PIC + ICW4);
51
52 for (i = 0; i < 8; i++)
53 outb(OCW2_SEOI | i, SLAVE_PIC + OCW2);
54
55 /*
56 * Enable cascaded interrupts by unmasking the cascade IRQ pin of
57 * the master PIC
58 */
59 unmask_irq(2);
60
61 /* Interrupt 9 should be level triggered (SCI). The OS might do this */
62 configure_irq_trigger(9, true);
63
64 return 0;
65 }
66
mask_irq(int irq)67 void mask_irq(int irq)
68 {
69 int imr_port;
70
71 if (irq >= SYS_NUM_IRQS)
72 return;
73
74 if (irq > 7)
75 imr_port = SLAVE_PIC + IMR;
76 else
77 imr_port = MASTER_PIC + IMR;
78
79 outb(inb(imr_port) | (1 << (irq & 7)), imr_port);
80 }
81
unmask_irq(int irq)82 void unmask_irq(int irq)
83 {
84 int imr_port;
85
86 if (irq >= SYS_NUM_IRQS)
87 return;
88
89 if (irq > 7)
90 imr_port = SLAVE_PIC + IMR;
91 else
92 imr_port = MASTER_PIC + IMR;
93
94 outb(inb(imr_port) & ~(1 << (irq & 7)), imr_port);
95 }
96
specific_eoi(int irq)97 void specific_eoi(int irq)
98 {
99 if (irq >= SYS_NUM_IRQS)
100 return;
101
102 if (irq > 7) {
103 /*
104 * IRQ is on the slave - Issue a corresponding EOI to the
105 * slave PIC and an EOI for IRQ2 (the cascade interrupt)
106 * on the master PIC
107 */
108 outb(OCW2_SEOI | (irq & 7), SLAVE_PIC + OCW2);
109 irq = SEOI_IR2;
110 }
111
112 outb(OCW2_SEOI | irq, MASTER_PIC + OCW2);
113 }
114
configure_irq_trigger(int int_num,bool is_level_triggered)115 void configure_irq_trigger(int int_num, bool is_level_triggered)
116 {
117 u16 int_bits = inb(ELCR1) | (((u16)inb(ELCR2)) << 8);
118
119 debug("%s: current interrupts are 0x%x\n", __func__, int_bits);
120 if (is_level_triggered)
121 int_bits |= (1 << int_num);
122 else
123 int_bits &= ~(1 << int_num);
124
125 /* Write new values */
126 debug("%s: try to set interrupts 0x%x\n", __func__, int_bits);
127 outb((u8)(int_bits & 0xff), ELCR1);
128 outb((u8)(int_bits >> 8), ELCR2);
129 }
130