1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2008 Freescale Semiconductor, Inc.
4  *
5  * (C) Copyright 2000
6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7  */
8 
9 #include <common.h>
10 #include <asm/mmu.h>
11 
12 struct fsl_e_tlb_entry tlb_table[] = {
13 	/* TLB 0 - for temp stack in cache */
14 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
15 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
16 		      0, 0, BOOKE_PAGESZ_4K, 0),
17 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
18 		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
19 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
20 		      0, 0, BOOKE_PAGESZ_4K, 0),
21 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
22 		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
23 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
24 		      0, 0, BOOKE_PAGESZ_4K, 0),
25 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
26 		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
27 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
28 		      0, 0, BOOKE_PAGESZ_4K, 0),
29 
30 	/*
31 	 * TLB 0:	64M	Non-cacheable, guarded
32 	 * 0xfc000000	56M	unused
33 	 * 0xff800000	8M	boot FLASH
34 	 *	.... or ....
35 	 * 0xfc000000	64M	user flash
36 	 *
37 	 * Out of reset this entry is only 4K.
38 	 */
39 	SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000,
40 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
41 		      0, 0, BOOKE_PAGESZ_64M, 1),
42 
43 	/*
44 	 * TLB 1:	1G	Non-cacheable, guarded
45 	 * 0x80000000	512M	PCI1 MEM
46 	 * 0xa0000000	512M	PCIe MEM
47 	 */
48 	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
49 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
50 		      0, 1, BOOKE_PAGESZ_1G, 1),
51 
52 	/*
53 	 * TLB 2:	64M	Non-cacheable, guarded
54 	 * 0xe0000000	1M	CCSRBAR
55 	 * 0xe2000000	8M	PCI1 IO
56 	 * 0xe2800000	8M	PCIe IO
57 	 */
58 	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
59 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
60 		      0, 2, BOOKE_PAGESZ_64M, 1),
61 
62 #ifdef CONFIG_SYS_LBC_SDRAM_BASE
63 	/*
64 	 * TLB 3:	64M	Cacheable, non-guarded
65 	 * 0xf0000000	64M	LBC SDRAM First half
66 	 */
67 	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
68 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
69 		      0, 3, BOOKE_PAGESZ_64M, 1),
70 
71 	/*
72 	 * TLB 4:	64M	Cacheable, non-guarded
73 	 * 0xf4000000	64M	LBC SDRAM Second half
74 	 */
75 	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
76 		      CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
77 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
78 		      0, 4, BOOKE_PAGESZ_64M, 1),
79 #endif
80 
81 	/*
82 	 * TLB 5:	16M	Cacheable, non-guarded
83 	 * 0xf8000000	1M	7-segment LED display
84 	 * 0xf8100000	1M	User switches
85 	 * 0xf8300000	1M	Board revision
86 	 * 0xf8b00000	1M	EEPROM
87 	 */
88 	SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,
89 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
90 		      0, 5, BOOKE_PAGESZ_16M, 1),
91 
92 #ifndef CONFIG_SYS_ALT_BOOT
93 	/*
94 	 * TLB 6:	64M	Non-cacheable, guarded
95 	 * 0xec000000	64M	64MB user FLASH
96 	 */
97 	SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
98 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
99 		      0, 6, BOOKE_PAGESZ_64M, 1),
100 #else
101 	/*
102 	 * TLB 6:	4M	Non-cacheable, guarded
103 	 * 0xef800000	4M	1st 1/2 8MB soldered FLASH
104 	 */
105 	SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
106 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
107 		      0, 6, BOOKE_PAGESZ_4M, 1),
108 
109 	/*
110 	 * TLB 7:	4M	Non-cacheable, guarded
111 	 * 0xefc00000	4M	2nd half 8MB soldered FLASH
112 	 */
113 	SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000,
114 		      CONFIG_SYS_ALT_FLASH + 0x400000,
115 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
116 		      0, 7, BOOKE_PAGESZ_4M, 1),
117 #endif
118 
119 };
120 
121 int num_tlb_entries = ARRAY_SIZE(tlb_table);
122