1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2019 MediaTek Inc. 4 * Author: Sam Shih <sam.shih@mediatek.com> 5 */ 6 7/dts-v1/; 8#include "mt7622.dtsi" 9#include "mt7622-u-boot.dtsi" 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 model = "mt7622-rfb"; 15 compatible = "mediatek,mt7622", "mediatek,mt7622-rfb"; 16 chosen { 17 stdout-path = &uart0; 18 tick-timer = &timer0; 19 }; 20 21 aliases { 22 spi0 = &snor; 23 }; 24 25 memory@40000000 { 26 device_type = "memory"; 27 reg = <0x40000000 0x10000000>; 28 }; 29 30 reg_1p8v: regulator-1p8v { 31 compatible = "regulator-fixed"; 32 regulator-name = "fixed-1.8V"; 33 regulator-min-microvolt = <1800000>; 34 regulator-max-microvolt = <1800000>; 35 regulator-boot-on; 36 regulator-always-on; 37 }; 38 39 reg_3p3v: regulator-3p3v { 40 compatible = "regulator-fixed"; 41 regulator-name = "fixed-3.3V"; 42 regulator-min-microvolt = <3300000>; 43 regulator-max-microvolt = <3300000>; 44 regulator-boot-on; 45 regulator-always-on; 46 }; 47}; 48 49&pcie { 50 pinctrl-names = "default"; 51 pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>; 52 status = "okay"; 53 54 pcie@0,0 { 55 status = "okay"; 56 }; 57 58 pcie@1,0 { 59 status = "okay"; 60 }; 61}; 62 63&pinctrl { 64 pcie0_pins: pcie0-pins { 65 mux { 66 function = "pcie"; 67 groups = "pcie0_pad_perst", 68 "pcie0_1_waken", 69 "pcie0_1_clkreq"; 70 }; 71 }; 72 73 pcie1_pins: pcie1-pins { 74 mux { 75 function = "pcie"; 76 groups = "pcie1_pad_perst", 77 "pcie1_0_waken", 78 "pcie1_0_clkreq"; 79 }; 80 }; 81 82 snfi_pins: snfi-pins { 83 mux { 84 function = "flash"; 85 groups = "snfi"; 86 }; 87 }; 88 89 snor_pins: snor-pins { 90 mux { 91 function = "flash"; 92 groups = "spi_nor"; 93 }; 94 }; 95 96 uart0_pins: uart0 { 97 mux { 98 function = "uart"; 99 groups = "uart0_0_tx_rx" ; 100 }; 101 }; 102 103 watchdog_pins: watchdog-default { 104 mux { 105 function = "watchdog"; 106 groups = "watchdog"; 107 }; 108 }; 109 110 mmc0_pins_default: mmc0default { 111 mux { 112 function = "emmc"; 113 groups = "emmc"; 114 }; 115 116 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", 117 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4, 118 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively 119 */ 120 conf-cmd-dat { 121 pins = "NDL0", "NDL1", "NDL2", 122 "NDL3", "NDL4", "NDL5", 123 "NDL6", "NDL7", "NRB"; 124 input-enable; 125 bias-pull-up; 126 }; 127 128 conf-clk { 129 pins = "NCLE"; 130 bias-pull-down; 131 }; 132 133 }; 134 135 mmc1_pins_default: mmc1default { 136 mux { 137 function = "sd"; 138 groups = "sd_0"; 139 }; 140 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN", 141 * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1, 142 * DAT2, DAT3, CMD, CLK for SD respectively. 143 */ 144 conf-cmd-data { 145 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN", 146 "I2S2_IN","I2S4_OUT"; 147 input-enable; 148 drive-strength = <8>; 149 bias-pull-up; 150 }; 151 conf-clk { 152 pins = "I2S3_OUT"; 153 drive-strength = <12>; 154 bias-pull-down; 155 }; 156 conf-cd { 157 pins = "TXD3"; 158 bias-pull-up; 159 }; 160 161 }; 162}; 163 164&snfi { 165 pinctrl-names = "default", "snfi"; 166 pinctrl-0 = <&snor_pins>; 167 pinctrl-1 = <&snfi_pins>; 168 status = "disabled"; 169 170 spi-flash@0{ 171 compatible = "jedec,spi-nor"; 172 reg = <0>; 173 u-boot,dm-pre-reloc; 174 }; 175}; 176 177&snor { 178 pinctrl-names = "default"; 179 pinctrl-0 = <&snor_pins>; 180 status = "okay"; 181 182 spi-flash@0{ 183 compatible = "jedec,spi-nor"; 184 reg = <0>; 185 spi-tx-bus-width = <1>; 186 spi-rx-bus-width = <4>; 187 u-boot,dm-pre-reloc; 188 }; 189}; 190 191&uart0 { 192 pinctrl-names = "default"; 193 pinctrl-0 = <&uart0_pins>; 194 status = "okay"; 195}; 196 197&mmc0 { 198 pinctrl-names = "default"; 199 pinctrl-0 = <&mmc0_pins_default>; 200 status = "okay"; 201 bus-width = <8>; 202 max-frequency = <50000000>; 203 cap-sd-highspeed; 204 vmmc-supply = <®_3p3v>; 205 vqmmc-supply = <®_3p3v>; 206 non-removable; 207}; 208 209&mmc1 { 210 pinctrl-names = "default"; 211 pinctrl-0 = <&mmc1_pins_default>; 212 status = "okay"; 213 bus-width = <4>; 214 max-frequency = <50000000>; 215 cap-sd-highspeed; 216 r_smpl = <1>; 217 vmmc-supply = <®_3p3v>; 218 vqmmc-supply = <®_3p3v>; 219}; 220 221&watchdog { 222 pinctrl-names = "default"; 223 pinctrl-0 = <&watchdog_pins>; 224 status = "okay"; 225}; 226 227ð { 228 status = "okay"; 229 mediatek,gmac-id = <0>; 230 phy-mode = "sgmii"; 231 mediatek,switch = "mt7531"; 232 reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>; 233 234 fixed-link { 235 speed = <1000>; 236 full-duplex; 237 }; 238}; 239 240&ssusb { 241 status = "okay"; 242}; 243 244&u3phy { 245 status = "okay"; 246}; 247