1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 * Chao Fu (B44548@freescale.com)
9 * Haikun Wang (B53464@freescale.com)
10 */
11
12 #include <asm/global_data.h>
13 #include <linux/math64.h>
14 #include <common.h>
15 #include <dm.h>
16 #include <errno.h>
17 #include <common.h>
18 #include <log.h>
19 #include <spi.h>
20 #include <malloc.h>
21 #include <asm/io.h>
22 #include <fdtdec.h>
23 #ifndef CONFIG_M68K
24 #include <asm/arch/clock.h>
25 #endif
26 #include <fsl_dspi.h>
27 #include <linux/bitops.h>
28 #include <linux/delay.h>
29
30 /* linux/include/time.h */
31 #define NSEC_PER_SEC 1000000000L
32
33 DECLARE_GLOBAL_DATA_PTR;
34
35 /* fsl_dspi_plat flags */
36 #define DSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0)
37
38 /* idle data value */
39 #define DSPI_IDLE_VAL 0x0
40
41 /* max chipselect signals number */
42 #define FSL_DSPI_MAX_CHIPSELECT 6
43
44 /* default SCK frequency, unit: HZ */
45 #define FSL_DSPI_DEFAULT_SCK_FREQ 10000000
46
47 /* tx/rx data wait timeout value, unit: us */
48 #define DSPI_TXRX_WAIT_TIMEOUT 1000000
49
50 /* CTAR register pre-configure value */
51 #define DSPI_CTAR_DEFAULT_VALUE (DSPI_CTAR_TRSZ(7) | \
52 DSPI_CTAR_PCSSCK_1CLK | \
53 DSPI_CTAR_PASC(0) | \
54 DSPI_CTAR_PDT(0) | \
55 DSPI_CTAR_CSSCK(0) | \
56 DSPI_CTAR_ASC(0) | \
57 DSPI_CTAR_DT(0))
58
59 /* CTAR register pre-configure mask */
60 #define DSPI_CTAR_SET_MODE_MASK (DSPI_CTAR_TRSZ(15) | \
61 DSPI_CTAR_PCSSCK(3) | \
62 DSPI_CTAR_PASC(3) | \
63 DSPI_CTAR_PDT(3) | \
64 DSPI_CTAR_CSSCK(15) | \
65 DSPI_CTAR_ASC(15) | \
66 DSPI_CTAR_DT(15))
67
68 /**
69 * struct fsl_dspi_plat - platform data for Freescale DSPI
70 *
71 * @flags: Flags for DSPI DSPI_FLAG_...
72 * @speed_hz: Default SCK frequency
73 * @num_chipselect: Number of DSPI chipselect signals
74 * @regs_addr: Base address of DSPI registers
75 */
76 struct fsl_dspi_plat {
77 uint flags;
78 uint speed_hz;
79 uint num_chipselect;
80 fdt_addr_t regs_addr;
81 };
82
83 /**
84 * struct fsl_dspi_priv - private data for Freescale DSPI
85 *
86 * @flags: Flags for DSPI DSPI_FLAG_...
87 * @mode: SPI mode to use for slave device (see SPI mode flags)
88 * @mcr_val: MCR register configure value
89 * @bus_clk: DSPI input clk frequency
90 * @speed_hz: Default SCK frequency
91 * @charbit: How many bits in every transfer
92 * @num_chipselect: Number of DSPI chipselect signals
93 * @ctar_val: CTAR register configure value of per chipselect slave device
94 * @regs: Point to DSPI register structure for I/O access
95 */
96 struct fsl_dspi_priv {
97 uint flags;
98 uint mode;
99 uint mcr_val;
100 uint bus_clk;
101 uint speed_hz;
102 uint charbit;
103 uint num_chipselect;
104 uint ctar_val[FSL_DSPI_MAX_CHIPSELECT];
105 struct dspi *regs;
106 };
107
cpu_dspi_port_conf(void)108 __weak void cpu_dspi_port_conf(void)
109 {
110 }
111
cpu_dspi_claim_bus(uint bus,uint cs)112 __weak int cpu_dspi_claim_bus(uint bus, uint cs)
113 {
114 return 0;
115 }
116
cpu_dspi_release_bus(uint bus,uint cs)117 __weak void cpu_dspi_release_bus(uint bus, uint cs)
118 {
119 }
120
dspi_read32(uint flags,uint * addr)121 static uint dspi_read32(uint flags, uint *addr)
122 {
123 return flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ?
124 in_be32(addr) : in_le32(addr);
125 }
126
dspi_write32(uint flags,uint * addr,uint val)127 static void dspi_write32(uint flags, uint *addr, uint val)
128 {
129 flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ?
130 out_be32(addr, val) : out_le32(addr, val);
131 }
132
dspi_halt(struct fsl_dspi_priv * priv,u8 halt)133 static void dspi_halt(struct fsl_dspi_priv *priv, u8 halt)
134 {
135 uint mcr_val;
136
137 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
138
139 if (halt)
140 mcr_val |= DSPI_MCR_HALT;
141 else
142 mcr_val &= ~DSPI_MCR_HALT;
143
144 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
145 }
146
fsl_dspi_init_mcr(struct fsl_dspi_priv * priv,uint cfg_val)147 static void fsl_dspi_init_mcr(struct fsl_dspi_priv *priv, uint cfg_val)
148 {
149 /* halt DSPI module */
150 dspi_halt(priv, 1);
151
152 dspi_write32(priv->flags, &priv->regs->mcr, cfg_val);
153
154 /* resume module */
155 dspi_halt(priv, 0);
156
157 priv->mcr_val = cfg_val;
158 }
159
fsl_dspi_cfg_cs_active_state(struct fsl_dspi_priv * priv,uint cs,uint state)160 static void fsl_dspi_cfg_cs_active_state(struct fsl_dspi_priv *priv,
161 uint cs, uint state)
162 {
163 uint mcr_val;
164
165 dspi_halt(priv, 1);
166
167 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
168 if (state & SPI_CS_HIGH)
169 /* CSx inactive state is low */
170 mcr_val &= ~DSPI_MCR_PCSIS(cs);
171 else
172 /* CSx inactive state is high */
173 mcr_val |= DSPI_MCR_PCSIS(cs);
174 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
175
176 dspi_halt(priv, 0);
177 }
178
fsl_dspi_cfg_ctar_mode(struct fsl_dspi_priv * priv,uint cs,uint mode)179 static int fsl_dspi_cfg_ctar_mode(struct fsl_dspi_priv *priv,
180 uint cs, uint mode)
181 {
182 uint bus_setup;
183
184 bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]);
185
186 bus_setup &= ~DSPI_CTAR_SET_MODE_MASK;
187 bus_setup |= priv->ctar_val[cs];
188 bus_setup &= ~(DSPI_CTAR_CPOL | DSPI_CTAR_CPHA | DSPI_CTAR_LSBFE);
189
190 if (mode & SPI_CPOL)
191 bus_setup |= DSPI_CTAR_CPOL;
192 if (mode & SPI_CPHA)
193 bus_setup |= DSPI_CTAR_CPHA;
194 if (mode & SPI_LSB_FIRST)
195 bus_setup |= DSPI_CTAR_LSBFE;
196
197 dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup);
198
199 priv->charbit =
200 ((dspi_read32(priv->flags, &priv->regs->ctar[0]) &
201 DSPI_CTAR_TRSZ(15)) == DSPI_CTAR_TRSZ(15)) ? 16 : 8;
202
203 return 0;
204 }
205
fsl_dspi_clr_fifo(struct fsl_dspi_priv * priv)206 static void fsl_dspi_clr_fifo(struct fsl_dspi_priv *priv)
207 {
208 uint mcr_val;
209
210 dspi_halt(priv, 1);
211 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
212 /* flush RX and TX FIFO */
213 mcr_val |= (DSPI_MCR_CTXF | DSPI_MCR_CRXF);
214 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
215 dspi_halt(priv, 0);
216 }
217
dspi_tx(struct fsl_dspi_priv * priv,u32 ctrl,u16 data)218 static void dspi_tx(struct fsl_dspi_priv *priv, u32 ctrl, u16 data)
219 {
220 int timeout = DSPI_TXRX_WAIT_TIMEOUT;
221
222 /* wait for empty entries in TXFIFO or timeout */
223 while (DSPI_SR_TXCTR(dspi_read32(priv->flags, &priv->regs->sr)) >= 4 &&
224 timeout--)
225 udelay(1);
226
227 if (timeout >= 0)
228 dspi_write32(priv->flags, &priv->regs->tfr, (ctrl | data));
229 else
230 debug("dspi_tx: waiting timeout!\n");
231 }
232
dspi_rx(struct fsl_dspi_priv * priv)233 static u16 dspi_rx(struct fsl_dspi_priv *priv)
234 {
235 int timeout = DSPI_TXRX_WAIT_TIMEOUT;
236
237 /* wait for valid entries in RXFIFO or timeout */
238 while (DSPI_SR_RXCTR(dspi_read32(priv->flags, &priv->regs->sr)) == 0 &&
239 timeout--)
240 udelay(1);
241
242 if (timeout >= 0)
243 return (u16)DSPI_RFR_RXDATA(
244 dspi_read32(priv->flags, &priv->regs->rfr));
245 else {
246 debug("dspi_rx: waiting timeout!\n");
247 return (u16)(~0);
248 }
249 }
250
dspi_xfer(struct fsl_dspi_priv * priv,uint cs,unsigned int bitlen,const void * dout,void * din,unsigned long flags)251 static int dspi_xfer(struct fsl_dspi_priv *priv, uint cs, unsigned int bitlen,
252 const void *dout, void *din, unsigned long flags)
253 {
254 u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
255 u8 *spi_rd = NULL, *spi_wr = NULL;
256 static u32 ctrl;
257 uint len = bitlen >> 3;
258
259 if (priv->charbit == 16) {
260 bitlen >>= 1;
261 spi_wr16 = (u16 *)dout;
262 spi_rd16 = (u16 *)din;
263 } else {
264 spi_wr = (u8 *)dout;
265 spi_rd = (u8 *)din;
266 }
267
268 if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
269 ctrl |= DSPI_TFR_CONT;
270
271 ctrl = ctrl & DSPI_TFR_CONT;
272 ctrl = ctrl | DSPI_TFR_CTAS(0) | DSPI_TFR_PCS(cs);
273
274 if (len > 1) {
275 int tmp_len = len - 1;
276 while (tmp_len--) {
277 if ((dout != NULL) && (din != NULL)) {
278 if (priv->charbit == 16) {
279 dspi_tx(priv, ctrl, *spi_wr16++);
280 *spi_rd16++ = dspi_rx(priv);
281 }
282 else {
283 dspi_tx(priv, ctrl, *spi_wr++);
284 *spi_rd++ = dspi_rx(priv);
285 }
286 }
287
288 else if (dout != NULL) {
289 if (priv->charbit == 16)
290 dspi_tx(priv, ctrl, *spi_wr16++);
291 else
292 dspi_tx(priv, ctrl, *spi_wr++);
293 dspi_rx(priv);
294 }
295
296 else if (din != NULL) {
297 dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
298 if (priv->charbit == 16)
299 *spi_rd16++ = dspi_rx(priv);
300 else
301 *spi_rd++ = dspi_rx(priv);
302 }
303 }
304
305 len = 1; /* remaining byte */
306 }
307
308 if ((flags & SPI_XFER_END) == SPI_XFER_END)
309 ctrl &= ~DSPI_TFR_CONT;
310
311 if (len) {
312 if ((dout != NULL) && (din != NULL)) {
313 if (priv->charbit == 16) {
314 dspi_tx(priv, ctrl, *spi_wr16++);
315 *spi_rd16++ = dspi_rx(priv);
316 }
317 else {
318 dspi_tx(priv, ctrl, *spi_wr++);
319 *spi_rd++ = dspi_rx(priv);
320 }
321 }
322
323 else if (dout != NULL) {
324 if (priv->charbit == 16)
325 dspi_tx(priv, ctrl, *spi_wr16);
326 else
327 dspi_tx(priv, ctrl, *spi_wr);
328 dspi_rx(priv);
329 }
330
331 else if (din != NULL) {
332 dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
333 if (priv->charbit == 16)
334 *spi_rd16 = dspi_rx(priv);
335 else
336 *spi_rd = dspi_rx(priv);
337 }
338 } else {
339 /* dummy read */
340 dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
341 dspi_rx(priv);
342 }
343
344 return 0;
345 }
346
347 /**
348 * Calculate the divide value between input clk frequency and expected SCK frequency
349 * Formula: SCK = (clkrate/pbr) x ((1+dbr)/br)
350 * Dbr: use default value 0
351 *
352 * @pbr: return Baud Rate Prescaler value
353 * @br: return Baud Rate Scaler value
354 * @speed_hz: expected SCK frequency
355 * @clkrate: input clk frequency
356 */
fsl_dspi_hz_to_spi_baud(int * pbr,int * br,int speed_hz,uint clkrate)357 static int fsl_dspi_hz_to_spi_baud(int *pbr, int *br,
358 int speed_hz, uint clkrate)
359 {
360 /* Valid baud rate pre-scaler values */
361 int pbr_tbl[4] = {2, 3, 5, 7};
362 int brs[16] = {2, 4, 6, 8,
363 16, 32, 64, 128,
364 256, 512, 1024, 2048,
365 4096, 8192, 16384, 32768};
366 int temp, i = 0, j = 0;
367
368 temp = clkrate / speed_hz;
369
370 for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++)
371 for (j = 0; j < ARRAY_SIZE(brs); j++) {
372 if (pbr_tbl[i] * brs[j] >= temp) {
373 *pbr = i;
374 *br = j;
375 return 0;
376 }
377 }
378
379 debug("Can not find valid baud rate,speed_hz is %d, ", speed_hz);
380 debug("clkrate is %d, we use the max prescaler value.\n", clkrate);
381
382 *pbr = ARRAY_SIZE(pbr_tbl) - 1;
383 *br = ARRAY_SIZE(brs) - 1;
384 return -EINVAL;
385 }
386
ns_delay_scale(unsigned char * psc,unsigned char * sc,int delay_ns,unsigned long clkrate)387 static void ns_delay_scale(unsigned char *psc, unsigned char *sc, int delay_ns,
388 unsigned long clkrate)
389 {
390 int scale_needed, scale, minscale = INT_MAX;
391 int pscale_tbl[4] = {1, 3, 5, 7};
392 u32 remainder;
393 int i, j;
394
395 scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
396 &remainder);
397 if (remainder)
398 scale_needed++;
399
400 for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
401 for (j = 0; j <= DSPI_CTAR_SCALE_BITS; j++) {
402 scale = pscale_tbl[i] * (2 << j);
403 if (scale >= scale_needed) {
404 if (scale < minscale) {
405 minscale = scale;
406 *psc = i;
407 *sc = j;
408 }
409 break;
410 }
411 }
412
413 if (minscale == INT_MAX) {
414 pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
415 delay_ns, clkrate);
416 *psc = ARRAY_SIZE(pscale_tbl) - 1;
417 *sc = DSPI_CTAR_SCALE_BITS;
418 }
419 }
420
fsl_dspi_cfg_speed(struct fsl_dspi_priv * priv,uint speed)421 static int fsl_dspi_cfg_speed(struct fsl_dspi_priv *priv, uint speed)
422 {
423 int ret;
424 uint bus_setup;
425 int best_i, best_j, bus_clk;
426
427 bus_clk = priv->bus_clk;
428
429 debug("DSPI set_speed: expected SCK speed %u, bus_clk %u.\n",
430 speed, bus_clk);
431
432 bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]);
433 bus_setup &= ~(DSPI_CTAR_DBR | DSPI_CTAR_PBR(0x3) | DSPI_CTAR_BR(0xf));
434
435 ret = fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk);
436 if (ret) {
437 speed = priv->speed_hz;
438 debug("DSPI set_speed use default SCK rate %u.\n", speed);
439 fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk);
440 }
441
442 bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
443 dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup);
444
445 priv->speed_hz = speed;
446
447 return 0;
448 }
449
fsl_dspi_child_pre_probe(struct udevice * dev)450 static int fsl_dspi_child_pre_probe(struct udevice *dev)
451 {
452 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
453 struct fsl_dspi_priv *priv = dev_get_priv(dev->parent);
454 u32 cs_sck_delay = 0, sck_cs_delay = 0;
455 unsigned char pcssck = 0, cssck = 0;
456 unsigned char pasc = 0, asc = 0;
457
458 if (slave_plat->cs >= priv->num_chipselect) {
459 debug("DSPI invalid chipselect number %d(max %d)!\n",
460 slave_plat->cs, priv->num_chipselect - 1);
461 return -EINVAL;
462 }
463
464 ofnode_read_u32(dev_ofnode(dev), "fsl,spi-cs-sck-delay",
465 &cs_sck_delay);
466 ofnode_read_u32(dev_ofnode(dev), "fsl,spi-sck-cs-delay",
467 &sck_cs_delay);
468
469 /* Set PCS to SCK delay scale values */
470 ns_delay_scale(&pcssck, &cssck, cs_sck_delay, priv->bus_clk);
471
472 /* Set After SCK delay scale values */
473 ns_delay_scale(&pasc, &asc, sck_cs_delay, priv->bus_clk);
474
475 priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE |
476 DSPI_CTAR_PCSSCK(pcssck) |
477 DSPI_CTAR_PASC(pasc);
478
479 debug("DSPI pre_probe slave device on CS %u, max_hz %u, mode 0x%x.\n",
480 slave_plat->cs, slave_plat->max_hz, slave_plat->mode);
481
482 return 0;
483 }
484
fsl_dspi_probe(struct udevice * bus)485 static int fsl_dspi_probe(struct udevice *bus)
486 {
487 struct fsl_dspi_plat *plat = dev_get_plat(bus);
488 struct fsl_dspi_priv *priv = dev_get_priv(bus);
489 struct dm_spi_bus *dm_spi_bus;
490 uint mcr_cfg_val;
491
492 dm_spi_bus = dev_get_uclass_priv(bus);
493
494 /* cpu speical pin muxing configure */
495 cpu_dspi_port_conf();
496
497 /* get input clk frequency */
498 priv->regs = (struct dspi *)plat->regs_addr;
499 priv->flags = plat->flags;
500 #ifdef CONFIG_M68K
501 priv->bus_clk = gd->bus_clk;
502 #else
503 priv->bus_clk = mxc_get_clock(MXC_DSPI_CLK);
504 #endif
505 priv->num_chipselect = plat->num_chipselect;
506 priv->speed_hz = plat->speed_hz;
507 /* frame data length in bits, default 8bits */
508 priv->charbit = 8;
509
510 dm_spi_bus->max_hz = plat->speed_hz;
511
512 /* default: all CS signals inactive state is high */
513 mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
514 DSPI_MCR_CRXF | DSPI_MCR_CTXF;
515 fsl_dspi_init_mcr(priv, mcr_cfg_val);
516
517 debug("%s probe done, bus-num %d.\n", bus->name, dev_seq(bus));
518
519 return 0;
520 }
521
fsl_dspi_claim_bus(struct udevice * dev)522 static int fsl_dspi_claim_bus(struct udevice *dev)
523 {
524 uint sr_val;
525 struct fsl_dspi_priv *priv;
526 struct udevice *bus = dev->parent;
527 struct dm_spi_slave_plat *slave_plat =
528 dev_get_parent_plat(dev);
529
530 priv = dev_get_priv(bus);
531
532 /* processor special preparation work */
533 cpu_dspi_claim_bus(dev_seq(bus), slave_plat->cs);
534
535 /* configure transfer mode */
536 fsl_dspi_cfg_ctar_mode(priv, slave_plat->cs, priv->mode);
537
538 /* configure active state of CSX */
539 fsl_dspi_cfg_cs_active_state(priv, slave_plat->cs,
540 priv->mode);
541
542 fsl_dspi_clr_fifo(priv);
543
544 /* check module TX and RX status */
545 sr_val = dspi_read32(priv->flags, &priv->regs->sr);
546 if ((sr_val & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) {
547 debug("DSPI RX/TX not ready!\n");
548 return -EIO;
549 }
550
551 return 0;
552 }
553
fsl_dspi_release_bus(struct udevice * dev)554 static int fsl_dspi_release_bus(struct udevice *dev)
555 {
556 struct udevice *bus = dev->parent;
557 struct fsl_dspi_priv *priv = dev_get_priv(bus);
558 struct dm_spi_slave_plat *slave_plat =
559 dev_get_parent_plat(dev);
560
561 /* halt module */
562 dspi_halt(priv, 1);
563
564 /* processor special release work */
565 cpu_dspi_release_bus(dev_seq(bus), slave_plat->cs);
566
567 return 0;
568 }
569
570 /**
571 * This function doesn't do anything except help with debugging
572 */
fsl_dspi_bind(struct udevice * bus)573 static int fsl_dspi_bind(struct udevice *bus)
574 {
575 debug("%s assigned seq %d.\n", bus->name, dev_seq(bus));
576 return 0;
577 }
578
fsl_dspi_of_to_plat(struct udevice * bus)579 static int fsl_dspi_of_to_plat(struct udevice *bus)
580 {
581 fdt_addr_t addr;
582 struct fsl_dspi_plat *plat = dev_get_plat(bus);
583 const void *blob = gd->fdt_blob;
584 int node = dev_of_offset(bus);
585
586 if (fdtdec_get_bool(blob, node, "big-endian"))
587 plat->flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG;
588
589 plat->num_chipselect =
590 fdtdec_get_int(blob, node, "num-cs", FSL_DSPI_MAX_CHIPSELECT);
591
592 addr = dev_read_addr(bus);
593 if (addr == FDT_ADDR_T_NONE) {
594 debug("DSPI: Can't get base address or size\n");
595 return -ENOMEM;
596 }
597 plat->regs_addr = addr;
598
599 plat->speed_hz = fdtdec_get_int(blob,
600 node, "spi-max-frequency", FSL_DSPI_DEFAULT_SCK_FREQ);
601
602 debug("DSPI: regs=%pa, max-frequency=%d, endianess=%s, num-cs=%d\n",
603 &plat->regs_addr, plat->speed_hz,
604 plat->flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le",
605 plat->num_chipselect);
606
607 return 0;
608 }
609
fsl_dspi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)610 static int fsl_dspi_xfer(struct udevice *dev, unsigned int bitlen,
611 const void *dout, void *din, unsigned long flags)
612 {
613 struct fsl_dspi_priv *priv;
614 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
615 struct udevice *bus;
616
617 bus = dev->parent;
618 priv = dev_get_priv(bus);
619
620 return dspi_xfer(priv, slave_plat->cs, bitlen, dout, din, flags);
621 }
622
fsl_dspi_set_speed(struct udevice * bus,uint speed)623 static int fsl_dspi_set_speed(struct udevice *bus, uint speed)
624 {
625 struct fsl_dspi_priv *priv = dev_get_priv(bus);
626
627 return fsl_dspi_cfg_speed(priv, speed);
628 }
629
fsl_dspi_set_mode(struct udevice * bus,uint mode)630 static int fsl_dspi_set_mode(struct udevice *bus, uint mode)
631 {
632 struct fsl_dspi_priv *priv = dev_get_priv(bus);
633
634 debug("DSPI set_mode: mode 0x%x.\n", mode);
635
636 /*
637 * We store some chipselect special configure value in priv->ctar_val,
638 * and we can't get the correct chipselect number here,
639 * so just store mode value.
640 * Do really configuration when claim_bus.
641 */
642 priv->mode = mode;
643
644 return 0;
645 }
646
647 static const struct dm_spi_ops fsl_dspi_ops = {
648 .claim_bus = fsl_dspi_claim_bus,
649 .release_bus = fsl_dspi_release_bus,
650 .xfer = fsl_dspi_xfer,
651 .set_speed = fsl_dspi_set_speed,
652 .set_mode = fsl_dspi_set_mode,
653 };
654
655 static const struct udevice_id fsl_dspi_ids[] = {
656 { .compatible = "fsl,vf610-dspi" },
657 { }
658 };
659
660 U_BOOT_DRIVER(fsl_dspi) = {
661 .name = "fsl_dspi",
662 .id = UCLASS_SPI,
663 .of_match = fsl_dspi_ids,
664 .ops = &fsl_dspi_ops,
665 .of_to_plat = fsl_dspi_of_to_plat,
666 .plat_auto = sizeof(struct fsl_dspi_plat),
667 .priv_auto = sizeof(struct fsl_dspi_priv),
668 .probe = fsl_dspi_probe,
669 .child_pre_probe = fsl_dspi_child_pre_probe,
670 .bind = fsl_dspi_bind,
671 };
672