1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2007 Freescale Semiconductor, Inc.
4 *
5 * Author: Scott Wood <scottwood@freescale.com>
6 * Dave Liu <daveliu@freescale.com>
7 */
8
9 #include <common.h>
10 #include <hwconfig.h>
11 #include <i2c.h>
12 #include <init.h>
13 #include <net.h>
14 #include <asm/global_data.h>
15 #include <linux/delay.h>
16 #include <linux/libfdt.h>
17 #include <fdt_support.h>
18 #include <pci.h>
19 #include <mpc83xx.h>
20 #include <netdev.h>
21 #include <asm/io.h>
22 #include <ns16550.h>
23 #include <nand.h>
24
25 DECLARE_GLOBAL_DATA_PTR;
26
board_early_init_f(void)27 int board_early_init_f(void)
28 {
29 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
30
31 if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
32 gd->flags |= GD_FLG_SILENT;
33
34 return 0;
35 }
36
37 #ifndef CONFIG_NAND_SPL
38
read_board_info(void)39 static u8 read_board_info(void)
40 {
41 u8 val8;
42 i2c_set_bus_num(0);
43
44 if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
45 return val8;
46 else
47 return 0;
48 }
49
checkboard(void)50 int checkboard(void)
51 {
52 static const char * const rev_str[] = {
53 "0.0",
54 "0.1",
55 "1.0",
56 "1.1",
57 "<unknown>",
58 };
59 u8 info;
60 int i;
61
62 info = read_board_info();
63 i = (!info) ? 4: info & 0x03;
64
65 printf("Board: Freescale MPC8315ERDB Rev %s\n", rev_str[i]);
66
67 return 0;
68 }
69
70 static struct pci_region pci_regions[] = {
71 {
72 bus_start: CONFIG_SYS_PCI_MEM_BASE,
73 phys_start: CONFIG_SYS_PCI_MEM_PHYS,
74 size: CONFIG_SYS_PCI_MEM_SIZE,
75 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
76 },
77 {
78 bus_start: CONFIG_SYS_PCI_MMIO_BASE,
79 phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
80 size: CONFIG_SYS_PCI_MMIO_SIZE,
81 flags: PCI_REGION_MEM
82 },
83 {
84 bus_start: CONFIG_SYS_PCI_IO_BASE,
85 phys_start: CONFIG_SYS_PCI_IO_PHYS,
86 size: CONFIG_SYS_PCI_IO_SIZE,
87 flags: PCI_REGION_IO
88 }
89 };
90
91 static struct pci_region pcie_regions_0[] = {
92 {
93 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
94 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
95 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
96 .flags = PCI_REGION_MEM,
97 },
98 {
99 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
100 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
101 .size = CONFIG_SYS_PCIE1_IO_SIZE,
102 .flags = PCI_REGION_IO,
103 },
104 };
105
106 static struct pci_region pcie_regions_1[] = {
107 {
108 .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
109 .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
110 .size = CONFIG_SYS_PCIE2_MEM_SIZE,
111 .flags = PCI_REGION_MEM,
112 },
113 {
114 .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
115 .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
116 .size = CONFIG_SYS_PCIE2_IO_SIZE,
117 .flags = PCI_REGION_IO,
118 },
119 };
120
pci_init_board(void)121 void pci_init_board(void)
122 {
123 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
124 volatile sysconf83xx_t *sysconf = &immr->sysconf;
125 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
126 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
127 volatile law83xx_t *pcie_law = sysconf->pcielaw;
128 struct pci_region *reg[] = { pci_regions };
129 struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
130
131 /* Enable all 3 PCI_CLK_OUTPUTs. */
132 clk->occr |= 0xe0000000;
133
134 /*
135 * Configure PCI Local Access Windows
136 */
137 pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
138 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
139
140 pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
141 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
142
143 mpc83xx_pci_init(1, reg);
144
145 /* Configure the clock for PCIE controller */
146 clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
147 SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
148
149 /* Deassert the resets in the control register */
150 out_be32(&sysconf->pecr1, 0xE0008000);
151 out_be32(&sysconf->pecr2, 0xE0008000);
152 udelay(2000);
153
154 /* Configure PCI Express Local Access Windows */
155 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
156 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
157
158 out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
159 out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
160
161 mpc83xx_pcie_init(2, pcie_reg);
162 }
163
164 #if defined(CONFIG_OF_BOARD_SETUP)
fdt_tsec1_fixup(void * fdt,struct bd_info * bd)165 void fdt_tsec1_fixup(void *fdt, struct bd_info *bd)
166 {
167 const char disabled[] = "disabled";
168 const char *path;
169 int ret;
170
171 if (hwconfig_arg_cmp("board_type", "tsec1")) {
172 return;
173 } else if (!hwconfig_arg_cmp("board_type", "ulpi")) {
174 printf("NOTICE: No or unknown board_type hwconfig specified.\n"
175 " Assuming board with TSEC1.\n");
176 return;
177 }
178
179 ret = fdt_path_offset(fdt, "/aliases");
180 if (ret < 0) {
181 printf("WARNING: can't find /aliases node\n");
182 return;
183 }
184
185 path = fdt_getprop(fdt, ret, "ethernet0", NULL);
186 if (!path) {
187 printf("WARNING: can't find ethernet0 alias\n");
188 return;
189 }
190
191 do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1);
192 }
193
ft_board_setup(void * blob,struct bd_info * bd)194 int ft_board_setup(void *blob, struct bd_info *bd)
195 {
196 ft_cpu_setup(blob, bd);
197 #ifdef CONFIG_PCI
198 ft_pci_setup(blob, bd);
199 #endif
200 fsl_fdt_fixup_dr_usb(blob, bd);
201 fdt_tsec1_fixup(blob, bd);
202
203 return 0;
204 }
205 #endif
206
board_eth_init(struct bd_info * bis)207 int board_eth_init(struct bd_info *bis)
208 {
209 cpu_eth_init(bis); /* Initialize TSECs first */
210 return pci_eth_init(bis);
211 }
212
213 #else /* CONFIG_NAND_SPL */
214
checkboard(void)215 int checkboard(void)
216 {
217 puts("Board: Freescale MPC8315ERDB\n");
218 return 0;
219 }
220
board_init_f(ulong bootflag)221 void board_init_f(ulong bootflag)
222 {
223 board_early_init_f();
224 ns16550_init((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500),
225 CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
226 puts("NAND boot... ");
227 timer_init();
228 dram_init();
229 relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
230 CONFIG_SYS_NAND_U_BOOT_RELOC);
231 }
232
board_init_r(gd_t * gd,ulong dest_addr)233 void board_init_r(gd_t *gd, ulong dest_addr)
234 {
235 nand_boot();
236 }
237
putc(char c)238 void putc(char c)
239 {
240 if (gd->flags & GD_FLG_SILENT)
241 return;
242
243 if (c == '\n')
244 ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), '\r');
245
246 ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), c);
247 }
248
249 #endif /* CONFIG_NAND_SPL */
250