1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2015-2016 Intel Corp. 4 * Copyright 2019 Google LLC 5 * 6 * Modified from coreboot gpio_defs.h 7 */ 8 9 #ifndef _ASM_INTEL_PINCTRL_DEFS_H_ 10 #define _ASM_INTEL_PINCTRL_DEFS_H_ 11 12 /* This file is included by device trees, so avoid BIT() macros */ 13 14 #define GPIO_DW_SIZE(x) (sizeof(u32) * (x)) 15 #define PAD_CFG_OFFSET(x, dw_num) ((x) + GPIO_DW_SIZE(dw_num)) 16 #define PAD_CFG0_OFFSET(x) PAD_CFG_OFFSET(x, 0) 17 #define PAD_CFG1_OFFSET(x) PAD_CFG_OFFSET(x, 1) 18 19 #define PAD_CFG0_TX_STATE_BIT 0 20 #define PAD_CFG0_TX_STATE (1 << PAD_CFG0_TX_STATE_BIT) 21 #define PAD_CFG0_RX_STATE_BIT 1 22 #define PAD_CFG0_RX_STATE (1 << PAD_CFG0_RX_STATE_BIT) 23 #define PAD_CFG0_TX_DISABLE (1 << 8) 24 #define PAD_CFG0_RX_DISABLE (1 << 9) 25 26 #define PAD_CFG0_MODE_SHIFT 10 27 #define PAD_CFG0_MODE_MASK (7 << PAD_CFG0_MODE_SHIFT) 28 #define PAD_CFG0_MODE_GPIO (0 << PAD_CFG0_MODE_SHIFT) 29 #define PAD_CFG0_MODE_NF1 (1 << PAD_CFG0_MODE_SHIFT) 30 #define PAD_CFG0_MODE_NF2 (2 << PAD_CFG0_MODE_SHIFT) 31 #define PAD_CFG0_MODE_NF3 (3 << PAD_CFG0_MODE_SHIFT) 32 #define PAD_CFG0_MODE_NF4 (4 << PAD_CFG0_MODE_SHIFT) 33 #define PAD_CFG0_MODE_NF5 (5 << PAD_CFG0_MODE_SHIFT) 34 #define PAD_CFG0_MODE_NF6 (6 << PAD_CFG0_MODE_SHIFT) 35 36 #define PAD_CFG0_ROUTE_MASK (0xf << 17) 37 #define PAD_CFG0_ROUTE_NMI (1 << 17) 38 #define PAD_CFG0_ROUTE_SMI (1 << 18) 39 #define PAD_CFG0_ROUTE_SCI (1 << 19) 40 #define PAD_CFG0_ROUTE_IOAPIC (1 << 20) 41 #define PAD_CFG0_RXTENCFG_MASK (3 << 21) 42 #define PAD_CFG0_RXINV_MASK (1 << 23) 43 #define PAD_CFG0_RX_POL_INVERT (1 << 23) 44 #define PAD_CFG0_RX_POL_NONE (0 << 23) 45 #define PAD_CFG0_PREGFRXSEL (1 << 24) 46 #define PAD_CFG0_TRIG_MASK (3 << 25) 47 #define PAD_CFG0_TRIG_LEVEL (0 << 25) 48 #define PAD_CFG0_TRIG_EDGE_SINGLE (1 << 25) /* controlled by RX_INVERT*/ 49 #define PAD_CFG0_TRIG_OFF (2 << 25) 50 #define PAD_CFG0_TRIG_EDGE_BOTH (3 << 25) 51 #define PAD_CFG0_RXRAW1_MASK (1 << 28) 52 #define PAD_CFG0_RXPADSTSEL_MASK (1 << 29) 53 #define PAD_CFG0_RESET_MASK (3 << 30) 54 #define PAD_CFG0_LOGICAL_RESET_PWROK (0U << 30) 55 #define PAD_CFG0_LOGICAL_RESET_DEEP (1U << 30) 56 #define PAD_CFG0_LOGICAL_RESET_PLTRST (2U << 30) 57 #define PAD_CFG0_LOGICAL_RESET_RSMRST (3U << 30) 58 59 /* 60 * Use the fourth bit in IntSel field to indicate gpio ownership. This field is 61 * RO and hence not used during gpio configuration. 62 */ 63 #define PAD_CFG1_GPIO_DRIVER (0x1 << 4) 64 #define PAD_CFG1_IRQ_MASK (0xff << 0) 65 #define PAD_CFG1_IOSTERM_MASK (0x3 << 8) 66 #define PAD_CFG1_IOSTERM_SAME (0x0 << 8) 67 #define PAD_CFG1_IOSTERM_DISPUPD (0x1 << 8) 68 #define PAD_CFG1_IOSTERM_ENPD (0x2 << 8) 69 #define PAD_CFG1_IOSTERM_ENPU (0x3 << 8) 70 #define PAD_CFG1_PULL_MASK (0xf << 10) 71 #define PAD_CFG1_PULL_NONE (0x0 << 10) 72 #define PAD_CFG1_PULL_DN_5K (0x2 << 10) 73 #define PAD_CFG1_PULL_DN_20K (0x4 << 10) 74 #define PAD_CFG1_PULL_UP_1K (0x9 << 10) 75 #define PAD_CFG1_PULL_UP_5K (0xa << 10) 76 #define PAD_CFG1_PULL_UP_2K (0xb << 10) 77 #define PAD_CFG1_PULL_UP_20K (0xc << 10) 78 #define PAD_CFG1_PULL_UP_667 (0xd << 10) 79 #define PAD_CFG1_PULL_NATIVE (0xf << 10) 80 81 /* Tx enabled driving last value driven, Rx enabled */ 82 #define PAD_CFG1_IOSSTATE_TX_LAST_RXE (0x0 << 14) 83 /* 84 * Tx enabled driving 0, Rx disabled and Rx driving 0 back to its controller 85 * internally 86 */ 87 #define PAD_CFG1_IOSSTATE_TX0_RX_DCR_X0 (0x1 << 14) 88 /* 89 * Tx enabled driving 0, Rx disabled and Rx driving 1 back to its controller 90 * internally 91 */ 92 #define PAD_CFG1_IOSSTATE_TX0_RX_DCR_X1 (0x2 << 14) 93 /* 94 * Tx enabled driving 1, Rx disabled and Rx driving 0 back to its controller 95 * internally 96 */ 97 #define PAD_CFG1_IOSSTATE_TX1_RX_DCR_X0 (0x3 << 14) 98 /* 99 * Tx enabled driving 1, Rx disabled and Rx driving 1 back to its controller 100 * internally 101 */ 102 #define PAD_CFG1_IOSSTATE_TX1_RX_DCR_X1 (0x4 << 14) 103 /* Tx enabled driving 0, Rx enabled */ 104 #define PAD_CFG1_IOSSTATE_TX0_RXE (0x5 << 14) 105 /* Tx enabled driving 1, Rx enabled */ 106 #define PAD_CFG1_IOSSTATE_TX1_RXE (0x6 << 14) 107 /* Hi-Z, Rx driving 0 back to its controller internally */ 108 #define PAD_CFG1_IOSSTATE_HIZCRX0 (0x7 << 14) 109 /* Hi-Z, Rx driving 1 back to its controller internally */ 110 #define PAD_CFG1_IOSSTATE_HIZCRX1 (0x8 << 14) 111 /* Tx disabled, Rx enabled */ 112 #define PAD_CFG1_IOSSTATE_TXD_RXE (0x9 << 14) 113 #define PAD_CFG1_IOSSTATE_IGNORE (0xf << 14) /* Ignore Iostandby */ 114 /* mask to extract Iostandby bits */ 115 #define PAD_CFG1_IOSSTATE_MASK (0xf << 14) 116 #define PAD_CFG1_IOSSTATE_SHIFT 14 /* set Iostandby bits [17:14] */ 117 118 #define PAD_CFG2_DEBEN 1 119 /* Debounce Duration = (2 ^ PAD_CFG2_DEBOUNCE_x_RTC) * RTC clock duration */ 120 #define PAD_CFG2_DEBOUNCE_8_RTC (0x3 << 1) 121 #define PAD_CFG2_DEBOUNCE_16_RTC (0x4 << 1) 122 #define PAD_CFG2_DEBOUNCE_32_RTC (0x5 << 1) 123 #define PAD_CFG2_DEBOUNCE_64_RTC (0x6 << 1) 124 #define PAD_CFG2_DEBOUNCE_128_RTC (0x7 << 1) 125 #define PAD_CFG2_DEBOUNCE_256_RTC (0x8 << 1) 126 #define PAD_CFG2_DEBOUNCE_512_RTC (0x9 << 1) 127 #define PAD_CFG2_DEBOUNCE_1K_RTC (0xa << 1) 128 #define PAD_CFG2_DEBOUNCE_2K_RTC (0xb << 1) 129 #define PAD_CFG2_DEBOUNCE_4K_RTC (0xc << 1) 130 #define PAD_CFG2_DEBOUNCE_8K_RTC (0xd << 1) 131 #define PAD_CFG2_DEBOUNCE_16K_RTC (0xe << 1) 132 #define PAD_CFG2_DEBOUNCE_32K_RTC (0xf << 1) 133 #define PAD_CFG2_DEBOUNCE_MASK 0x1f 134 135 /* voltage tolerance 0=3.3V default 1=1.8V tolerant */ 136 #if IS_ENABLED(INTEL_PINCTRL_IOSTANDBY) 137 #define PAD_CFG1_TOL_MASK (0x1 << 25) 138 #define PAD_CFG1_TOL_1V8 (0x1 << 25) 139 #endif 140 141 #define PAD_FUNC(value) PAD_CFG0_MODE_##value 142 #define PAD_RESET(value) PAD_CFG0_LOGICAL_RESET_##value 143 #define PAD_PULL(value) PAD_CFG1_PULL_##value 144 145 #define PAD_IOSSTATE(value) PAD_CFG1_IOSSTATE_##value 146 #define PAD_IOSTERM(value) PAD_CFG1_IOSTERM_##value 147 148 #define PAD_IRQ_CFG(route, trig, inv) \ 149 (PAD_CFG0_ROUTE_##route | \ 150 PAD_CFG0_TRIG_##trig | \ 151 PAD_CFG0_RX_POL_##inv) 152 153 #if IS_ENABLED(INTEL_PINCTRL_DUAL_ROUTE_SUPPORT) 154 #define PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv) \ 155 (PAD_CFG0_ROUTE_##route1 | \ 156 PAD_CFG0_ROUTE_##route2 | \ 157 PAD_CFG0_TRIG_##trig | \ 158 PAD_CFG0_RX_POL_##inv) 159 #endif /* CONFIG_INTEL_PINCTRL_DUAL_ROUTE_SUPPORT */ 160 161 #define _PAD_CFG_STRUCT(__pad, __config0, __config1) \ 162 __pad(__config0) (__config1) 163 164 /* Native function configuration */ 165 #define PAD_CFG_NF(pad, pull, rst, func) \ 166 _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ 167 PAD_IOSSTATE(TX_LAST_RXE)) 168 169 #if IS_ENABLED(CONFIG_INTEL_GPIO_PADCFG_PADTOL) 170 /* 171 * Native 1.8V tolerant pad, only applies to some pads like I2C/I2S. Not 172 * applicable to all SOCs. Refer EDS. 173 */ 174 #define PAD_CFG_NF_1V8(pad, pull, rst, func) \ 175 _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) |\ 176 PAD_IOSSTATE(TX_LAST_RXE) | PAD_CFG1_TOL_1V8) 177 #endif 178 179 /* Native function configuration for standby state */ 180 #define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \ 181 _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ 182 PAD_IOSSTATE(iosstate)) 183 184 /* 185 * Native function configuration for standby state, also configuring iostandby 186 * as masked 187 */ 188 #define PAD_CFG_NF_IOSTANDBY_IGNORE(pad, pull, rst, func) \ 189 _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ 190 PAD_IOSSTATE(IGNORE)) 191 192 /* 193 * Native function configuration for standby state, also configuring iosstate 194 * and iosterm 195 */ 196 #define PAD_CFG_NF_IOSSTATE_IOSTERM(pad, pull, rst, func, iosstate, iosterm) \ 197 _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ 198 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) 199 200 /* General purpose output, no pullup/down */ 201 #define PAD_CFG_GPO(pad, val, rst) \ 202 _PAD_CFG_STRUCT(pad, \ 203 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ 204 PAD_PULL(NONE) | PAD_IOSSTATE(TX_LAST_RXE)) 205 206 /* General purpose output, with termination specified */ 207 #define PAD_CFG_TERM_GPO(pad, val, pull, rst) \ 208 _PAD_CFG_STRUCT(pad, \ 209 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ 210 PAD_PULL(pull) | PAD_IOSSTATE(TX_LAST_RXE)) 211 212 /* General purpose output, no pullup/down */ 213 #define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \ 214 _PAD_CFG_STRUCT(pad, \ 215 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ 216 PAD_PULL(pull) | PAD_IOSSTATE(TX_LAST_RXE) | \ 217 PAD_CFG1_GPIO_DRIVER) 218 219 /* General purpose output */ 220 #define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) \ 221 _PAD_CFG_STRUCT(pad, \ 222 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \ 223 PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm)) 224 225 /* General purpose input */ 226 #define PAD_CFG_GPI(pad, pull, rst) \ 227 _PAD_CFG_STRUCT(pad, \ 228 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ 229 PAD_PULL(pull) | PAD_IOSSTATE(TXD_RXE)) 230 231 /* General purpose input. The following macro sets the 232 * Host Software Pad Ownership to GPIO Driver mode. 233 */ 234 #define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ 235 _PAD_CFG_STRUCT(pad, \ 236 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ 237 PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TXD_RXE)) 238 239 #define PAD_CFG_GPIO_DRIVER_HI_Z(pad, pull, rst, iosstate, iosterm) \ 240 _PAD_CFG_STRUCT(pad, \ 241 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ 242 PAD_CFG0_RX_DISABLE, \ 243 PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | \ 244 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) 245 246 #define PAD_CFG_GPIO_HI_Z(pad, pull, rst, iosstate, iosterm) \ 247 _PAD_CFG_STRUCT(pad, \ 248 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ 249 PAD_CFG0_RX_DISABLE, PAD_PULL(pull) | \ 250 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) 251 252 /* GPIO Interrupt */ 253 #define PAD_CFG_GPI_INT(pad, pull, rst, trig) \ 254 _PAD_CFG_STRUCT(pad, \ 255 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ 256 PAD_CFG0_TRIG_##trig | PAD_CFG0_RX_POL_NONE, \ 257 PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TXD_RXE)) 258 259 /* 260 * No Connect configuration for unused pad. 261 * Both TX and RX are disabled. RX disabling is done to avoid unnecessary 262 * setting of GPI_STS. 263 */ 264 #define PAD_NC(pad, pull) \ 265 _PAD_CFG_STRUCT(pad, \ 266 PAD_FUNC(GPIO) | PAD_RESET(DEEP) | \ 267 PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE, \ 268 PAD_PULL(pull) | PAD_IOSSTATE(TXD_RXE)) 269 270 /* General purpose input, routed to APIC */ 271 #define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \ 272 _PAD_CFG_STRUCT(pad, \ 273 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ 274 PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ 275 PAD_IOSSTATE(TXD_RXE)) 276 277 /* General purpose input, routed to APIC - with IOStandby Config*/ 278 #define PAD_CFG_GPI_APIC_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ 279 _PAD_CFG_STRUCT(pad, \ 280 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ 281 PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ 282 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) 283 284 /* 285 * The following APIC macros assume the APIC will handle the filtering 286 * on its own end. One just needs to pass an active high message into the 287 * ITSS. 288 */ 289 #define PAD_CFG_GPI_APIC_LOW(pad, pull, rst) \ 290 PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, INVERT) 291 292 #define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \ 293 PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, NONE) 294 295 #define PAD_CFG_GPI_APIC_EDGE_LOW(pad, pull, rst) \ 296 PAD_CFG_GPI_APIC(pad, pull, rst, EDGE_SINGLE, INVERT) 297 298 /* General purpose input, routed to SMI */ 299 #define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \ 300 _PAD_CFG_STRUCT(pad, \ 301 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ 302 PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ 303 PAD_IOSSTATE(TXD_RXE)) 304 305 /* General purpose input, routed to SMI */ 306 #define PAD_CFG_GPI_SMI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ 307 _PAD_CFG_STRUCT(pad, \ 308 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ 309 PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ 310 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) 311 312 #define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \ 313 PAD_CFG_GPI_SMI(pad, pull, rst, trig, INVERT) 314 315 #define PAD_CFG_GPI_SMI_HIGH(pad, pull, rst, trig) \ 316 PAD_CFG_GPI_SMI(pad, pull, rst, trig, NONE) 317 318 /* General purpose input, routed to SCI */ 319 #define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \ 320 _PAD_CFG_STRUCT(pad, \ 321 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ 322 PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ 323 PAD_IOSSTATE(TXD_RXE)) 324 325 /* General purpose input, routed to SCI */ 326 #define PAD_CFG_GPI_SCI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ 327 _PAD_CFG_STRUCT(pad, \ 328 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ 329 PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ 330 PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) 331 332 #define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig) \ 333 PAD_CFG_GPI_SCI(pad, pull, rst, trig, INVERT) 334 335 #define PAD_CFG_GPI_SCI_HIGH(pad, pull, rst, trig) \ 336 PAD_CFG_GPI_SCI(pad, pull, rst, trig, NONE) 337 338 #define PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, inv, dur) \ 339 _PAD_CFG_STRUCT_3(pad, \ 340 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ 341 PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ 342 PAD_IOSSTATE(TXD_RXE), PAD_CFG2_DEBEN | PAD_CFG2_##dur) 343 344 #define PAD_CFG_GPI_SCI_LOW_DEBEN(pad, pull, rst, trig, dur) \ 345 PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, INVERT, dur) 346 347 #define PAD_CFG_GPI_SCI_HIGH_DEBEN(pad, pull, rst, trig, dur) \ 348 PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, NONE, dur) 349 350 /* General purpose input, routed to NMI */ 351 #define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \ 352 _PAD_CFG_STRUCT(pad, \ 353 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ 354 PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \ 355 PAD_IOSSTATE(TXD_RXE)) 356 357 #if IS_ENABLED(INTEL_PINCTRL_DUAL_ROUTE_SUPPORT) 358 /* GPI, GPIO Driver, SCI interrupt */ 359 #define PAD_CFG_GPI_GPIO_DRIVER_SCI(pad, pull, rst, trig, inv) \ 360 _PAD_CFG_STRUCT(pad, \ 361 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ 362 PAD_IRQ_CFG(SCI, trig, inv), \ 363 PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TXD_RXE)) 364 365 #define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \ 366 _PAD_CFG_STRUCT(pad, \ 367 PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ 368 PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv), \ 369 PAD_PULL(pull) | PAD_IOSSTATE(TXD_RXE)) 370 371 #define PAD_CFG_GPI_IRQ_WAKE(pad, pull, rst, trig, inv) \ 372 PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, IOAPIC, SCI) 373 374 #endif /* CONFIG_INTEL_PINCTRL_DUAL_ROUTE_SUPPORT */ 375 376 #endif /* _ASM_INTEL_PINCTRL_DEFS_H_ */ 377