1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2007 Atmel Corporation
4 */
5 #include <common.h>
6 #include <clk.h>
7 #include <dm.h>
8 #include <fdtdec.h>
9 #include <spi.h>
10 #include <malloc.h>
11 #include <wait_bit.h>
12 #include <asm/io.h>
13 #include <asm/arch/clk.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/at91_spi.h>
16 #if CONFIG_IS_ENABLED(DM_GPIO)
17 #include <asm/gpio.h>
18 #endif
19 #include <linux/bitops.h>
20
21 /*
22 * Register definitions for the Atmel AT32/AT91 SPI Controller
23 */
24 /* Register offsets */
25 #define ATMEL_SPI_CR 0x0000
26 #define ATMEL_SPI_MR 0x0004
27 #define ATMEL_SPI_RDR 0x0008
28 #define ATMEL_SPI_TDR 0x000c
29 #define ATMEL_SPI_SR 0x0010
30 #define ATMEL_SPI_IER 0x0014
31 #define ATMEL_SPI_IDR 0x0018
32 #define ATMEL_SPI_IMR 0x001c
33 #define ATMEL_SPI_CSR(x) (0x0030 + 4 * (x))
34 #define ATMEL_SPI_VERSION 0x00fc
35
36 /* Bits in CR */
37 #define ATMEL_SPI_CR_SPIEN BIT(0)
38 #define ATMEL_SPI_CR_SPIDIS BIT(1)
39 #define ATMEL_SPI_CR_SWRST BIT(7)
40 #define ATMEL_SPI_CR_LASTXFER BIT(24)
41
42 /* Bits in MR */
43 #define ATMEL_SPI_MR_MSTR BIT(0)
44 #define ATMEL_SPI_MR_PS BIT(1)
45 #define ATMEL_SPI_MR_PCSDEC BIT(2)
46 #define ATMEL_SPI_MR_FDIV BIT(3)
47 #define ATMEL_SPI_MR_MODFDIS BIT(4)
48 #define ATMEL_SPI_MR_WDRBT BIT(5)
49 #define ATMEL_SPI_MR_LLB BIT(7)
50 #define ATMEL_SPI_MR_PCS(x) (((x) & 15) << 16)
51 #define ATMEL_SPI_MR_DLYBCS(x) ((x) << 24)
52
53 /* Bits in RDR */
54 #define ATMEL_SPI_RDR_RD(x) (x)
55 #define ATMEL_SPI_RDR_PCS(x) ((x) << 16)
56
57 /* Bits in TDR */
58 #define ATMEL_SPI_TDR_TD(x) (x)
59 #define ATMEL_SPI_TDR_PCS(x) ((x) << 16)
60 #define ATMEL_SPI_TDR_LASTXFER BIT(24)
61
62 /* Bits in SR/IER/IDR/IMR */
63 #define ATMEL_SPI_SR_RDRF BIT(0)
64 #define ATMEL_SPI_SR_TDRE BIT(1)
65 #define ATMEL_SPI_SR_MODF BIT(2)
66 #define ATMEL_SPI_SR_OVRES BIT(3)
67 #define ATMEL_SPI_SR_ENDRX BIT(4)
68 #define ATMEL_SPI_SR_ENDTX BIT(5)
69 #define ATMEL_SPI_SR_RXBUFF BIT(6)
70 #define ATMEL_SPI_SR_TXBUFE BIT(7)
71 #define ATMEL_SPI_SR_NSSR BIT(8)
72 #define ATMEL_SPI_SR_TXEMPTY BIT(9)
73 #define ATMEL_SPI_SR_SPIENS BIT(16)
74
75 /* Bits in CSRx */
76 #define ATMEL_SPI_CSRx_CPOL BIT(0)
77 #define ATMEL_SPI_CSRx_NCPHA BIT(1)
78 #define ATMEL_SPI_CSRx_CSAAT BIT(3)
79 #define ATMEL_SPI_CSRx_BITS(x) ((x) << 4)
80 #define ATMEL_SPI_CSRx_SCBR(x) ((x) << 8)
81 #define ATMEL_SPI_CSRx_SCBR_MAX GENMASK(7, 0)
82 #define ATMEL_SPI_CSRx_DLYBS(x) ((x) << 16)
83 #define ATMEL_SPI_CSRx_DLYBCT(x) ((x) << 24)
84
85 /* Bits in VERSION */
86 #define ATMEL_SPI_VERSION_REV(x) ((x) & 0xfff)
87 #define ATMEL_SPI_VERSION_MFN(x) ((x) << 16)
88
89 /* Constants for CSRx:BITS */
90 #define ATMEL_SPI_BITS_8 0
91 #define ATMEL_SPI_BITS_9 1
92 #define ATMEL_SPI_BITS_10 2
93 #define ATMEL_SPI_BITS_11 3
94 #define ATMEL_SPI_BITS_12 4
95 #define ATMEL_SPI_BITS_13 5
96 #define ATMEL_SPI_BITS_14 6
97 #define ATMEL_SPI_BITS_15 7
98 #define ATMEL_SPI_BITS_16 8
99
100 #define MAX_CS_COUNT 4
101
102 /* Register access macros */
103 #define spi_readl(as, reg) \
104 readl(as->regs + ATMEL_SPI_##reg)
105 #define spi_writel(as, reg, value) \
106 writel(value, as->regs + ATMEL_SPI_##reg)
107
108 struct atmel_spi_plat {
109 struct at91_spi *regs;
110 };
111
112 struct atmel_spi_priv {
113 unsigned int freq; /* Default frequency */
114 unsigned int mode;
115 ulong bus_clk_rate;
116 #if CONFIG_IS_ENABLED(DM_GPIO)
117 struct gpio_desc cs_gpios[MAX_CS_COUNT];
118 #endif
119 };
120
atmel_spi_claim_bus(struct udevice * dev)121 static int atmel_spi_claim_bus(struct udevice *dev)
122 {
123 struct udevice *bus = dev_get_parent(dev);
124 struct atmel_spi_plat *bus_plat = dev_get_plat(bus);
125 struct atmel_spi_priv *priv = dev_get_priv(bus);
126 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
127 struct at91_spi *reg_base = bus_plat->regs;
128 u32 cs = slave_plat->cs;
129 u32 freq = priv->freq;
130 u32 scbr, csrx, mode;
131
132 scbr = (priv->bus_clk_rate + freq - 1) / freq;
133 if (scbr > ATMEL_SPI_CSRx_SCBR_MAX)
134 return -EINVAL;
135
136 if (scbr < 1)
137 scbr = 1;
138
139 csrx = ATMEL_SPI_CSRx_SCBR(scbr);
140 csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8);
141
142 if (!(priv->mode & SPI_CPHA))
143 csrx |= ATMEL_SPI_CSRx_NCPHA;
144 if (priv->mode & SPI_CPOL)
145 csrx |= ATMEL_SPI_CSRx_CPOL;
146
147 writel(csrx, ®_base->csr[cs]);
148
149 mode = ATMEL_SPI_MR_MSTR |
150 ATMEL_SPI_MR_MODFDIS |
151 ATMEL_SPI_MR_WDRBT |
152 ATMEL_SPI_MR_PCS(~(1 << cs));
153
154 writel(mode, ®_base->mr);
155
156 writel(ATMEL_SPI_CR_SPIEN, ®_base->cr);
157
158 return 0;
159 }
160
atmel_spi_release_bus(struct udevice * dev)161 static int atmel_spi_release_bus(struct udevice *dev)
162 {
163 struct udevice *bus = dev_get_parent(dev);
164 struct atmel_spi_plat *bus_plat = dev_get_plat(bus);
165
166 writel(ATMEL_SPI_CR_SPIDIS, &bus_plat->regs->cr);
167
168 return 0;
169 }
170
atmel_spi_cs_activate(struct udevice * dev)171 static void atmel_spi_cs_activate(struct udevice *dev)
172 {
173 #if CONFIG_IS_ENABLED(DM_GPIO)
174 struct udevice *bus = dev_get_parent(dev);
175 struct atmel_spi_priv *priv = dev_get_priv(bus);
176 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
177 u32 cs = slave_plat->cs;
178
179 if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
180 return;
181
182 dm_gpio_set_value(&priv->cs_gpios[cs], 0);
183 #endif
184 }
185
atmel_spi_cs_deactivate(struct udevice * dev)186 static void atmel_spi_cs_deactivate(struct udevice *dev)
187 {
188 #if CONFIG_IS_ENABLED(DM_GPIO)
189 struct udevice *bus = dev_get_parent(dev);
190 struct atmel_spi_priv *priv = dev_get_priv(bus);
191 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
192 u32 cs = slave_plat->cs;
193
194 if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
195 return;
196
197 dm_gpio_set_value(&priv->cs_gpios[cs], 1);
198 #endif
199 }
200
atmel_spi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)201 static int atmel_spi_xfer(struct udevice *dev, unsigned int bitlen,
202 const void *dout, void *din, unsigned long flags)
203 {
204 struct udevice *bus = dev_get_parent(dev);
205 struct atmel_spi_plat *bus_plat = dev_get_plat(bus);
206 struct at91_spi *reg_base = bus_plat->regs;
207
208 u32 len_tx, len_rx, len;
209 u32 status;
210 const u8 *txp = dout;
211 u8 *rxp = din;
212 u8 value;
213
214 if (bitlen == 0)
215 goto out;
216
217 /*
218 * The controller can do non-multiple-of-8 bit
219 * transfers, but this driver currently doesn't support it.
220 *
221 * It's also not clear how such transfers are supposed to be
222 * represented as a stream of bytes...this is a limitation of
223 * the current SPI interface.
224 */
225 if (bitlen % 8) {
226 /* Errors always terminate an ongoing transfer */
227 flags |= SPI_XFER_END;
228 goto out;
229 }
230
231 len = bitlen / 8;
232
233 /*
234 * The controller can do automatic CS control, but it is
235 * somewhat quirky, and it doesn't really buy us much anyway
236 * in the context of U-Boot.
237 */
238 if (flags & SPI_XFER_BEGIN) {
239 atmel_spi_cs_activate(dev);
240
241 /*
242 * sometimes the RDR is not empty when we get here,
243 * in theory that should not happen, but it DOES happen.
244 * Read it here to be on the safe side.
245 * That also clears the OVRES flag. Required if the
246 * following loop exits due to OVRES!
247 */
248 readl(®_base->rdr);
249 }
250
251 for (len_tx = 0, len_rx = 0; len_rx < len; ) {
252 status = readl(®_base->sr);
253
254 if (status & ATMEL_SPI_SR_OVRES)
255 return -1;
256
257 if ((len_tx < len) && (status & ATMEL_SPI_SR_TDRE)) {
258 if (txp)
259 value = *txp++;
260 else
261 value = 0;
262 writel(value, ®_base->tdr);
263 len_tx++;
264 }
265
266 if (status & ATMEL_SPI_SR_RDRF) {
267 value = readl(®_base->rdr);
268 if (rxp)
269 *rxp++ = value;
270 len_rx++;
271 }
272 }
273
274 out:
275 if (flags & SPI_XFER_END) {
276 /*
277 * Wait until the transfer is completely done before
278 * we deactivate CS.
279 */
280 wait_for_bit_le32(®_base->sr,
281 ATMEL_SPI_SR_TXEMPTY, true, 1000, false);
282
283 atmel_spi_cs_deactivate(dev);
284 }
285
286 return 0;
287 }
288
atmel_spi_set_speed(struct udevice * bus,uint speed)289 static int atmel_spi_set_speed(struct udevice *bus, uint speed)
290 {
291 struct atmel_spi_priv *priv = dev_get_priv(bus);
292
293 priv->freq = speed;
294
295 return 0;
296 }
297
atmel_spi_set_mode(struct udevice * bus,uint mode)298 static int atmel_spi_set_mode(struct udevice *bus, uint mode)
299 {
300 struct atmel_spi_priv *priv = dev_get_priv(bus);
301
302 priv->mode = mode;
303
304 return 0;
305 }
306
307 static const struct dm_spi_ops atmel_spi_ops = {
308 .claim_bus = atmel_spi_claim_bus,
309 .release_bus = atmel_spi_release_bus,
310 .xfer = atmel_spi_xfer,
311 .set_speed = atmel_spi_set_speed,
312 .set_mode = atmel_spi_set_mode,
313 /*
314 * cs_info is not needed, since we require all chip selects to be
315 * in the device tree explicitly
316 */
317 };
318
atmel_spi_enable_clk(struct udevice * bus)319 static int atmel_spi_enable_clk(struct udevice *bus)
320 {
321 struct atmel_spi_priv *priv = dev_get_priv(bus);
322 struct clk clk;
323 ulong clk_rate;
324 int ret;
325
326 ret = clk_get_by_index(bus, 0, &clk);
327 if (ret)
328 return -EINVAL;
329
330 ret = clk_enable(&clk);
331 if (ret)
332 return ret;
333
334 clk_rate = clk_get_rate(&clk);
335 if (!clk_rate)
336 return -EINVAL;
337
338 priv->bus_clk_rate = clk_rate;
339
340 clk_free(&clk);
341
342 return 0;
343 }
344
atmel_spi_probe(struct udevice * bus)345 static int atmel_spi_probe(struct udevice *bus)
346 {
347 struct atmel_spi_plat *bus_plat = dev_get_plat(bus);
348 int ret;
349
350 ret = atmel_spi_enable_clk(bus);
351 if (ret)
352 return ret;
353
354 bus_plat->regs = dev_read_addr_ptr(bus);
355
356 #if CONFIG_IS_ENABLED(DM_GPIO)
357 struct atmel_spi_priv *priv = dev_get_priv(bus);
358 int i;
359
360 ret = gpio_request_list_by_name(bus, "cs-gpios", priv->cs_gpios,
361 ARRAY_SIZE(priv->cs_gpios), 0);
362 if (ret < 0) {
363 pr_err("Can't get %s gpios! Error: %d", bus->name, ret);
364 return ret;
365 }
366
367 for(i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) {
368 if (!dm_gpio_is_valid(&priv->cs_gpios[i]))
369 continue;
370
371 dm_gpio_set_dir_flags(&priv->cs_gpios[i],
372 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
373 }
374 #endif
375
376 writel(ATMEL_SPI_CR_SWRST, &bus_plat->regs->cr);
377
378 return 0;
379 }
380
381 static const struct udevice_id atmel_spi_ids[] = {
382 { .compatible = "atmel,at91rm9200-spi" },
383 { }
384 };
385
386 U_BOOT_DRIVER(atmel_spi) = {
387 .name = "atmel_spi",
388 .id = UCLASS_SPI,
389 .of_match = atmel_spi_ids,
390 .ops = &atmel_spi_ops,
391 .plat_auto = sizeof(struct atmel_spi_plat),
392 .priv_auto = sizeof(struct atmel_spi_priv),
393 .probe = atmel_spi_probe,
394 };
395