1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) Marvell International Ltd. and its affiliates 4 */ 5 6 #ifndef _DDR_TOPOLOGY_DEF_H 7 #define _DDR_TOPOLOGY_DEF_H 8 9 #include "ddr3_training_ip_def.h" 10 #include "mv_ddr_topology.h" 11 #include "mv_ddr_spd.h" 12 #include "ddr3_logging_def.h" 13 14 #define MV_DDR_MAX_BUS_NUM 9 15 #define MV_DDR_MAX_IFACE_NUM 1 16 17 enum mv_ddr_twin_die { 18 NOT_COMBINED, 19 COMBINED, 20 }; 21 22 struct bus_params { 23 /* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */ 24 u8 cs_bitmask; 25 26 /* 27 * mirror enable/disable 28 * (bits 0-CS0 mirroring, bit 1- CS1 mirroring ...) 29 */ 30 int mirror_enable_bitmask; 31 32 /* DQS Swap (polarity) - true if enable */ 33 int is_dqs_swap; 34 35 /* CK swap (polarity) - true if enable */ 36 int is_ck_swap; 37 }; 38 39 struct if_params { 40 /* bus configuration */ 41 struct bus_params as_bus_params[MV_DDR_MAX_BUS_NUM]; 42 43 /* Speed Bin Table */ 44 enum mv_ddr_speed_bin speed_bin_index; 45 46 /* sdram device width */ 47 enum mv_ddr_dev_width bus_width; 48 49 /* total sdram capacity per die, megabits */ 50 enum mv_ddr_die_capacity memory_size; 51 52 /* The DDR frequency for each interfaces */ 53 enum mv_ddr_freq memory_freq; 54 55 /* 56 * delay CAS Write Latency 57 * - 0 for using default value (jedec suggested) 58 */ 59 u8 cas_wl; 60 61 /* 62 * delay CAS Latency 63 * - 0 for using default value (jedec suggested) 64 */ 65 u8 cas_l; 66 67 /* operation temperature */ 68 enum mv_ddr_temperature interface_temp; 69 70 /* 2T vs 1T mode (by default computed from number of CSs) */ 71 enum mv_ddr_timing timing; 72 }; 73 74 /* memory electrical configuration */ 75 struct mv_ddr_mem_edata { 76 enum mv_ddr_rtt_nom_park_evalue rtt_nom; 77 enum mv_ddr_rtt_nom_park_evalue rtt_park[MAX_CS_NUM]; 78 enum mv_ddr_rtt_wr_evalue rtt_wr[MAX_CS_NUM]; 79 enum mv_ddr_dic_evalue dic; 80 }; 81 82 /* phy electrical configuration */ 83 struct mv_ddr_phy_edata { 84 enum mv_ddr_ohm_evalue drv_data_p; 85 enum mv_ddr_ohm_evalue drv_data_n; 86 enum mv_ddr_ohm_evalue drv_ctrl_p; 87 enum mv_ddr_ohm_evalue drv_ctrl_n; 88 enum mv_ddr_ohm_evalue odt_p[MAX_CS_NUM]; 89 enum mv_ddr_ohm_evalue odt_n[MAX_CS_NUM]; 90 }; 91 92 /* mac electrical configuration */ 93 struct mv_ddr_mac_edata { 94 enum mv_ddr_odt_cfg_evalue odt_cfg_pat; 95 enum mv_ddr_odt_cfg_evalue odt_cfg_wr; 96 enum mv_ddr_odt_cfg_evalue odt_cfg_rd; 97 }; 98 99 struct mv_ddr_edata { 100 struct mv_ddr_mem_edata mem_edata; 101 struct mv_ddr_phy_edata phy_edata; 102 struct mv_ddr_mac_edata mac_edata; 103 }; 104 105 struct mv_ddr_topology_map { 106 /* debug level configuration */ 107 enum mv_ddr_debug_level debug_level; 108 109 /* Number of interfaces (default is 12) */ 110 u8 if_act_mask; 111 112 /* Controller configuration per interface */ 113 struct if_params interface_params[MV_DDR_MAX_IFACE_NUM]; 114 115 /* Bit mask for active buses */ 116 u16 bus_act_mask; 117 118 /* source of ddr configuration data */ 119 enum mv_ddr_cfg_src cfg_src; 120 121 /* ddr twin-die */ 122 enum mv_ddr_twin_die twin_die_combined; 123 124 /* raw spd data */ 125 union mv_ddr_spd_data spd_data; 126 127 /* timing parameters */ 128 unsigned int timing_data[MV_DDR_TDATA_LAST]; 129 130 /* electrical configuration */ 131 struct mv_ddr_edata edata; 132 133 /* electrical parameters */ 134 unsigned int electrical_data[MV_DDR_EDATA_LAST]; 135 136 /* ODT configuration */ 137 u32 odt_config; 138 139 /* Clock enable mask */ 140 u32 clk_enable; 141 142 /* Clock delay */ 143 int ck_delay; 144 }; 145 146 enum mv_ddr_iface_mode { 147 MV_DDR_RAR_ENA, 148 MV_DDR_RAR_DIS, 149 }; 150 151 enum mv_ddr_iface_state { 152 MV_DDR_IFACE_NRDY, /* not ready */ 153 MV_DDR_IFACE_INIT, /* init'd */ 154 MV_DDR_IFACE_RDY, /* ready */ 155 MV_DDR_IFACE_DNE /* does not exist */ 156 }; 157 158 enum mv_ddr_validation { 159 MV_DDR_VAL_DIS, 160 MV_DDR_VAL_RX, 161 MV_DDR_VAL_TX, 162 MV_DDR_VAL_RX_TX, 163 MV_DDR_MEMORY_CHECK 164 }; 165 166 enum mv_ddr_sscg { 167 SSCG_EN, 168 SSCG_DIS, 169 }; 170 171 struct mv_ddr_iface { 172 /* base addr of ap ddr interface belongs to */ 173 unsigned int ap_base; 174 175 /* ddr interface id */ 176 unsigned int id; 177 178 /* ddr interface state */ 179 enum mv_ddr_iface_state state; 180 181 /* ddr interface mode (rar enabled/disabled) */ 182 enum mv_ddr_iface_mode iface_mode; 183 184 /* ddr interface base address */ 185 unsigned long long iface_base_addr; 186 187 /* ddr interface size - ddr flow will update this parameter */ 188 unsigned long long iface_byte_size; 189 190 /* ddr i2c spd data address */ 191 unsigned int spd_data_addr; 192 193 /* ddr i2c spd page 0 select address */ 194 unsigned int spd_page_sel_addr; 195 196 /* ddr interface validation mode */ 197 enum mv_ddr_validation validation; 198 199 /* ddr interface validation mode */ 200 enum mv_ddr_sscg sscg; 201 202 /* ddr interface topology map */ 203 struct mv_ddr_topology_map tm; 204 205 }; 206 207 struct mv_ddr_iface *mv_ddr_iface_get(void); 208 209 /* DDR3 training global configuration parameters */ 210 struct tune_train_params { 211 u32 ck_delay; 212 u32 phy_reg3_val; 213 u32 g_zpri_data; 214 u32 g_znri_data; 215 u32 g_zpri_ctrl; 216 u32 g_znri_ctrl; 217 u32 g_zpodt_data; 218 u32 g_znodt_data; 219 u32 g_zpodt_ctrl; 220 u32 g_znodt_ctrl; 221 u32 g_dic; 222 u32 g_odt_config; 223 u32 g_rtt_nom; 224 u32 g_rtt_wr; 225 u32 g_rtt_park; 226 }; 227 228 #endif /* _DDR_TOPOLOGY_DEF_H */ 229