1 /*
2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * - Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * - Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * - Neither the name of the Altera Corporation nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include <common.h>
29 #include <log.h>
30 #include <asm/io.h>
31 #include <dma.h>
32 #include <linux/bitops.h>
33 #include <linux/delay.h>
34 #include <linux/errno.h>
35 #include <wait_bit.h>
36 #include <spi.h>
37 #include <spi-mem.h>
38 #include <malloc.h>
39 #include "cadence_qspi.h"
40
41 #define CQSPI_REG_POLL_US 1 /* 1us */
42 #define CQSPI_REG_RETRY 10000
43 #define CQSPI_POLL_IDLE_RETRY 3
44
45 /* Transfer mode */
46 #define CQSPI_INST_TYPE_SINGLE 0
47 #define CQSPI_INST_TYPE_DUAL 1
48 #define CQSPI_INST_TYPE_QUAD 2
49 #define CQSPI_INST_TYPE_OCTAL 3
50
51 #define CQSPI_STIG_DATA_LEN_MAX 8
52
53 #define CQSPI_DUMMY_CLKS_PER_BYTE 8
54 #define CQSPI_DUMMY_BYTES_MAX 4
55
56 /****************************************************************************
57 * Controller's configuration and status register (offset from QSPI_BASE)
58 ****************************************************************************/
59 #define CQSPI_REG_CONFIG 0x00
60 #define CQSPI_REG_CONFIG_ENABLE BIT(0)
61 #define CQSPI_REG_CONFIG_CLK_POL BIT(1)
62 #define CQSPI_REG_CONFIG_CLK_PHA BIT(2)
63 #define CQSPI_REG_CONFIG_DIRECT BIT(7)
64 #define CQSPI_REG_CONFIG_DECODE BIT(9)
65 #define CQSPI_REG_CONFIG_XIP_IMM BIT(18)
66 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
67 #define CQSPI_REG_CONFIG_BAUD_LSB 19
68 #define CQSPI_REG_CONFIG_IDLE_LSB 31
69 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
70 #define CQSPI_REG_CONFIG_BAUD_MASK 0xF
71
72 #define CQSPI_REG_RD_INSTR 0x04
73 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
74 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
75 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
76 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
77 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
78 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
79 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
80 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
81 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
82 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
83
84 #define CQSPI_REG_WR_INSTR 0x08
85 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
86 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16
87
88 #define CQSPI_REG_DELAY 0x0C
89 #define CQSPI_REG_DELAY_TSLCH_LSB 0
90 #define CQSPI_REG_DELAY_TCHSH_LSB 8
91 #define CQSPI_REG_DELAY_TSD2D_LSB 16
92 #define CQSPI_REG_DELAY_TSHSL_LSB 24
93 #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
94 #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
95 #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
96 #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
97
98 #define CQSPI_REG_RD_DATA_CAPTURE 0x10
99 #define CQSPI_REG_RD_DATA_CAPTURE_BYPASS BIT(0)
100 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB 1
101 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK 0xF
102
103 #define CQSPI_REG_SIZE 0x14
104 #define CQSPI_REG_SIZE_ADDRESS_LSB 0
105 #define CQSPI_REG_SIZE_PAGE_LSB 4
106 #define CQSPI_REG_SIZE_BLOCK_LSB 16
107 #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
108 #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
109 #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
110
111 #define CQSPI_REG_SRAMPARTITION 0x18
112 #define CQSPI_REG_INDIRECTTRIGGER 0x1C
113
114 #define CQSPI_REG_REMAP 0x24
115 #define CQSPI_REG_MODE_BIT 0x28
116
117 #define CQSPI_REG_SDRAMLEVEL 0x2C
118 #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
119 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
120 #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
121 #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
122
123 #define CQSPI_REG_IRQSTATUS 0x40
124 #define CQSPI_REG_IRQMASK 0x44
125
126 #define CQSPI_REG_INDIRECTRD 0x60
127 #define CQSPI_REG_INDIRECTRD_START BIT(0)
128 #define CQSPI_REG_INDIRECTRD_CANCEL BIT(1)
129 #define CQSPI_REG_INDIRECTRD_INPROGRESS BIT(2)
130 #define CQSPI_REG_INDIRECTRD_DONE BIT(5)
131
132 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64
133 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
134 #define CQSPI_REG_INDIRECTRDBYTES 0x6C
135
136 #define CQSPI_REG_CMDCTRL 0x90
137 #define CQSPI_REG_CMDCTRL_EXECUTE BIT(0)
138 #define CQSPI_REG_CMDCTRL_INPROGRESS BIT(1)
139 #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7
140 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
141 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
142 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
143 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
144 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
145 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
146 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
147 #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F
148 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
149 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
150 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
151 #define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF
152
153 #define CQSPI_REG_INDIRECTWR 0x70
154 #define CQSPI_REG_INDIRECTWR_START BIT(0)
155 #define CQSPI_REG_INDIRECTWR_CANCEL BIT(1)
156 #define CQSPI_REG_INDIRECTWR_INPROGRESS BIT(2)
157 #define CQSPI_REG_INDIRECTWR_DONE BIT(5)
158
159 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74
160 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
161 #define CQSPI_REG_INDIRECTWRBYTES 0x7C
162
163 #define CQSPI_REG_CMDADDRESS 0x94
164 #define CQSPI_REG_CMDREADDATALOWER 0xA0
165 #define CQSPI_REG_CMDREADDATAUPPER 0xA4
166 #define CQSPI_REG_CMDWRITEDATALOWER 0xA8
167 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
168
169 #define CQSPI_REG_IS_IDLE(base) \
170 ((readl(base + CQSPI_REG_CONFIG) >> \
171 CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
172
173 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \
174 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
175 CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
176
177 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \
178 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
179 CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
180
cadence_qspi_apb_controller_enable(void * reg_base)181 void cadence_qspi_apb_controller_enable(void *reg_base)
182 {
183 unsigned int reg;
184 reg = readl(reg_base + CQSPI_REG_CONFIG);
185 reg |= CQSPI_REG_CONFIG_ENABLE;
186 writel(reg, reg_base + CQSPI_REG_CONFIG);
187 }
188
cadence_qspi_apb_controller_disable(void * reg_base)189 void cadence_qspi_apb_controller_disable(void *reg_base)
190 {
191 unsigned int reg;
192 reg = readl(reg_base + CQSPI_REG_CONFIG);
193 reg &= ~CQSPI_REG_CONFIG_ENABLE;
194 writel(reg, reg_base + CQSPI_REG_CONFIG);
195 }
196
cadence_qspi_apb_dac_mode_enable(void * reg_base)197 void cadence_qspi_apb_dac_mode_enable(void *reg_base)
198 {
199 unsigned int reg;
200
201 reg = readl(reg_base + CQSPI_REG_CONFIG);
202 reg |= CQSPI_REG_CONFIG_DIRECT;
203 writel(reg, reg_base + CQSPI_REG_CONFIG);
204 }
205
206 /* Return 1 if idle, otherwise return 0 (busy). */
cadence_qspi_wait_idle(void * reg_base)207 static unsigned int cadence_qspi_wait_idle(void *reg_base)
208 {
209 unsigned int start, count = 0;
210 /* timeout in unit of ms */
211 unsigned int timeout = 5000;
212
213 start = get_timer(0);
214 for ( ; get_timer(start) < timeout ; ) {
215 if (CQSPI_REG_IS_IDLE(reg_base))
216 count++;
217 else
218 count = 0;
219 /*
220 * Ensure the QSPI controller is in true idle state after
221 * reading back the same idle status consecutively
222 */
223 if (count >= CQSPI_POLL_IDLE_RETRY)
224 return 1;
225 }
226
227 /* Timeout, still in busy mode. */
228 printf("QSPI: QSPI is still busy after poll for %d times.\n",
229 CQSPI_REG_RETRY);
230 return 0;
231 }
232
cadence_qspi_apb_readdata_capture(void * reg_base,unsigned int bypass,unsigned int delay)233 void cadence_qspi_apb_readdata_capture(void *reg_base,
234 unsigned int bypass, unsigned int delay)
235 {
236 unsigned int reg;
237 cadence_qspi_apb_controller_disable(reg_base);
238
239 reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE);
240
241 if (bypass)
242 reg |= CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
243 else
244 reg &= ~CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
245
246 reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK
247 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB);
248
249 reg |= (delay & CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK)
250 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB;
251
252 writel(reg, reg_base + CQSPI_REG_RD_DATA_CAPTURE);
253
254 cadence_qspi_apb_controller_enable(reg_base);
255 }
256
cadence_qspi_apb_config_baudrate_div(void * reg_base,unsigned int ref_clk_hz,unsigned int sclk_hz)257 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
258 unsigned int ref_clk_hz, unsigned int sclk_hz)
259 {
260 unsigned int reg;
261 unsigned int div;
262
263 cadence_qspi_apb_controller_disable(reg_base);
264 reg = readl(reg_base + CQSPI_REG_CONFIG);
265 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
266
267 /*
268 * The baud_div field in the config reg is 4 bits, and the ref clock is
269 * divided by 2 * (baud_div + 1). Round up the divider to ensure the
270 * SPI clock rate is less than or equal to the requested clock rate.
271 */
272 div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1;
273
274 /* ensure the baud rate doesn't exceed the max value */
275 if (div > CQSPI_REG_CONFIG_BAUD_MASK)
276 div = CQSPI_REG_CONFIG_BAUD_MASK;
277
278 debug("%s: ref_clk %dHz sclk %dHz Div 0x%x, actual %dHz\n", __func__,
279 ref_clk_hz, sclk_hz, div, ref_clk_hz / (2 * (div + 1)));
280
281 reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB);
282 writel(reg, reg_base + CQSPI_REG_CONFIG);
283
284 cadence_qspi_apb_controller_enable(reg_base);
285 }
286
cadence_qspi_apb_set_clk_mode(void * reg_base,uint mode)287 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode)
288 {
289 unsigned int reg;
290
291 cadence_qspi_apb_controller_disable(reg_base);
292 reg = readl(reg_base + CQSPI_REG_CONFIG);
293 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA);
294
295 if (mode & SPI_CPOL)
296 reg |= CQSPI_REG_CONFIG_CLK_POL;
297 if (mode & SPI_CPHA)
298 reg |= CQSPI_REG_CONFIG_CLK_PHA;
299
300 writel(reg, reg_base + CQSPI_REG_CONFIG);
301
302 cadence_qspi_apb_controller_enable(reg_base);
303 }
304
cadence_qspi_apb_chipselect(void * reg_base,unsigned int chip_select,unsigned int decoder_enable)305 void cadence_qspi_apb_chipselect(void *reg_base,
306 unsigned int chip_select, unsigned int decoder_enable)
307 {
308 unsigned int reg;
309
310 cadence_qspi_apb_controller_disable(reg_base);
311
312 debug("%s : chipselect %d decode %d\n", __func__, chip_select,
313 decoder_enable);
314
315 reg = readl(reg_base + CQSPI_REG_CONFIG);
316 /* docoder */
317 if (decoder_enable) {
318 reg |= CQSPI_REG_CONFIG_DECODE;
319 } else {
320 reg &= ~CQSPI_REG_CONFIG_DECODE;
321 /* Convert CS if without decoder.
322 * CS0 to 4b'1110
323 * CS1 to 4b'1101
324 * CS2 to 4b'1011
325 * CS3 to 4b'0111
326 */
327 chip_select = 0xF & ~(1 << chip_select);
328 }
329
330 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
331 << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
332 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
333 << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
334 writel(reg, reg_base + CQSPI_REG_CONFIG);
335
336 cadence_qspi_apb_controller_enable(reg_base);
337 }
338
cadence_qspi_apb_delay(void * reg_base,unsigned int ref_clk,unsigned int sclk_hz,unsigned int tshsl_ns,unsigned int tsd2d_ns,unsigned int tchsh_ns,unsigned int tslch_ns)339 void cadence_qspi_apb_delay(void *reg_base,
340 unsigned int ref_clk, unsigned int sclk_hz,
341 unsigned int tshsl_ns, unsigned int tsd2d_ns,
342 unsigned int tchsh_ns, unsigned int tslch_ns)
343 {
344 unsigned int ref_clk_ns;
345 unsigned int sclk_ns;
346 unsigned int tshsl, tchsh, tslch, tsd2d;
347 unsigned int reg;
348
349 cadence_qspi_apb_controller_disable(reg_base);
350
351 /* Convert to ns. */
352 ref_clk_ns = DIV_ROUND_UP(1000000000, ref_clk);
353
354 /* Convert to ns. */
355 sclk_ns = DIV_ROUND_UP(1000000000, sclk_hz);
356
357 /* The controller adds additional delay to that programmed in the reg */
358 if (tshsl_ns >= sclk_ns + ref_clk_ns)
359 tshsl_ns -= sclk_ns + ref_clk_ns;
360 if (tchsh_ns >= sclk_ns + 3 * ref_clk_ns)
361 tchsh_ns -= sclk_ns + 3 * ref_clk_ns;
362 tshsl = DIV_ROUND_UP(tshsl_ns, ref_clk_ns);
363 tchsh = DIV_ROUND_UP(tchsh_ns, ref_clk_ns);
364 tslch = DIV_ROUND_UP(tslch_ns, ref_clk_ns);
365 tsd2d = DIV_ROUND_UP(tsd2d_ns, ref_clk_ns);
366
367 reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
368 << CQSPI_REG_DELAY_TSHSL_LSB);
369 reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
370 << CQSPI_REG_DELAY_TCHSH_LSB);
371 reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
372 << CQSPI_REG_DELAY_TSLCH_LSB);
373 reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
374 << CQSPI_REG_DELAY_TSD2D_LSB);
375 writel(reg, reg_base + CQSPI_REG_DELAY);
376
377 cadence_qspi_apb_controller_enable(reg_base);
378 }
379
cadence_qspi_apb_controller_init(struct cadence_spi_plat * plat)380 void cadence_qspi_apb_controller_init(struct cadence_spi_plat *plat)
381 {
382 unsigned reg;
383
384 cadence_qspi_apb_controller_disable(plat->regbase);
385
386 /* Configure the device size and address bytes */
387 reg = readl(plat->regbase + CQSPI_REG_SIZE);
388 /* Clear the previous value */
389 reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
390 reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
391 reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
392 reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
393 writel(reg, plat->regbase + CQSPI_REG_SIZE);
394
395 /* Configure the remap address register, no remap */
396 writel(0, plat->regbase + CQSPI_REG_REMAP);
397
398 /* Indirect mode configurations */
399 writel(plat->fifo_depth / 2, plat->regbase + CQSPI_REG_SRAMPARTITION);
400
401 /* Disable all interrupts */
402 writel(0, plat->regbase + CQSPI_REG_IRQMASK);
403
404 cadence_qspi_apb_controller_enable(plat->regbase);
405 }
406
cadence_qspi_apb_exec_flash_cmd(void * reg_base,unsigned int reg)407 static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
408 unsigned int reg)
409 {
410 unsigned int retry = CQSPI_REG_RETRY;
411
412 /* Write the CMDCTRL without start execution. */
413 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
414 /* Start execute */
415 reg |= CQSPI_REG_CMDCTRL_EXECUTE;
416 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
417
418 while (retry--) {
419 reg = readl(reg_base + CQSPI_REG_CMDCTRL);
420 if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS) == 0)
421 break;
422 udelay(1);
423 }
424
425 if (!retry) {
426 printf("QSPI: flash command execution timeout\n");
427 return -EIO;
428 }
429
430 /* Polling QSPI idle status. */
431 if (!cadence_qspi_wait_idle(reg_base))
432 return -EIO;
433
434 return 0;
435 }
436
437 /* For command RDID, RDSR. */
cadence_qspi_apb_command_read(void * reg_base,const struct spi_mem_op * op)438 int cadence_qspi_apb_command_read(void *reg_base, const struct spi_mem_op *op)
439 {
440 unsigned int reg;
441 unsigned int read_len;
442 int status;
443 unsigned int rxlen = op->data.nbytes;
444 void *rxbuf = op->data.buf.in;
445
446 if (rxlen > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
447 printf("QSPI: Invalid input arguments rxlen %u\n", rxlen);
448 return -EINVAL;
449 }
450
451 reg = op->cmd.opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
452
453 reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
454
455 /* 0 means 1 byte. */
456 reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
457 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
458 status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
459 if (status != 0)
460 return status;
461
462 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
463
464 /* Put the read value into rx_buf */
465 read_len = (rxlen > 4) ? 4 : rxlen;
466 memcpy(rxbuf, ®, read_len);
467 rxbuf += read_len;
468
469 if (rxlen > 4) {
470 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
471
472 read_len = rxlen - read_len;
473 memcpy(rxbuf, ®, read_len);
474 }
475 return 0;
476 }
477
478 /* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
cadence_qspi_apb_command_write(void * reg_base,const struct spi_mem_op * op)479 int cadence_qspi_apb_command_write(void *reg_base, const struct spi_mem_op *op)
480 {
481 unsigned int reg = 0;
482 unsigned int wr_data;
483 unsigned int wr_len;
484 unsigned int txlen = op->data.nbytes;
485 const void *txbuf = op->data.buf.out;
486 u32 addr;
487
488 /* Reorder address to SPI bus order if only transferring address */
489 if (!txlen) {
490 addr = cpu_to_be32(op->addr.val);
491 if (op->addr.nbytes == 3)
492 addr >>= 8;
493 txbuf = &addr;
494 txlen = op->addr.nbytes;
495 }
496
497 if (txlen > CQSPI_STIG_DATA_LEN_MAX) {
498 printf("QSPI: Invalid input arguments txlen %u\n", txlen);
499 return -EINVAL;
500 }
501
502 reg |= op->cmd.opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
503
504 if (txlen) {
505 /* writing data = yes */
506 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
507 reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
508 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
509
510 wr_len = txlen > 4 ? 4 : txlen;
511 memcpy(&wr_data, txbuf, wr_len);
512 writel(wr_data, reg_base +
513 CQSPI_REG_CMDWRITEDATALOWER);
514
515 if (txlen > 4) {
516 txbuf += wr_len;
517 wr_len = txlen - wr_len;
518 memcpy(&wr_data, txbuf, wr_len);
519 writel(wr_data, reg_base +
520 CQSPI_REG_CMDWRITEDATAUPPER);
521 }
522 }
523
524 /* Execute the command */
525 return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
526 }
527
528 /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
cadence_qspi_apb_read_setup(struct cadence_spi_plat * plat,const struct spi_mem_op * op)529 int cadence_qspi_apb_read_setup(struct cadence_spi_plat *plat,
530 const struct spi_mem_op *op)
531 {
532 unsigned int reg;
533 unsigned int rd_reg;
534 unsigned int dummy_clk;
535 unsigned int dummy_bytes = op->dummy.nbytes;
536
537 /* Setup the indirect trigger address */
538 writel(plat->trigger_address,
539 plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
540
541 /* Configure the opcode */
542 rd_reg = op->cmd.opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
543
544 if (op->data.buswidth == 8)
545 /* Instruction and address at DQ0, data at DQ0-7. */
546 rd_reg |= CQSPI_INST_TYPE_OCTAL << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
547 else if (op->data.buswidth == 4)
548 /* Instruction and address at DQ0, data at DQ0-3. */
549 rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
550
551 writel(op->addr.val, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
552
553 if (dummy_bytes) {
554 if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
555 dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
556
557 /* Convert to clock cycles. */
558 dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
559
560 if (dummy_clk)
561 rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
562 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
563 }
564
565 writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);
566
567 /* set device size */
568 reg = readl(plat->regbase + CQSPI_REG_SIZE);
569 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
570 reg |= (op->addr.nbytes - 1);
571 writel(reg, plat->regbase + CQSPI_REG_SIZE);
572 return 0;
573 }
574
cadence_qspi_get_rd_sram_level(struct cadence_spi_plat * plat)575 static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_plat *plat)
576 {
577 u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL);
578 reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
579 return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
580 }
581
cadence_qspi_wait_for_data(struct cadence_spi_plat * plat)582 static int cadence_qspi_wait_for_data(struct cadence_spi_plat *plat)
583 {
584 unsigned int timeout = 10000;
585 u32 reg;
586
587 while (timeout--) {
588 reg = cadence_qspi_get_rd_sram_level(plat);
589 if (reg)
590 return reg;
591 udelay(1);
592 }
593
594 return -ETIMEDOUT;
595 }
596
597 static int
cadence_qspi_apb_indirect_read_execute(struct cadence_spi_plat * plat,unsigned int n_rx,u8 * rxbuf)598 cadence_qspi_apb_indirect_read_execute(struct cadence_spi_plat *plat,
599 unsigned int n_rx, u8 *rxbuf)
600 {
601 unsigned int remaining = n_rx;
602 unsigned int bytes_to_read = 0;
603 int ret;
604
605 writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
606
607 /* Start the indirect read transfer */
608 writel(CQSPI_REG_INDIRECTRD_START,
609 plat->regbase + CQSPI_REG_INDIRECTRD);
610
611 while (remaining > 0) {
612 ret = cadence_qspi_wait_for_data(plat);
613 if (ret < 0) {
614 printf("Indirect write timed out (%i)\n", ret);
615 goto failrd;
616 }
617
618 bytes_to_read = ret;
619
620 while (bytes_to_read != 0) {
621 bytes_to_read *= plat->fifo_width;
622 bytes_to_read = bytes_to_read > remaining ?
623 remaining : bytes_to_read;
624 /*
625 * Handle non-4-byte aligned access to avoid
626 * data abort.
627 */
628 if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
629 readsb(plat->ahbbase, rxbuf, bytes_to_read);
630 else
631 readsl(plat->ahbbase, rxbuf,
632 bytes_to_read >> 2);
633 rxbuf += bytes_to_read;
634 remaining -= bytes_to_read;
635 bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
636 }
637 }
638
639 /* Check indirect done status */
640 ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD,
641 CQSPI_REG_INDIRECTRD_DONE, 1, 10, 0);
642 if (ret) {
643 printf("Indirect read completion error (%i)\n", ret);
644 goto failrd;
645 }
646
647 /* Clear indirect completion status */
648 writel(CQSPI_REG_INDIRECTRD_DONE,
649 plat->regbase + CQSPI_REG_INDIRECTRD);
650
651 return 0;
652
653 failrd:
654 /* Cancel the indirect read */
655 writel(CQSPI_REG_INDIRECTRD_CANCEL,
656 plat->regbase + CQSPI_REG_INDIRECTRD);
657 return ret;
658 }
659
cadence_qspi_apb_read_execute(struct cadence_spi_plat * plat,const struct spi_mem_op * op)660 int cadence_qspi_apb_read_execute(struct cadence_spi_plat *plat,
661 const struct spi_mem_op *op)
662 {
663 u64 from = op->addr.val;
664 void *buf = op->data.buf.in;
665 size_t len = op->data.nbytes;
666
667 if (plat->use_dac_mode && (from + len < plat->ahbsize)) {
668 if (len < 256 ||
669 dma_memcpy(buf, plat->ahbbase + from, len) < 0) {
670 memcpy_fromio(buf, plat->ahbbase + from, len);
671 }
672 if (!cadence_qspi_wait_idle(plat->regbase))
673 return -EIO;
674 return 0;
675 }
676
677 return cadence_qspi_apb_indirect_read_execute(plat, len, buf);
678 }
679
680 /* Opcode + Address (3/4 bytes) */
cadence_qspi_apb_write_setup(struct cadence_spi_plat * plat,const struct spi_mem_op * op)681 int cadence_qspi_apb_write_setup(struct cadence_spi_plat *plat,
682 const struct spi_mem_op *op)
683 {
684 unsigned int reg;
685
686 /* Setup the indirect trigger address */
687 writel(plat->trigger_address,
688 plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
689
690 /* Configure the opcode */
691 reg = op->cmd.opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
692 writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
693
694 writel(op->addr.val, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
695
696 reg = readl(plat->regbase + CQSPI_REG_SIZE);
697 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
698 reg |= (op->addr.nbytes - 1);
699 writel(reg, plat->regbase + CQSPI_REG_SIZE);
700 return 0;
701 }
702
703 static int
cadence_qspi_apb_indirect_write_execute(struct cadence_spi_plat * plat,unsigned int n_tx,const u8 * txbuf)704 cadence_qspi_apb_indirect_write_execute(struct cadence_spi_plat *plat,
705 unsigned int n_tx, const u8 *txbuf)
706 {
707 unsigned int page_size = plat->page_size;
708 unsigned int remaining = n_tx;
709 const u8 *bb_txbuf = txbuf;
710 void *bounce_buf = NULL;
711 unsigned int write_bytes;
712 int ret;
713
714 /*
715 * Use bounce buffer for non 32 bit aligned txbuf to avoid data
716 * aborts
717 */
718 if ((uintptr_t)txbuf % 4) {
719 bounce_buf = malloc(n_tx);
720 if (!bounce_buf)
721 return -ENOMEM;
722 memcpy(bounce_buf, txbuf, n_tx);
723 bb_txbuf = bounce_buf;
724 }
725
726 /* Configure the indirect read transfer bytes */
727 writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
728
729 /* Start the indirect write transfer */
730 writel(CQSPI_REG_INDIRECTWR_START,
731 plat->regbase + CQSPI_REG_INDIRECTWR);
732
733 while (remaining > 0) {
734 write_bytes = remaining > page_size ? page_size : remaining;
735 writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);
736 if (write_bytes % 4)
737 writesb(plat->ahbbase,
738 bb_txbuf + rounddown(write_bytes, 4),
739 write_bytes % 4);
740
741 ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_SDRAMLEVEL,
742 CQSPI_REG_SDRAMLEVEL_WR_MASK <<
743 CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
744 if (ret) {
745 printf("Indirect write timed out (%i)\n", ret);
746 goto failwr;
747 }
748
749 bb_txbuf += write_bytes;
750 remaining -= write_bytes;
751 }
752
753 /* Check indirect done status */
754 ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTWR,
755 CQSPI_REG_INDIRECTWR_DONE, 1, 10, 0);
756 if (ret) {
757 printf("Indirect write completion error (%i)\n", ret);
758 goto failwr;
759 }
760
761 /* Clear indirect completion status */
762 writel(CQSPI_REG_INDIRECTWR_DONE,
763 plat->regbase + CQSPI_REG_INDIRECTWR);
764 if (bounce_buf)
765 free(bounce_buf);
766 return 0;
767
768 failwr:
769 /* Cancel the indirect write */
770 writel(CQSPI_REG_INDIRECTWR_CANCEL,
771 plat->regbase + CQSPI_REG_INDIRECTWR);
772 if (bounce_buf)
773 free(bounce_buf);
774 return ret;
775 }
776
cadence_qspi_apb_write_execute(struct cadence_spi_plat * plat,const struct spi_mem_op * op)777 int cadence_qspi_apb_write_execute(struct cadence_spi_plat *plat,
778 const struct spi_mem_op *op)
779 {
780 u32 to = op->addr.val;
781 const void *buf = op->data.buf.out;
782 size_t len = op->data.nbytes;
783
784 if (plat->use_dac_mode && (to + len < plat->ahbsize)) {
785 memcpy_toio(plat->ahbbase + to, buf, len);
786 if (!cadence_qspi_wait_idle(plat->regbase))
787 return -EIO;
788 return 0;
789 }
790
791 return cadence_qspi_apb_indirect_write_execute(plat, len, buf);
792 }
793
cadence_qspi_apb_enter_xip(void * reg_base,char xip_dummy)794 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
795 {
796 unsigned int reg;
797
798 /* enter XiP mode immediately and enable direct mode */
799 reg = readl(reg_base + CQSPI_REG_CONFIG);
800 reg |= CQSPI_REG_CONFIG_ENABLE;
801 reg |= CQSPI_REG_CONFIG_DIRECT;
802 reg |= CQSPI_REG_CONFIG_XIP_IMM;
803 writel(reg, reg_base + CQSPI_REG_CONFIG);
804
805 /* keep the XiP mode */
806 writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
807
808 /* Enable mode bit at devrd */
809 reg = readl(reg_base + CQSPI_REG_RD_INSTR);
810 reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
811 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
812 }
813