1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * CPPI5 descriptors interface
4 *
5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
6 */
7
8 #ifndef __TI_CPPI5_H__
9 #define __TI_CPPI5_H__
10
11 #include <hexdump.h>
12 #include <linux/bitops.h>
13 #include <linux/bug.h>
14
15 /**
16 * Descriptor header, present in all types of descriptors
17 */
18 struct cppi5_desc_hdr_t {
19 u32 pkt_info0; /* Packet info word 0 (n/a in Buffer desc) */
20 u32 pkt_info1; /* Packet info word 1 (n/a in Buffer desc) */
21 u32 pkt_info2; /* Packet info word 2 Buffer reclamation info */
22 u32 src_dst_tag; /* Packet info word 3 (n/a in Buffer desc) */
23 } __packed;
24
25 /**
26 * Host-mode packet and buffer descriptor definition
27 */
28 struct cppi5_host_desc_t {
29 struct cppi5_desc_hdr_t hdr;
30 u64 next_desc; /* w4/5: Linking word */
31 u64 buf_ptr; /* w6/7: Buffer pointer */
32 u32 buf_info1; /* w8: Buffer valid data length */
33 u32 org_buf_len; /* w9: Original buffer length */
34 u64 org_buf_ptr; /* w10/11: Original buffer pointer */
35 u32 epib[0]; /* Extended Packet Info Data (optional, 4 words) */
36 /*
37 * Protocol Specific Data (optional, 0-128 bytes in multiples of 4),
38 * and/or Other Software Data (0-N bytes, optional)
39 */
40 } __packed;
41
42 #define CPPI5_DESC_MIN_ALIGN (16U)
43
44 #define CPPI5_INFO0_HDESC_EPIB_SIZE (16U)
45 #define CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE (128U)
46
47 #define CPPI5_INFO0_HDESC_TYPE_SHIFT (30U)
48 #define CPPI5_INFO0_HDESC_TYPE_MASK GENMASK(31, 30)
49 #define CPPI5_INFO0_DESC_TYPE_VAL_HOST (1U)
50 #define CPPI5_INFO0_DESC_TYPE_VAL_MONO (2U)
51 #define CPPI5_INFO0_DESC_TYPE_VAL_TR (3U)
52 #define CPPI5_INFO0_HDESC_EPIB_PRESENT BIT(29)
53 /*
54 * Protocol Specific Words location:
55 * 0 - located in the descriptor,
56 * 1 = located in the SOP Buffer immediately prior to the data.
57 */
58 #define CPPI5_INFO0_HDESC_PSINFO_LOCATION BIT(28)
59 #define CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT (22U)
60 #define CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK GENMASK(27, 22)
61 #define CPPI5_INFO0_HDESC_PKTLEN_SHIFT (0)
62 #define CPPI5_INFO0_HDESC_PKTLEN_MASK GENMASK(21, 0)
63
64 #define CPPI5_INFO1_DESC_PKTERROR_SHIFT (28U)
65 #define CPPI5_INFO1_DESC_PKTERROR_MASK GENMASK(31, 28)
66 #define CPPI5_INFO1_HDESC_PSFLGS_SHIFT (24U)
67 #define CPPI5_INFO1_HDESC_PSFLGS_MASK GENMASK(27, 24)
68 #define CPPI5_INFO1_DESC_PKTID_SHIFT (14U)
69 #define CPPI5_INFO1_DESC_PKTID_MASK GENMASK(23, 14)
70 #define CPPI5_INFO1_DESC_FLOWID_SHIFT (0)
71 #define CPPI5_INFO1_DESC_FLOWID_MASK GENMASK(13, 0)
72
73 #define CPPI5_INFO2_HDESC_PKTTYPE_SHIFT (27U)
74 #define CPPI5_INFO2_HDESC_PKTTYPE_MASK GENMASK(31, 27)
75 /* Return Policy: 0 - Entire packet 1 - Each buffer */
76 #define CPPI5_INFO2_HDESC_RETPOLICY BIT(18)
77 /*
78 * Early Return:
79 * 0 = desc pointers should be returned after all reads have been completed
80 * 1 = desc pointers should be returned immediately upon fetching
81 * the descriptor and beginning to transfer data.
82 */
83 #define CPPI5_INFO2_HDESC_EARLYRET BIT(17)
84 /*
85 * Return Push Policy:
86 * 0 = Descriptor must be returned to tail of queue
87 * 1 = Descriptor must be returned to head of queue
88 */
89 #define CPPI5_INFO2_DESC_RETPUSHPOLICY BIT(16)
90 #define CPPI5_INFO2_DESC_RETQ_SHIFT (0)
91 #define CPPI5_INFO2_DESC_RETQ_MASK GENMASK(15, 0)
92
93 #define CPPI5_INFO3_DESC_SRCTAG_SHIFT (16U)
94 #define CPPI5_INFO3_DESC_SRCTAG_MASK GENMASK(31, 16)
95 #define CPPI5_INFO3_DESC_DSTTAG_SHIFT (0)
96 #define CPPI5_INFO3_DESC_DSTTAG_MASK GENMASK(15, 0)
97
98 #define CPPI5_BUFINFO1_HDESC_DATA_LEN_SHIFT (0)
99 #define CPPI5_BUFINFO1_HDESC_DATA_LEN_MASK GENMASK(27, 0)
100
101 #define CPPI5_OBUFINFO0_HDESC_BUF_LEN_SHIFT (0)
102 #define CPPI5_OBUFINFO0_HDESC_BUF_LEN_MASK GENMASK(27, 0)
103
104 /*
105 * Host Packet Descriptor Extended Packet Info Block
106 */
107 struct cppi5_desc_epib_t {
108 u32 timestamp; /* w0: application specific timestamp */
109 u32 sw_info0; /* w1: Software Info 0 */
110 u32 sw_info1; /* w2: Software Info 1 */
111 u32 sw_info2; /* w3: Software Info 2 */
112 };
113
114 /**
115 * Monolithic-mode packet descriptor
116 */
117 struct cppi5_monolithic_desc_t {
118 struct cppi5_desc_hdr_t hdr;
119 u32 epib[0]; /* Extended Packet Info Data (optional, 4 words) */
120 /*
121 * Protocol Specific Data (optional, 0-128 bytes in multiples of 4),
122 * and/or Other Software Data (0-N bytes, optional)
123 */
124 };
125
126 #define CPPI5_INFO2_MDESC_DATA_OFFSET_SHIFT (18U)
127 #define CPPI5_INFO2_MDESC_DATA_OFFSET_MASK GENMASK(26, 18)
128
129 /*
130 * Reload Enable:
131 * 0 = Finish the packet and place the descriptor back on the return queue
132 * 1 = Vector to the Reload Index and resume processing
133 */
134 #define CPPI5_INFO0_TRDESC_RLDCNT_SHIFT (20U)
135 #define CPPI5_INFO0_TRDESC_RLDCNT_MASK GENMASK(28, 20)
136 #define CPPI5_INFO0_TRDESC_RLDCNT_MAX (0x1ff)
137 #define CPPI5_INFO0_TRDESC_RLDCNT_INFINITE CPPI5_INFO0_TRDESC_RLDCNT_MAX
138 #define CPPI5_INFO0_TRDESC_RLDIDX_SHIFT (14U)
139 #define CPPI5_INFO0_TRDESC_RLDIDX_MASK GENMASK(19, 14)
140 #define CPPI5_INFO0_TRDESC_RLDIDX_MAX (0x3f)
141 #define CPPI5_INFO0_TRDESC_LASTIDX_SHIFT (0)
142 #define CPPI5_INFO0_TRDESC_LASTIDX_MASK GENMASK(13, 0)
143
144 #define CPPI5_INFO1_TRDESC_RECSIZE_SHIFT (24U)
145 #define CPPI5_INFO1_TRDESC_RECSIZE_MASK GENMASK(26, 24)
146 #define CPPI5_INFO1_TRDESC_RECSIZE_VAL_16B (0)
147 #define CPPI5_INFO1_TRDESC_RECSIZE_VAL_32B (1U)
148 #define CPPI5_INFO1_TRDESC_RECSIZE_VAL_64B (2U)
149 #define CPPI5_INFO1_TRDESC_RECSIZE_VAL_128B (3U)
150
cppi5_desc_dump(void * desc,u32 size)151 static inline void cppi5_desc_dump(void *desc, u32 size)
152 {
153 print_hex_dump(KERN_ERR "dump udmap_desc: ", DUMP_PREFIX_NONE,
154 32, 4, desc, size, false);
155 }
156
157 /**
158 * cppi5_desc_get_type - get descriptor type
159 * @desc_hdr: packet descriptor/TR header
160 *
161 * Returns descriptor type:
162 * CPPI5_INFO0_DESC_TYPE_VAL_HOST
163 * CPPI5_INFO0_DESC_TYPE_VAL_MONO
164 * CPPI5_INFO0_DESC_TYPE_VAL_TR
165 */
cppi5_desc_get_type(struct cppi5_desc_hdr_t * desc_hdr)166 static inline u32 cppi5_desc_get_type(struct cppi5_desc_hdr_t *desc_hdr)
167 {
168 WARN_ON(!desc_hdr);
169
170 return (desc_hdr->pkt_info0 & CPPI5_INFO0_HDESC_TYPE_MASK) >>
171 CPPI5_INFO0_HDESC_TYPE_SHIFT;
172 }
173
174 /**
175 * cppi5_desc_get_errflags - get Error Flags from Desc
176 * @desc_hdr: packet/TR descriptor header
177 *
178 * Returns Error Flags from Packet/TR Descriptor
179 */
cppi5_desc_get_errflags(struct cppi5_desc_hdr_t * desc_hdr)180 static inline u32 cppi5_desc_get_errflags(struct cppi5_desc_hdr_t *desc_hdr)
181 {
182 WARN_ON(!desc_hdr);
183
184 return (desc_hdr->pkt_info1 & CPPI5_INFO1_DESC_PKTERROR_MASK) >>
185 CPPI5_INFO1_DESC_PKTERROR_SHIFT;
186 }
187
188 /**
189 * cppi5_desc_get_pktids - get Packet and Flow ids from Desc
190 * @desc_hdr: packet/TR descriptor header
191 * @pkt_id: Packet ID
192 * @flow_id: Flow ID
193 *
194 * Returns Packet and Flow ids from packet/TR descriptor
195 */
cppi5_desc_get_pktids(struct cppi5_desc_hdr_t * desc_hdr,u32 * pkt_id,u32 * flow_id)196 static inline void cppi5_desc_get_pktids(struct cppi5_desc_hdr_t *desc_hdr,
197 u32 *pkt_id, u32 *flow_id)
198 {
199 WARN_ON(!desc_hdr);
200
201 *pkt_id = (desc_hdr->pkt_info1 & CPPI5_INFO1_DESC_PKTID_MASK) >>
202 CPPI5_INFO1_DESC_PKTID_SHIFT;
203 *flow_id = (desc_hdr->pkt_info1 & CPPI5_INFO1_DESC_FLOWID_MASK) >>
204 CPPI5_INFO1_DESC_FLOWID_SHIFT;
205 }
206
207 /**
208 * cppi5_desc_set_pktids - set Packet and Flow ids in Desc
209 * @desc_hdr: packet/TR descriptor header
210 * @pkt_id: Packet ID
211 * @flow_id: Flow ID
212 */
cppi5_desc_set_pktids(struct cppi5_desc_hdr_t * desc_hdr,u32 pkt_id,u32 flow_id)213 static inline void cppi5_desc_set_pktids(struct cppi5_desc_hdr_t *desc_hdr,
214 u32 pkt_id, u32 flow_id)
215 {
216 WARN_ON(!desc_hdr);
217
218 desc_hdr->pkt_info1 |= (pkt_id << CPPI5_INFO1_DESC_PKTID_SHIFT) &
219 CPPI5_INFO1_DESC_PKTID_MASK;
220 desc_hdr->pkt_info1 |= (flow_id << CPPI5_INFO1_DESC_FLOWID_SHIFT) &
221 CPPI5_INFO1_DESC_FLOWID_MASK;
222 }
223
224 /**
225 * cppi5_desc_set_retpolicy - set Packet Return Policy in Desc
226 * @desc_hdr: packet/TR descriptor header
227 * @flags: fags, supported values
228 * CPPI5_INFO2_HDESC_RETPOLICY
229 * CPPI5_INFO2_HDESC_EARLYRET
230 * CPPI5_INFO2_DESC_RETPUSHPOLICY
231 * @return_ring_id: Packet Return Queue/Ring id, value 0xFFFF reserved
232 */
cppi5_desc_set_retpolicy(struct cppi5_desc_hdr_t * desc_hdr,u32 flags,u32 return_ring_id)233 static inline void cppi5_desc_set_retpolicy(struct cppi5_desc_hdr_t *desc_hdr,
234 u32 flags, u32 return_ring_id)
235 {
236 WARN_ON(!desc_hdr);
237
238 desc_hdr->pkt_info2 |= flags;
239 desc_hdr->pkt_info2 |= return_ring_id & CPPI5_INFO2_DESC_RETQ_MASK;
240 }
241
242 /**
243 * cppi5_desc_get_tags_ids - get Packet Src/Dst Tags from Desc
244 * @desc_hdr: packet/TR descriptor header
245 * @src_tag_id: Source Tag
246 * @dst_tag_id: Dest Tag
247 *
248 * Returns Packet Src/Dst Tags from packet/TR descriptor
249 */
cppi5_desc_get_tags_ids(struct cppi5_desc_hdr_t * desc_hdr,u32 * src_tag_id,u32 * dst_tag_id)250 static inline void cppi5_desc_get_tags_ids(struct cppi5_desc_hdr_t *desc_hdr,
251 u32 *src_tag_id, u32 *dst_tag_id)
252 {
253 WARN_ON(!desc_hdr);
254
255 if (src_tag_id)
256 *src_tag_id = (desc_hdr->src_dst_tag &
257 CPPI5_INFO3_DESC_SRCTAG_MASK) >>
258 CPPI5_INFO3_DESC_SRCTAG_SHIFT;
259 if (dst_tag_id)
260 *dst_tag_id = desc_hdr->src_dst_tag &
261 CPPI5_INFO3_DESC_DSTTAG_MASK;
262 }
263
264 /**
265 * cppi5_desc_set_tags_ids - set Packet Src/Dst Tags in HDesc
266 * @desc_hdr: packet/TR descriptor header
267 * @src_tag_id: Source Tag
268 * @dst_tag_id: Dest Tag
269 *
270 * Returns Packet Src/Dst Tags from packet/TR descriptor
271 */
cppi5_desc_set_tags_ids(struct cppi5_desc_hdr_t * desc_hdr,u32 src_tag_id,u32 dst_tag_id)272 static inline void cppi5_desc_set_tags_ids(struct cppi5_desc_hdr_t *desc_hdr,
273 u32 src_tag_id, u32 dst_tag_id)
274 {
275 WARN_ON(!desc_hdr);
276
277 desc_hdr->src_dst_tag = (src_tag_id << CPPI5_INFO3_DESC_SRCTAG_SHIFT) &
278 CPPI5_INFO3_DESC_SRCTAG_MASK;
279 desc_hdr->src_dst_tag |= dst_tag_id & CPPI5_INFO3_DESC_DSTTAG_MASK;
280 }
281
282 /**
283 * cppi5_hdesc_calc_size - Calculate Host Packet Descriptor size
284 * @epib: is EPIB present
285 * @psdata_size: PSDATA size
286 * @sw_data_size: SWDATA size
287 *
288 * Returns required Host Packet Descriptor size
289 * 0 - if PSDATA > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE
290 */
cppi5_hdesc_calc_size(bool epib,u32 psdata_size,u32 sw_data_size)291 static inline u32 cppi5_hdesc_calc_size(bool epib, u32 psdata_size,
292 u32 sw_data_size)
293 {
294 u32 desc_size;
295
296 if (psdata_size > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE)
297 return 0;
298 //TODO_GS: align
299 desc_size = sizeof(struct cppi5_host_desc_t) + psdata_size +
300 sw_data_size;
301
302 if (epib)
303 desc_size += CPPI5_INFO0_HDESC_EPIB_SIZE;
304
305 return ALIGN(desc_size, CPPI5_DESC_MIN_ALIGN);
306 }
307
308 /**
309 * cppi5_hdesc_init - Init Host Packet Descriptor size
310 * @desc: Host packet descriptor
311 * @flags: supported values
312 * CPPI5_INFO0_HDESC_EPIB_PRESENT
313 * CPPI5_INFO0_HDESC_PSINFO_LOCATION
314 * @psdata_size: PSDATA size
315 *
316 * Returns required Host Packet Descriptor size
317 * 0 - if PSDATA > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE
318 */
cppi5_hdesc_init(struct cppi5_host_desc_t * desc,u32 flags,u32 psdata_size)319 static inline void cppi5_hdesc_init(struct cppi5_host_desc_t *desc, u32 flags,
320 u32 psdata_size)
321 {
322 WARN_ON(!desc);
323 WARN_ON(psdata_size > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE);
324 WARN_ON(flags & ~(CPPI5_INFO0_HDESC_EPIB_PRESENT |
325 CPPI5_INFO0_HDESC_PSINFO_LOCATION));
326
327 desc->hdr.pkt_info0 = (CPPI5_INFO0_DESC_TYPE_VAL_HOST <<
328 CPPI5_INFO0_HDESC_TYPE_SHIFT) | (flags);
329 desc->hdr.pkt_info0 |= ((psdata_size >> 2) <<
330 CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT) &
331 CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK;
332 desc->next_desc = 0;
333 }
334
335 /**
336 * cppi5_hdesc_update_flags - Replace descriptor flags
337 * @desc: Host packet descriptor
338 * @flags: supported values
339 * CPPI5_INFO0_HDESC_EPIB_PRESENT
340 * CPPI5_INFO0_HDESC_PSINFO_LOCATION
341 */
cppi5_hdesc_update_flags(struct cppi5_host_desc_t * desc,u32 flags)342 static inline void cppi5_hdesc_update_flags(struct cppi5_host_desc_t *desc,
343 u32 flags)
344 {
345 WARN_ON(!desc);
346 WARN_ON(flags & ~(CPPI5_INFO0_HDESC_EPIB_PRESENT |
347 CPPI5_INFO0_HDESC_PSINFO_LOCATION));
348
349 desc->hdr.pkt_info0 &= ~(CPPI5_INFO0_HDESC_EPIB_PRESENT |
350 CPPI5_INFO0_HDESC_PSINFO_LOCATION);
351 desc->hdr.pkt_info0 |= flags;
352 }
353
354 /**
355 * cppi5_hdesc_update_psdata_size - Replace PSdata size
356 * @desc: Host packet descriptor
357 * @psdata_size: PSDATA size
358 */
cppi5_hdesc_update_psdata_size(struct cppi5_host_desc_t * desc,u32 psdata_size)359 static inline void cppi5_hdesc_update_psdata_size(
360 struct cppi5_host_desc_t *desc, u32 psdata_size)
361 {
362 WARN_ON(!desc);
363 WARN_ON(psdata_size > CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE);
364
365 desc->hdr.pkt_info0 &= ~CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK;
366 desc->hdr.pkt_info0 |= ((psdata_size >> 2) <<
367 CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT) &
368 CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK;
369 }
370
371 /**
372 * cppi5_hdesc_get_psdata_size - get PSdata size in bytes
373 * @desc: Host packet descriptor
374 */
cppi5_hdesc_get_psdata_size(struct cppi5_host_desc_t * desc)375 static inline u32 cppi5_hdesc_get_psdata_size(struct cppi5_host_desc_t *desc)
376 {
377 u32 psdata_size = 0;
378
379 WARN_ON(!desc);
380
381 if (!(desc->hdr.pkt_info0 & CPPI5_INFO0_HDESC_PSINFO_LOCATION))
382 psdata_size = (desc->hdr.pkt_info0 &
383 CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK) >>
384 CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT;
385
386 return (psdata_size << 2);
387 }
388
389 /**
390 * cppi5_hdesc_get_pktlen - get Packet Length from HDesc
391 * @desc: Host packet descriptor
392 *
393 * Returns Packet Length from Host Packet Descriptor
394 */
cppi5_hdesc_get_pktlen(struct cppi5_host_desc_t * desc)395 static inline u32 cppi5_hdesc_get_pktlen(struct cppi5_host_desc_t *desc)
396 {
397 WARN_ON(!desc);
398
399 return (desc->hdr.pkt_info0 & CPPI5_INFO0_HDESC_PKTLEN_MASK);
400 }
401
402 /**
403 * cppi5_hdesc_set_pktlen - set Packet Length in HDesc
404 * @desc: Host packet descriptor
405 */
cppi5_hdesc_set_pktlen(struct cppi5_host_desc_t * desc,u32 pkt_len)406 static inline void cppi5_hdesc_set_pktlen(struct cppi5_host_desc_t *desc,
407 u32 pkt_len)
408 {
409 WARN_ON(!desc);
410
411 desc->hdr.pkt_info0 |= (pkt_len & CPPI5_INFO0_HDESC_PKTLEN_MASK);
412 }
413
414 /**
415 * cppi5_hdesc_get_psflags - get Protocol Specific Flags from HDesc
416 * @desc: Host packet descriptor
417 *
418 * Returns Protocol Specific Flags from Host Packet Descriptor
419 */
cppi5_hdesc_get_psflags(struct cppi5_host_desc_t * desc)420 static inline u32 cppi5_hdesc_get_psflags(struct cppi5_host_desc_t *desc)
421 {
422 WARN_ON(!desc);
423
424 return (desc->hdr.pkt_info1 & CPPI5_INFO1_HDESC_PSFLGS_MASK) >>
425 CPPI5_INFO1_HDESC_PSFLGS_SHIFT;
426 }
427
428 /**
429 * cppi5_hdesc_set_psflags - set Protocol Specific Flags in HDesc
430 * @desc: Host packet descriptor
431 */
cppi5_hdesc_set_psflags(struct cppi5_host_desc_t * desc,u32 ps_flags)432 static inline void cppi5_hdesc_set_psflags(struct cppi5_host_desc_t *desc,
433 u32 ps_flags)
434 {
435 WARN_ON(!desc);
436
437 desc->hdr.pkt_info1 |= (ps_flags <<
438 CPPI5_INFO1_HDESC_PSFLGS_SHIFT) &
439 CPPI5_INFO1_HDESC_PSFLGS_MASK;
440 }
441
442 /**
443 * cppi5_hdesc_get_errflags - get Packet Type from HDesc
444 * @desc: Host packet descriptor
445 */
cppi5_hdesc_get_pkttype(struct cppi5_host_desc_t * desc)446 static inline u32 cppi5_hdesc_get_pkttype(struct cppi5_host_desc_t *desc)
447 {
448 WARN_ON(!desc);
449
450 return (desc->hdr.pkt_info2 & CPPI5_INFO2_HDESC_PKTTYPE_MASK) >>
451 CPPI5_INFO2_HDESC_PKTTYPE_SHIFT;
452 }
453
454 /**
455 * cppi5_hdesc_get_errflags - set Packet Type in HDesc
456 * @desc: Host packet descriptor
457 * @pkt_type: Packet Type
458 */
cppi5_hdesc_set_pkttype(struct cppi5_host_desc_t * desc,u32 pkt_type)459 static inline void cppi5_hdesc_set_pkttype(struct cppi5_host_desc_t *desc,
460 u32 pkt_type)
461 {
462 WARN_ON(!desc);
463 desc->hdr.pkt_info2 |=
464 (pkt_type << CPPI5_INFO2_HDESC_PKTTYPE_SHIFT) &
465 CPPI5_INFO2_HDESC_PKTTYPE_MASK;
466 }
467
468 /**
469 * cppi5_hdesc_attach_buf - attach buffer to HDesc
470 * @desc: Host packet descriptor
471 * @buf: Buffer physical address
472 * @buf_data_len: Buffer length
473 * @obuf: Original Buffer physical address
474 * @obuf_len: Original Buffer length
475 *
476 * Attaches buffer to Host Packet Descriptor
477 */
cppi5_hdesc_attach_buf(struct cppi5_host_desc_t * desc,dma_addr_t buf,u32 buf_data_len,dma_addr_t obuf,u32 obuf_len)478 static inline void cppi5_hdesc_attach_buf(struct cppi5_host_desc_t *desc,
479 dma_addr_t buf, u32 buf_data_len,
480 dma_addr_t obuf, u32 obuf_len)
481 {
482 WARN_ON(!desc);
483 WARN_ON(!buf && !obuf);
484
485 desc->buf_ptr = buf;
486 desc->buf_info1 = buf_data_len & CPPI5_BUFINFO1_HDESC_DATA_LEN_MASK;
487 desc->org_buf_ptr = obuf;
488 desc->org_buf_len = obuf_len & CPPI5_OBUFINFO0_HDESC_BUF_LEN_MASK;
489 }
490
cppi5_hdesc_get_obuf(struct cppi5_host_desc_t * desc,dma_addr_t * obuf,u32 * obuf_len)491 static inline void cppi5_hdesc_get_obuf(struct cppi5_host_desc_t *desc,
492 dma_addr_t *obuf, u32 *obuf_len)
493 {
494 WARN_ON(!desc);
495 WARN_ON(!obuf);
496 WARN_ON(!obuf_len);
497
498 *obuf = desc->org_buf_ptr;
499 *obuf_len = desc->org_buf_len & CPPI5_OBUFINFO0_HDESC_BUF_LEN_MASK;
500 }
501
cppi5_hdesc_reset_to_original(struct cppi5_host_desc_t * desc)502 static inline void cppi5_hdesc_reset_to_original(struct cppi5_host_desc_t *desc)
503 {
504 WARN_ON(!desc);
505
506 desc->buf_ptr = desc->org_buf_ptr;
507 desc->buf_info1 = desc->org_buf_len;
508 }
509
510 /**
511 * cppi5_hdesc_link_hbdesc - link Host Buffer Descriptor to HDesc
512 * @desc: Host Packet Descriptor
513 * @buf_desc: Host Buffer Descriptor physical address
514 *
515 * add and link Host Buffer Descriptor to HDesc
516 */
cppi5_hdesc_link_hbdesc(struct cppi5_host_desc_t * desc,dma_addr_t hbuf_desc)517 static inline void cppi5_hdesc_link_hbdesc(struct cppi5_host_desc_t *desc,
518 dma_addr_t hbuf_desc)
519 {
520 WARN_ON(!desc);
521 WARN_ON(!hbuf_desc);
522
523 desc->next_desc = hbuf_desc;
524 }
525
cppi5_hdesc_get_next_hbdesc(struct cppi5_host_desc_t * desc)526 static inline dma_addr_t cppi5_hdesc_get_next_hbdesc(
527 struct cppi5_host_desc_t *desc)
528 {
529 WARN_ON(!desc);
530
531 return (dma_addr_t)desc->next_desc;
532 }
533
cppi5_hdesc_reset_hbdesc(struct cppi5_host_desc_t * desc)534 static inline void cppi5_hdesc_reset_hbdesc(struct cppi5_host_desc_t *desc)
535 {
536 WARN_ON(!desc);
537
538 desc->hdr = (struct cppi5_desc_hdr_t) { 0 };
539 desc->next_desc = 0;
540 }
541
542 /**
543 * cppi5_hdesc_epib_present - check if EPIB present
544 * @desc_hdr: packet descriptor/TR header
545 *
546 * Returns true if EPIB present in the packet
547 */
cppi5_hdesc_epib_present(struct cppi5_desc_hdr_t * desc_hdr)548 static inline bool cppi5_hdesc_epib_present(struct cppi5_desc_hdr_t *desc_hdr)
549 {
550 WARN_ON(!desc_hdr);
551 return !!(desc_hdr->pkt_info0 & CPPI5_INFO0_HDESC_EPIB_PRESENT);
552 }
553
554 /**
555 * cppi5_hdesc_get_psdata - Get pointer on PSDATA
556 * @desc: Host packet descriptor
557 *
558 * Returns pointer on PSDATA in HDesc.
559 * NULL - if ps_data placed at the start of data buffer.
560 */
cppi5_hdesc_get_psdata(struct cppi5_host_desc_t * desc)561 static inline void *cppi5_hdesc_get_psdata(struct cppi5_host_desc_t *desc)
562 {
563 u32 psdata_size;
564 void *psdata;
565
566 WARN_ON(!desc);
567
568 if (desc->hdr.pkt_info0 & CPPI5_INFO0_HDESC_PSINFO_LOCATION)
569 return NULL;
570
571 psdata_size = (desc->hdr.pkt_info0 &
572 CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK) >>
573 CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT;
574
575 if (!psdata_size)
576 return NULL;
577
578 psdata = &desc->epib;
579
580 if (cppi5_hdesc_epib_present(&desc->hdr))
581 psdata += CPPI5_INFO0_HDESC_EPIB_SIZE;
582
583 return psdata;
584 }
585
cppi5_hdesc_get_psdata32(struct cppi5_host_desc_t * desc)586 static inline u32 *cppi5_hdesc_get_psdata32(struct cppi5_host_desc_t *desc)
587 {
588 return (u32 *)cppi5_hdesc_get_psdata(desc);
589 }
590
591 /**
592 * cppi5_hdesc_get_swdata - Get pointer on swdata
593 * @desc: Host packet descriptor
594 *
595 * Returns pointer on SWDATA in HDesc.
596 * NOTE. It's caller responsibility to be sure hdesc actually has swdata.
597 */
cppi5_hdesc_get_swdata(struct cppi5_host_desc_t * desc)598 static inline void *cppi5_hdesc_get_swdata(struct cppi5_host_desc_t *desc)
599 {
600 u32 psdata_size = 0;
601 void *swdata;
602
603 WARN_ON(!desc);
604
605 if (!(desc->hdr.pkt_info0 & CPPI5_INFO0_HDESC_PSINFO_LOCATION))
606 psdata_size = (desc->hdr.pkt_info0 &
607 CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK) >>
608 CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT;
609
610 swdata = &desc->epib;
611
612 if (cppi5_hdesc_epib_present(&desc->hdr))
613 swdata += CPPI5_INFO0_HDESC_EPIB_SIZE;
614
615 swdata += (psdata_size << 2);
616
617 return swdata;
618 }
619
620 /* ================================== TR ================================== */
621
622 #define CPPI5_TR_TYPE_SHIFT (0U)
623 #define CPPI5_TR_TYPE_MASK GENMASK(3, 0)
624 #define CPPI5_TR_STATIC BIT(4)
625 #define CPPI5_TR_WAIT BIT(5)
626 #define CPPI5_TR_EVENT_SIZE_SHIFT (6U)
627 #define CPPI5_TR_EVENT_SIZE_MASK GENMASK(7, 6)
628 #define CPPI5_TR_TRIGGER0_SHIFT (8U)
629 #define CPPI5_TR_TRIGGER0_MASK GENMASK(9, 8)
630 #define CPPI5_TR_TRIGGER0_TYPE_SHIFT (10U)
631 #define CPPI5_TR_TRIGGER0_TYPE_MASK GENMASK(11, 10)
632 #define CPPI5_TR_TRIGGER1_SHIFT (12U)
633 #define CPPI5_TR_TRIGGER1_MASK GENMASK(13, 12)
634 #define CPPI5_TR_TRIGGER1_TYPE_SHIFT (14U)
635 #define CPPI5_TR_TRIGGER1_TYPE_MASK GENMASK(15, 14)
636 #define CPPI5_TR_CMD_ID_SHIFT (16U)
637 #define CPPI5_TR_CMD_ID_MASK GENMASK(23, 16)
638 #define CPPI5_TR_CSF_FLAGS_SHIFT (24U)
639 #define CPPI5_TR_CSF_FLAGS_MASK GENMASK(31, 24)
640 #define CPPI5_TR_CSF_SA_INDIRECT BIT(0)
641 #define CPPI5_TR_CSF_DA_INDIRECT BIT(1)
642 #define CPPI5_TR_CSF_SUPR_EVT BIT(2)
643 #define CPPI5_TR_CSF_EOL_ADV_SHIFT (4U)
644 #define CPPI5_TR_CSF_EOL_ADV_MASK GENMASK(6, 4)
645 #define CPPI5_TR_CSF_EOP BIT(7)
646
647 /* Udmap TR flags Type field specifies the type of TR. */
648 enum cppi5_tr_types {
649 /* type0: One dimensional data move */
650 CPPI5_TR_TYPE0 = 0,
651 /* type1: Two dimensional data move */
652 CPPI5_TR_TYPE1,
653 /* type2: Three dimensional data move */
654 CPPI5_TR_TYPE2,
655 /* type3: Four dimensional data move */
656 CPPI5_TR_TYPE3,
657 /* type4: Four dimensional data move with data formatting */
658 CPPI5_TR_TYPE4,
659 /* type5: Four dimensional Cache Warm */
660 CPPI5_TR_TYPE5,
661 /* type6-7: Reserved */
662 /* type8: Four Dimensional Block Move */
663 CPPI5_TR_TYPE8 = 8,
664 /* type9: Four Dimensional Block Move with Repacking */
665 CPPI5_TR_TYPE9,
666 /* type10: Two Dimensional Block Move */
667 CPPI5_TR_TYPE10,
668 /* type11: Two Dimensional Block Move with Repacking */
669 CPPI5_TR_TYPE11,
670 /* type12-14: Reserved */
671 /* type15 Four Dimensional Block Move with Repacking and Indirection */
672 CPPI5_TR_TYPE15 = 15,
673 CPPI5_TR_TYPE_MAX
674 };
675
676 /*
677 * Udmap TR Flags EVENT_SIZE field specifies when an event is generated
678 * for each TR.
679 */
680 enum cppi5_tr_event_size {
681 /* When TR is complete and all status for the TR has been received */
682 CPPI5_TR_EVENT_SIZE_COMPLETION,
683 /*
684 * Type 0: when the last data transaction is sent for the TR;
685 * Type 1-11: when ICNT1 is decremented
686 */
687 CPPI5_TR_EVENT_SIZE_ICNT1_DEC,
688 /*
689 * Type 0-1,10-11: when the last data transaction is sent for the TR;
690 * All other types: when ICNT2 is decremented
691 */
692 CPPI5_TR_EVENT_SIZE_ICNT2_DEC,
693 /*
694 * Type 0-2,10-11: when the last data transaction is sent for the TR;
695 * All other types: when ICNT3 is decremented
696 */
697 CPPI5_TR_EVENT_SIZE_ICNT3_DEC,
698 CPPI5_TR_EVENT_SIZE_MAX
699 };
700
701 /*
702 * Udmap TR Flags TRIGGERx field specifies the type of trigger used to
703 * enable the TR to transfer data as specified by TRIGGERx_TYPE field.
704 */
705 enum cppi5_tr_trigger {
706 CPPI5_TR_TRIGGER_NONE, /* No Trigger */
707 CPPI5_TR_TRIGGER_GLOBAL0, /* Global Trigger 0 */
708 CPPI5_TR_TRIGGER_GLOBAL1, /* Global Trigger 1 */
709 CPPI5_TR_TRIGGER_LOCAL_EVENT, /* Local Event */
710 CPPI5_TR_TRIGGER_MAX
711 };
712
713 /*
714 * Udmap TR Flags TRIGGERx_TYPE field specifies the type of data transfer
715 * that will be enabled by receiving a trigger as specified by TRIGGERx.
716 */
717 enum cppi5_tr_trigger_type {
718 /* The second inner most loop (ICNT1) will be decremented by 1 */
719 CPPI5_TR_TRIGGER_TYPE_ICNT1_DEC,
720 /* The third inner most loop (ICNT2) will be decremented by 1 */
721 CPPI5_TR_TRIGGER_TYPE_ICNT2_DEC,
722 /* The outer most loop (ICNT3) will be decremented by 1 */
723 CPPI5_TR_TRIGGER_TYPE_ICNT3_DEC,
724 /* The entire TR will be allowed to complete */
725 CPPI5_TR_TRIGGER_TYPE_ALL,
726 CPPI5_TR_TRIGGER_TYPE_MAX
727 };
728
729 typedef u32 cppi5_tr_flags_t;
730
731 /* Type 0 (One dimensional data move) TR (16 byte) */
732 struct cppi5_tr_type0_t {
733 cppi5_tr_flags_t flags;
734 u16 icnt0;
735 u16 unused;
736 u64 addr;
737 } __aligned(16) __packed;
738
739 /* Type 1 (Two dimensional data move) TR (32 byte) */
740 struct cppi5_tr_type1_t {
741 cppi5_tr_flags_t flags;
742 u16 icnt0;
743 u16 icnt1;
744 u64 addr;
745 s32 dim1;
746 } __aligned(32) __packed;
747
748 /* Type 2 (Three dimensional data move) TR (32 byte) */
749 struct cppi5_tr_type2_t {
750 cppi5_tr_flags_t flags;
751 u16 icnt0;
752 u16 icnt1;
753 u64 addr;
754 s32 dim1;
755 u16 icnt2;
756 u16 unused;
757 s32 dim2;
758 } __aligned(32) __packed;
759
760 /* Type 3 (Four dimensional data move) TR (32 byte) */
761 struct cppi5_tr_type3_t {
762 cppi5_tr_flags_t flags;
763 u16 icnt0;
764 u16 icnt1;
765 u64 addr;
766 s32 dim1;
767 u16 icnt2;
768 u16 icnt3;
769 s32 dim2;
770 s32 dim3;
771 } __aligned(32) __packed;
772
773 /*
774 * Type 15 (Four Dimensional Block Copy with Repacking and
775 * Indirection Support) TR (64 byte).
776 */
777 struct cppi5_tr_type15_t {
778 cppi5_tr_flags_t flags;
779 u16 icnt0;
780 u16 icnt1;
781 u64 addr;
782 s32 dim1;
783 u16 icnt2;
784 u16 icnt3;
785 s32 dim2;
786 s32 dim3;
787 u32 _reserved;
788 s32 ddim1;
789 u64 daddr;
790 s32 ddim2;
791 s32 ddim3;
792 u16 dicnt0;
793 u16 dicnt1;
794 u16 dicnt2;
795 u16 dicnt3;
796 } __aligned(64) __packed;
797
798 struct cppi5_tr_resp_t {
799 u8 status;
800 u8 reserved;
801 u8 cmd_id;
802 u8 flags;
803 } __packed;
804
805 #define CPPI5_TR_RESPONSE_STATUS_TYPE_SHIFT (0U)
806 #define CPPI5_TR_RESPONSE_STATUS_TYPE_MASK GENMASK(3, 0)
807 #define CPPI5_TR_RESPONSE_STATUS_INFO_SHIFT (4U)
808 #define CPPI5_TR_RESPONSE_STATUS_INFO_MASK GENMASK(7, 4)
809 #define CPPI5_TR_RESPONSE_CMDID_SHIFT (16U)
810 #define CPPI5_TR_RESPONSE_CMDID_MASK GENMASK(23, 16)
811 #define CPPI5_TR_RESPONSE_CFG_SPECIFIC_SHIFT (24U)
812 #define CPPI5_TR_RESPONSE_CFG_SPECIFIC_MASK GENMASK(31, 24)
813
814 /*
815 * Udmap TR Response Status Type field is used to determine
816 * what type of status is being returned.
817 */
818 enum cppi5_tr_resp_status_type {
819 CPPI5_TR_RESPONSE_STATUS_COMPLETE, /* None */
820 CPPI5_TR_RESPONSE_STATUS_TRANSFER_ERR, /* Transfer Error */
821 CPPI5_TR_RESPONSE_STATUS_ABORTED_ERR, /* Aborted Error */
822 CPPI5_TR_RESPONSE_STATUS_SUBMISSION_ERR, /* Submission Error */
823 CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_ERR, /* Unsup. Feature */
824 CPPI5_TR_RESPONSE_STATUS_MAX
825 };
826
827 /*
828 * Udmap TR Response Status field values which corresponds
829 * CPPI5_TR_RESPONSE_STATUS_SUBMISSION_ERR
830 */
831 enum cppi5_tr_resp_status_submission {
832 /* ICNT0 was 0 */
833 CPPI5_TR_RESPONSE_STATUS_SUBMISSION_ICNT0,
834 /* Channel FIFO was full when TR received */
835 CPPI5_TR_RESPONSE_STATUS_SUBMISSION_FIFO_FULL,
836 /* Channel is not owned by the submitter */
837 CPPI5_TR_RESPONSE_STATUS_SUBMISSION_OWN,
838 CPPI5_TR_RESPONSE_STATUS_SUBMISSION_MAX
839 };
840
841 /*
842 * Udmap TR Response Status field values which corresponds
843 * CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_ERR
844 */
845 enum cppi5_tr_resp_status_unsupported {
846 /* TR Type not supported */
847 CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_TR_TYPE,
848 /* STATIC not supported */
849 CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_STATIC,
850 /* EOL not supported */
851 CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_EOL,
852 /* CONFIGURATION SPECIFIC not supported */
853 CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_CFG_SPECIFIC,
854 /* AMODE not supported */
855 CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_AMODE,
856 /* ELTYPE not supported */
857 CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_ELTYPE,
858 /* DFMT not supported */
859 CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_DFMT,
860 /* SECTR not supported */
861 CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_SECTR,
862 /* AMODE SPECIFIC field not supported */
863 CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_AMODE_SPECIFIC,
864 CPPI5_TR_RESPONSE_STATUS_UNSUPPORTED_MAX
865 };
866
867 /**
868 * cppi5_trdesc_calc_size - Calculate TR Descriptor size
869 * @tr_count: number of TR records
870 * @tr_size: Nominal size of TR record (max) [16, 32, 64, 128]
871 *
872 * Returns required TR Descriptor size
873 */
cppi5_trdesc_calc_size(u32 tr_count,u32 tr_size)874 static inline size_t cppi5_trdesc_calc_size(u32 tr_count, u32 tr_size)
875 {
876 /*
877 * The Size of a TR descriptor is:
878 * 1 x tr_size : the first 16 bytes is used by the packet info block +
879 * tr_count x tr_size : Transfer Request Records +
880 * tr_count x sizeof(struct cppi5_tr_resp_t) : Transfer Response Records
881 */
882 return tr_size * (tr_count + 1) +
883 sizeof(struct cppi5_tr_resp_t) * tr_count;
884 }
885
886 /**
887 * cppi5_trdesc_init - Init TR Descriptor
888 * @desc: TR Descriptor
889 * @tr_count: number of TR records
890 * @tr_size: Nominal size of TR record (max) [16, 32, 64, 128]
891 * @reload_idx: Absolute index to jump to on the 2nd and following passes
892 * through the TR packet.
893 * @reload_count: Number of times to jump from last entry to reload_idx. 0x1ff
894 * indicates infinite looping.
895 *
896 * Init TR Descriptor
897 */
cppi5_trdesc_init(struct cppi5_desc_hdr_t * desc_hdr,u32 tr_count,u32 tr_size,u32 reload_idx,u32 reload_count)898 static inline void cppi5_trdesc_init(struct cppi5_desc_hdr_t *desc_hdr,
899 u32 tr_count, u32 tr_size, u32 reload_idx,
900 u32 reload_count)
901 {
902 WARN_ON(!desc_hdr);
903 WARN_ON(tr_count & ~CPPI5_INFO0_TRDESC_LASTIDX_MASK);
904 WARN_ON(reload_idx > CPPI5_INFO0_TRDESC_RLDIDX_MAX);
905 WARN_ON(reload_count > CPPI5_INFO0_TRDESC_RLDCNT_MAX);
906
907 desc_hdr->pkt_info0 = CPPI5_INFO0_DESC_TYPE_VAL_TR <<
908 CPPI5_INFO0_HDESC_TYPE_SHIFT;
909 desc_hdr->pkt_info0 |= (reload_count << CPPI5_INFO0_TRDESC_RLDCNT_SHIFT) &
910 CPPI5_INFO0_TRDESC_RLDCNT_MASK;
911 desc_hdr->pkt_info0 |= (reload_idx << CPPI5_INFO0_TRDESC_RLDIDX_SHIFT) &
912 CPPI5_INFO0_TRDESC_RLDIDX_MASK;
913 desc_hdr->pkt_info0 |= (tr_count - 1) & CPPI5_INFO0_TRDESC_LASTIDX_MASK;
914
915 desc_hdr->pkt_info1 |= ((ffs(tr_size >> 4) - 1) <<
916 CPPI5_INFO1_TRDESC_RECSIZE_SHIFT) &
917 CPPI5_INFO1_TRDESC_RECSIZE_MASK;
918 }
919
920 /**
921 * cppi5_tr_init - Init TR record
922 * @flags: Pointer to the TR's flags
923 * @type: TR type
924 * @static_tr: TR is static
925 * @wait: Wait for TR completion before allow the next TR to start
926 * @event_size: output event generation cfg
927 * @cmd_id: TR identifier (application specifics)
928 *
929 * Init TR record
930 */
cppi5_tr_init(cppi5_tr_flags_t * flags,enum cppi5_tr_types type,bool static_tr,bool wait,enum cppi5_tr_event_size event_size,u32 cmd_id)931 static inline void cppi5_tr_init(cppi5_tr_flags_t *flags,
932 enum cppi5_tr_types type, bool static_tr,
933 bool wait, enum cppi5_tr_event_size event_size,
934 u32 cmd_id)
935 {
936 WARN_ON(!flags);
937
938 *flags = type;
939 *flags |= (event_size << CPPI5_TR_EVENT_SIZE_SHIFT) &
940 CPPI5_TR_EVENT_SIZE_MASK;
941
942 *flags |= (cmd_id << CPPI5_TR_CMD_ID_SHIFT) &
943 CPPI5_TR_CMD_ID_MASK;
944
945 if (static_tr && (type == CPPI5_TR_TYPE8 || type == CPPI5_TR_TYPE9))
946 *flags |= CPPI5_TR_STATIC;
947
948 if (wait)
949 *flags |= CPPI5_TR_WAIT;
950 }
951
952 /**
953 * cppi5_tr_set_trigger - Configure trigger0/1 and trigger0/1_type
954 * @flags: Pointer to the TR's flags
955 * @trigger0: trigger0 selection
956 * @trigger0_type: type of data transfer that will be enabled by trigger0
957 * @trigger1: trigger1 selection
958 * @trigger1_type: type of data transfer that will be enabled by trigger1
959 *
960 * Configure the triggers for the TR
961 */
cppi5_tr_set_trigger(cppi5_tr_flags_t * flags,enum cppi5_tr_trigger trigger0,enum cppi5_tr_trigger_type trigger0_type,enum cppi5_tr_trigger trigger1,enum cppi5_tr_trigger_type trigger1_type)962 static inline void cppi5_tr_set_trigger(cppi5_tr_flags_t *flags,
963 enum cppi5_tr_trigger trigger0,
964 enum cppi5_tr_trigger_type trigger0_type,
965 enum cppi5_tr_trigger trigger1,
966 enum cppi5_tr_trigger_type trigger1_type)
967 {
968 WARN_ON(!flags);
969
970 *flags |= (trigger0 << CPPI5_TR_TRIGGER0_SHIFT) &
971 CPPI5_TR_TRIGGER0_MASK;
972 *flags |= (trigger0_type << CPPI5_TR_TRIGGER0_TYPE_SHIFT) &
973 CPPI5_TR_TRIGGER0_TYPE_MASK;
974
975 *flags |= (trigger1 << CPPI5_TR_TRIGGER1_SHIFT) &
976 CPPI5_TR_TRIGGER1_MASK;
977 *flags |= (trigger1_type << CPPI5_TR_TRIGGER1_TYPE_SHIFT) &
978 CPPI5_TR_TRIGGER1_TYPE_MASK;
979 }
980
981 /**
982 * cppi5_tr_cflag_set - Update the Configuration specific flags
983 * @flags: Pointer to the TR's flags
984 * @csf: Configuration specific flags
985 *
986 * Set a bit in Configuration Specific Flags section of the TR flags.
987 */
cppi5_tr_csf_set(cppi5_tr_flags_t * flags,u32 csf)988 static inline void cppi5_tr_csf_set(cppi5_tr_flags_t *flags, u32 csf)
989 {
990 WARN_ON(!flags);
991
992 *flags |= (csf << CPPI5_TR_CSF_FLAGS_SHIFT) &
993 CPPI5_TR_CSF_FLAGS_MASK;
994 }
995
996 #endif /* __TI_CPPI5_H__ */
997