1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014 Gateworks Corporation
4 * Author: Tim Harvey <tharvey@gateworks.com>
5 */
6
7 #include <common.h>
8 #include <hang.h>
9 #include <log.h>
10 #include <linux/delay.h>
11 #include <linux/types.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/mx6-ddr.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/io.h>
16 #include <asm/types.h>
17 #include <wait_bit.h>
18
19 #if defined(CONFIG_MX6_DDRCAL)
reset_read_data_fifos(void)20 static void reset_read_data_fifos(void)
21 {
22 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
23
24 /* Reset data FIFOs twice. */
25 setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
26 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
27
28 setbits_le32(&mmdc0->mpdgctrl0, 1 << 31);
29 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0);
30 }
31
precharge_all(const bool cs0_enable,const bool cs1_enable)32 static void precharge_all(const bool cs0_enable, const bool cs1_enable)
33 {
34 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
35
36 /*
37 * Issue the Precharge-All command to the DDR device for both
38 * chip selects. Note, CON_REQ bit should also remain set. If
39 * only using one chip select, then precharge only the desired
40 * chip select.
41 */
42 if (cs0_enable) { /* CS0 */
43 writel(0x04008050, &mmdc0->mdscr);
44 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
45 }
46
47 if (cs1_enable) { /* CS1 */
48 writel(0x04008058, &mmdc0->mdscr);
49 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
50 }
51 }
52
force_delay_measurement(int bus_size)53 static void force_delay_measurement(int bus_size)
54 {
55 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
56 struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
57
58 writel(0x800, &mmdc0->mpmur0);
59 if (bus_size == 0x2)
60 writel(0x800, &mmdc1->mpmur0);
61 }
62
modify_dg_result(u32 * reg_st0,u32 * reg_st1,u32 * reg_ctrl)63 static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, u32 *reg_ctrl)
64 {
65 u32 dg_tmp_val, dg_dl_abs_offset, dg_hc_del, val_ctrl;
66
67 /*
68 * DQS gating absolute offset should be modified from reflecting
69 * (HW_DG_LOWx + HW_DG_UPx)/2 to reflecting (HW_DG_UPx - 0x80)
70 */
71
72 val_ctrl = readl(reg_ctrl);
73 val_ctrl &= 0xf0000000;
74
75 dg_tmp_val = ((readl(reg_st0) & 0x07ff0000) >> 16) - 0xc0;
76 dg_dl_abs_offset = dg_tmp_val & 0x7f;
77 dg_hc_del = (dg_tmp_val & 0x780) << 1;
78
79 val_ctrl |= dg_dl_abs_offset + dg_hc_del;
80
81 dg_tmp_val = ((readl(reg_st1) & 0x07ff0000) >> 16) - 0xc0;
82 dg_dl_abs_offset = dg_tmp_val & 0x7f;
83 dg_hc_del = (dg_tmp_val & 0x780) << 1;
84
85 val_ctrl |= (dg_dl_abs_offset + dg_hc_del) << 16;
86
87 writel(val_ctrl, reg_ctrl);
88 }
89
correct_mpwldectr_result(void * reg)90 static void correct_mpwldectr_result(void *reg)
91 {
92 /* Limit is 200/256 of CK, which is WL_HC_DELx | 0x48. */
93 const unsigned int limit = 0x148;
94 u32 val = readl(reg);
95 u32 old = val;
96
97 if ((val & 0x17f) > limit)
98 val &= 0xffff << 16;
99
100 if (((val >> 16) & 0x17f) > limit)
101 val &= 0xffff;
102
103 if (old != val)
104 writel(val, reg);
105 }
106
mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const * sysinfo)107 int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
108 {
109 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
110 struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
111 u32 esdmisc_val, zq_val;
112 u32 errors = 0;
113 u32 ldectrl[4] = {0};
114 u32 ddr_mr1 = 0x4;
115 u32 rwalat_max;
116
117 /*
118 * Stash old values in case calibration fails,
119 * we need to restore them
120 */
121 ldectrl[0] = readl(&mmdc0->mpwldectrl0);
122 ldectrl[1] = readl(&mmdc0->mpwldectrl1);
123 if (sysinfo->dsize == 2) {
124 ldectrl[2] = readl(&mmdc1->mpwldectrl0);
125 ldectrl[3] = readl(&mmdc1->mpwldectrl1);
126 }
127
128 /* disable DDR logic power down timer */
129 clrbits_le32(&mmdc0->mdpdc, 0xff00);
130
131 /* disable Adopt power down timer */
132 setbits_le32(&mmdc0->mapsr, 0x1);
133
134 debug("Starting write leveling calibration.\n");
135
136 /*
137 * 2. disable auto refresh and ZQ calibration
138 * before proceeding with Write Leveling calibration
139 */
140 esdmisc_val = readl(&mmdc0->mdref);
141 writel(0x0000C000, &mmdc0->mdref);
142 zq_val = readl(&mmdc0->mpzqhwctrl);
143 writel(zq_val & ~0x3, &mmdc0->mpzqhwctrl);
144
145 /* 3. increase walat and ralat to maximum */
146 rwalat_max = (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17);
147 setbits_le32(&mmdc0->mdmisc, rwalat_max);
148 if (sysinfo->dsize == 2)
149 setbits_le32(&mmdc1->mdmisc, rwalat_max);
150 /*
151 * 4 & 5. Configure the external DDR device to enter write-leveling
152 * mode through Load Mode Register command.
153 * Register setting:
154 * Bits[31:16] MR1 value (0x0080 write leveling enable)
155 * Bit[9] set WL_EN to enable MMDC DQS output
156 * Bits[6:4] set CMD bits for Load Mode Register programming
157 * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming
158 */
159 writel(0x00808231, &mmdc0->mdscr);
160
161 /* 6. Activate automatic calibration by setting MPWLGCR[HW_WL_EN] */
162 writel(0x00000001, &mmdc0->mpwlgcr);
163
164 /*
165 * 7. Upon completion of this process the MMDC de-asserts
166 * the MPWLGCR[HW_WL_EN]
167 */
168 wait_for_bit_le32(&mmdc0->mpwlgcr, 1 << 0, 0, 100, 0);
169
170 /*
171 * 8. check for any errors: check both PHYs for x64 configuration,
172 * if x32, check only PHY0
173 */
174 if (readl(&mmdc0->mpwlgcr) & 0x00000F00)
175 errors |= 1;
176 if (sysinfo->dsize == 2)
177 if (readl(&mmdc1->mpwlgcr) & 0x00000F00)
178 errors |= 2;
179
180 debug("Ending write leveling calibration. Error mask: 0x%x\n", errors);
181
182 /* check to see if cal failed */
183 if ((readl(&mmdc0->mpwldectrl0) == 0x001F001F) &&
184 (readl(&mmdc0->mpwldectrl1) == 0x001F001F) &&
185 ((sysinfo->dsize < 2) ||
186 ((readl(&mmdc1->mpwldectrl0) == 0x001F001F) &&
187 (readl(&mmdc1->mpwldectrl1) == 0x001F001F)))) {
188 debug("Cal seems to have soft-failed due to memory not supporting write leveling on all channels. Restoring original write leveling values.\n");
189 writel(ldectrl[0], &mmdc0->mpwldectrl0);
190 writel(ldectrl[1], &mmdc0->mpwldectrl1);
191 if (sysinfo->dsize == 2) {
192 writel(ldectrl[2], &mmdc1->mpwldectrl0);
193 writel(ldectrl[3], &mmdc1->mpwldectrl1);
194 }
195 errors |= 4;
196 }
197
198 correct_mpwldectr_result(&mmdc0->mpwldectrl0);
199 correct_mpwldectr_result(&mmdc0->mpwldectrl1);
200 if (sysinfo->dsize == 2) {
201 correct_mpwldectr_result(&mmdc1->mpwldectrl0);
202 correct_mpwldectr_result(&mmdc1->mpwldectrl1);
203 }
204
205 /*
206 * User should issue MRS command to exit write leveling mode
207 * through Load Mode Register command
208 * Register setting:
209 * Bits[31:16] MR1 value "ddr_mr1" value from initialization
210 * Bit[9] clear WL_EN to disable MMDC DQS output
211 * Bits[6:4] set CMD bits for Load Mode Register programming
212 * Bits[2:0] set CMD_BA to 0x1 for DDR MR1 programming
213 */
214 writel((ddr_mr1 << 16) + 0x8031, &mmdc0->mdscr);
215
216 /* re-enable auto refresh and zq cal */
217 writel(esdmisc_val, &mmdc0->mdref);
218 writel(zq_val, &mmdc0->mpzqhwctrl);
219
220 debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08x\n",
221 readl(&mmdc0->mpwldectrl0));
222 debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08x\n",
223 readl(&mmdc0->mpwldectrl1));
224 if (sysinfo->dsize == 2) {
225 debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08x\n",
226 readl(&mmdc1->mpwldectrl0));
227 debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08x\n",
228 readl(&mmdc1->mpwldectrl1));
229 }
230
231 /* We must force a readback of these values, to get them to stick */
232 readl(&mmdc0->mpwldectrl0);
233 readl(&mmdc0->mpwldectrl1);
234 if (sysinfo->dsize == 2) {
235 readl(&mmdc1->mpwldectrl0);
236 readl(&mmdc1->mpwldectrl1);
237 }
238
239 /* enable DDR logic power down timer: */
240 setbits_le32(&mmdc0->mdpdc, 0x00005500);
241
242 /* Enable Adopt power down timer: */
243 clrbits_le32(&mmdc0->mapsr, 0x1);
244
245 /* Clear CON_REQ */
246 writel(0, &mmdc0->mdscr);
247
248 return errors;
249 }
250
mmdc_set_sdqs(bool set)251 static void mmdc_set_sdqs(bool set)
252 {
253 struct mx6sdl_iomux_ddr_regs *mx6sdl_ddr_iomux =
254 (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
255 struct mx6dq_iomux_ddr_regs *mx6dq_ddr_iomux =
256 (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
257 struct mx6sx_iomux_ddr_regs *mx6sx_ddr_iomux =
258 (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
259 struct mx6sl_iomux_ddr_regs *mx6sl_ddr_iomux =
260 (struct mx6sl_iomux_ddr_regs *)MX6SL_IOM_DDR_BASE;
261 struct mx6ul_iomux_ddr_regs *mx6ul_ddr_iomux =
262 (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
263 int i, sdqs_cnt;
264 u32 sdqs;
265
266 if (is_mx6sx()) {
267 sdqs = (u32)(&mx6sx_ddr_iomux->dram_sdqs0);
268 sdqs_cnt = 2;
269 } else if (is_mx6sl()) {
270 sdqs = (u32)(&mx6sl_ddr_iomux->dram_sdqs0);
271 sdqs_cnt = 2;
272 } else if (is_mx6ul() || is_mx6ull()) {
273 sdqs = (u32)(&mx6ul_ddr_iomux->dram_sdqs0);
274 sdqs_cnt = 2;
275 } else if (is_mx6sdl()) {
276 sdqs = (u32)(&mx6sdl_ddr_iomux->dram_sdqs0);
277 sdqs_cnt = 8;
278 } else { /* MX6DQ */
279 sdqs = (u32)(&mx6dq_ddr_iomux->dram_sdqs0);
280 sdqs_cnt = 8;
281 }
282
283 for (i = 0; i < sdqs_cnt; i++) {
284 if (set)
285 setbits_le32(sdqs + (4 * i), 0x7000);
286 else
287 clrbits_le32(sdqs + (4 * i), 0x7000);
288 }
289 }
290
mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const * sysinfo)291 int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
292 {
293 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
294 struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
295 bool cs0_enable;
296 bool cs1_enable;
297 bool cs0_enable_initial;
298 bool cs1_enable_initial;
299 u32 esdmisc_val;
300 u32 temp_ref;
301 u32 pddword = 0x00ffff00; /* best so far, place into MPPDCMPR1 */
302 u32 errors = 0;
303 u32 initdelay = 0x40404040;
304
305 /* check to see which chip selects are enabled */
306 cs0_enable_initial = readl(&mmdc0->mdctl) & 0x80000000;
307 cs1_enable_initial = readl(&mmdc0->mdctl) & 0x40000000;
308
309 /* disable DDR logic power down timer: */
310 clrbits_le32(&mmdc0->mdpdc, 0xff00);
311
312 /* disable Adopt power down timer: */
313 setbits_le32(&mmdc0->mapsr, 0x1);
314
315 /* set DQS pull ups */
316 mmdc_set_sdqs(true);
317
318 /* Save old RALAT and WALAT values */
319 esdmisc_val = readl(&mmdc0->mdmisc);
320
321 setbits_le32(&mmdc0->mdmisc,
322 (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
323
324 /* Disable auto refresh before proceeding with calibration */
325 temp_ref = readl(&mmdc0->mdref);
326 writel(0x0000c000, &mmdc0->mdref);
327
328 /*
329 * Per the ref manual, issue one refresh cycle MDSCR[CMD]= 0x2,
330 * this also sets the CON_REQ bit.
331 */
332 if (cs0_enable_initial)
333 writel(0x00008020, &mmdc0->mdscr);
334 if (cs1_enable_initial)
335 writel(0x00008028, &mmdc0->mdscr);
336
337 /* poll to make sure the con_ack bit was asserted */
338 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 1, 100, 0);
339
340 /*
341 * Check MDMISC register CALIB_PER_CS to see which CS calibration
342 * is targeted to (under normal cases, it should be cleared
343 * as this is the default value, indicating calibration is directed
344 * to CS0).
345 * Disable the other chip select not being target for calibration
346 * to avoid any potential issues. This will get re-enabled at end
347 * of calibration.
348 */
349 if ((readl(&mmdc0->mdmisc) & 0x00100000) == 0)
350 clrbits_le32(&mmdc0->mdctl, 1 << 30); /* clear SDE_1 */
351 else
352 clrbits_le32(&mmdc0->mdctl, 1 << 31); /* clear SDE_0 */
353
354 /*
355 * Check to see which chip selects are now enabled for
356 * the remainder of the calibration.
357 */
358 cs0_enable = readl(&mmdc0->mdctl) & 0x80000000;
359 cs1_enable = readl(&mmdc0->mdctl) & 0x40000000;
360
361 precharge_all(cs0_enable, cs1_enable);
362
363 /* Write the pre-defined value into MPPDCMPR1 */
364 writel(pddword, &mmdc0->mppdcmpr1);
365
366 /*
367 * Issue a write access to the external DDR device by setting
368 * the bit SW_DUMMY_WR (bit 0) in the MPSWDAR0 and then poll
369 * this bit until it clears to indicate completion of the write access.
370 */
371 setbits_le32(&mmdc0->mpswdar0, 1);
372 wait_for_bit_le32(&mmdc0->mpswdar0, 1 << 0, 0, 100, 0);
373
374 /* Set the RD_DL_ABS# bits to their default values
375 * (will be calibrated later in the read delay-line calibration).
376 * Both PHYs for x64 configuration, if x32, do only PHY0.
377 */
378 writel(initdelay, &mmdc0->mprddlctl);
379 if (sysinfo->dsize == 0x2)
380 writel(initdelay, &mmdc1->mprddlctl);
381
382 /* Force a measurment, for previous delay setup to take effect. */
383 force_delay_measurement(sysinfo->dsize);
384
385 /*
386 * ***************************
387 * Read DQS Gating calibration
388 * ***************************
389 */
390 debug("Starting Read DQS Gating calibration.\n");
391
392 /*
393 * Reset the read data FIFOs (two resets); only need to issue reset
394 * to PHY0 since in x64 mode, the reset will also go to PHY1.
395 */
396 reset_read_data_fifos();
397
398 /*
399 * Start the automatic read DQS gating calibration process by
400 * asserting MPDGCTRL0[HW_DG_EN] and MPDGCTRL0[DG_CMP_CYC]
401 * and then poll MPDGCTRL0[HW_DG_EN]] until this bit clears
402 * to indicate completion.
403 * Also, ensure that MPDGCTRL0[HW_DG_ERR] is clear to indicate
404 * no errors were seen during calibration.
405 */
406
407 /*
408 * Set bit 30: chooses option to wait 32 cycles instead of
409 * 16 before comparing read data.
410 */
411 setbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
412 if (sysinfo->dsize == 2)
413 setbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
414
415 /* Set bit 28 to start automatic read DQS gating calibration */
416 setbits_le32(&mmdc0->mpdgctrl0, 5 << 28);
417
418 /* Poll for completion. MPDGCTRL0[HW_DG_EN] should be 0 */
419 wait_for_bit_le32(&mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0);
420
421 /*
422 * Check to see if any errors were encountered during calibration
423 * (check MPDGCTRL0[HW_DG_ERR]).
424 * Check both PHYs for x64 configuration, if x32, check only PHY0.
425 */
426 if (readl(&mmdc0->mpdgctrl0) & 0x00001000)
427 errors |= 1;
428
429 if ((sysinfo->dsize == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000))
430 errors |= 2;
431
432 /* now disable mpdgctrl0[DG_CMP_CYC] */
433 clrbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
434 if (sysinfo->dsize == 2)
435 clrbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
436
437 /*
438 * DQS gating absolute offset should be modified from
439 * reflecting (HW_DG_LOWx + HW_DG_UPx)/2 to
440 * reflecting (HW_DG_UPx - 0x80)
441 */
442 modify_dg_result(&mmdc0->mpdghwst0, &mmdc0->mpdghwst1,
443 &mmdc0->mpdgctrl0);
444 modify_dg_result(&mmdc0->mpdghwst2, &mmdc0->mpdghwst3,
445 &mmdc0->mpdgctrl1);
446 if (sysinfo->dsize == 0x2) {
447 modify_dg_result(&mmdc1->mpdghwst0, &mmdc1->mpdghwst1,
448 &mmdc1->mpdgctrl0);
449 modify_dg_result(&mmdc1->mpdghwst2, &mmdc1->mpdghwst3,
450 &mmdc1->mpdgctrl1);
451 }
452 debug("Ending Read DQS Gating calibration. Error mask: 0x%x\n", errors);
453
454 /*
455 * **********************
456 * Read Delay calibration
457 * **********************
458 */
459 debug("Starting Read Delay calibration.\n");
460
461 reset_read_data_fifos();
462
463 /*
464 * 4. Issue the Precharge-All command to the DDR device for both
465 * chip selects. If only using one chip select, then precharge
466 * only the desired chip select.
467 */
468 precharge_all(cs0_enable, cs1_enable);
469
470 /*
471 * 9. Read delay-line calibration
472 * Start the automatic read calibration process by asserting
473 * MPRDDLHWCTL[HW_RD_DL_EN].
474 */
475 writel(0x00000030, &mmdc0->mprddlhwctl);
476
477 /*
478 * 10. poll for completion
479 * MMDC indicates that the write data calibration had finished by
480 * setting MPRDDLHWCTL[HW_RD_DL_EN] = 0. Also, ensure that
481 * no error bits were set.
482 */
483 wait_for_bit_le32(&mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0);
484
485 /* check both PHYs for x64 configuration, if x32, check only PHY0 */
486 if (readl(&mmdc0->mprddlhwctl) & 0x0000000f)
487 errors |= 4;
488
489 if ((sysinfo->dsize == 0x2) &&
490 (readl(&mmdc1->mprddlhwctl) & 0x0000000f))
491 errors |= 8;
492
493 debug("Ending Read Delay calibration. Error mask: 0x%x\n", errors);
494
495 /*
496 * ***********************
497 * Write Delay Calibration
498 * ***********************
499 */
500 debug("Starting Write Delay calibration.\n");
501
502 reset_read_data_fifos();
503
504 /*
505 * 4. Issue the Precharge-All command to the DDR device for both
506 * chip selects. If only using one chip select, then precharge
507 * only the desired chip select.
508 */
509 precharge_all(cs0_enable, cs1_enable);
510
511 /*
512 * 8. Set the WR_DL_ABS# bits to their default values.
513 * Both PHYs for x64 configuration, if x32, do only PHY0.
514 */
515 writel(initdelay, &mmdc0->mpwrdlctl);
516 if (sysinfo->dsize == 0x2)
517 writel(initdelay, &mmdc1->mpwrdlctl);
518
519 /*
520 * XXX This isn't in the manual. Force a measurement,
521 * for previous delay setup to effect.
522 */
523 force_delay_measurement(sysinfo->dsize);
524
525 /*
526 * 9. 10. Start the automatic write calibration process
527 * by asserting MPWRDLHWCTL0[HW_WR_DL_EN].
528 */
529 writel(0x00000030, &mmdc0->mpwrdlhwctl);
530
531 /*
532 * Poll for completion.
533 * MMDC indicates that the write data calibration had finished
534 * by setting MPWRDLHWCTL[HW_WR_DL_EN] = 0.
535 * Also, ensure that no error bits were set.
536 */
537 wait_for_bit_le32(&mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0);
538
539 /* Check both PHYs for x64 configuration, if x32, check only PHY0 */
540 if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f)
541 errors |= 16;
542
543 if ((sysinfo->dsize == 0x2) &&
544 (readl(&mmdc1->mpwrdlhwctl) & 0x0000000f))
545 errors |= 32;
546
547 debug("Ending Write Delay calibration. Error mask: 0x%x\n", errors);
548
549 reset_read_data_fifos();
550
551 /* Enable DDR logic power down timer */
552 setbits_le32(&mmdc0->mdpdc, 0x00005500);
553
554 /* Enable Adopt power down timer */
555 clrbits_le32(&mmdc0->mapsr, 0x1);
556
557 /* Restore MDMISC value (RALAT, WALAT) to MMDCP1 */
558 writel(esdmisc_val, &mmdc0->mdmisc);
559
560 /* Clear DQS pull ups */
561 mmdc_set_sdqs(false);
562
563 /* Re-enable SDE (chip selects) if they were set initially */
564 if (cs1_enable_initial)
565 /* Set SDE_1 */
566 setbits_le32(&mmdc0->mdctl, 1 << 30);
567
568 if (cs0_enable_initial)
569 /* Set SDE_0 */
570 setbits_le32(&mmdc0->mdctl, 1 << 31);
571
572 /* Re-enable to auto refresh */
573 writel(temp_ref, &mmdc0->mdref);
574
575 /* Clear the MDSCR (including the con_req bit) */
576 writel(0x0, &mmdc0->mdscr); /* CS0 */
577
578 /* Poll to make sure the con_ack bit is clear */
579 wait_for_bit_le32(&mmdc0->mdscr, 1 << 14, 0, 100, 0);
580
581 /*
582 * Print out the registers that were updated as a result
583 * of the calibration process.
584 */
585 debug("MMDC registers updated from calibration\n");
586 debug("Read DQS gating calibration:\n");
587 debug("\tMPDGCTRL0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdgctrl0));
588 debug("\tMPDGCTRL1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdgctrl1));
589 if (sysinfo->dsize == 2) {
590 debug("\tMPDGCTRL0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdgctrl0));
591 debug("\tMPDGCTRL1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdgctrl1));
592 }
593 debug("Read calibration:\n");
594 debug("\tMPRDDLCTL PHY0 = 0x%08x\n", readl(&mmdc0->mprddlctl));
595 if (sysinfo->dsize == 2)
596 debug("\tMPRDDLCTL PHY1 = 0x%08x\n", readl(&mmdc1->mprddlctl));
597 debug("Write calibration:\n");
598 debug("\tMPWRDLCTL PHY0 = 0x%08x\n", readl(&mmdc0->mpwrdlctl));
599 if (sysinfo->dsize == 2)
600 debug("\tMPWRDLCTL PHY1 = 0x%08x\n", readl(&mmdc1->mpwrdlctl));
601
602 /*
603 * Registers below are for debugging purposes. These print out
604 * the upper and lower boundaries captured during
605 * read DQS gating calibration.
606 */
607 debug("Status registers bounds for read DQS gating:\n");
608 debug("\tMPDGHWST0 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst0));
609 debug("\tMPDGHWST1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst1));
610 debug("\tMPDGHWST2 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst2));
611 debug("\tMPDGHWST3 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst3));
612 if (sysinfo->dsize == 2) {
613 debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0));
614 debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1));
615 debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2));
616 debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3));
617 }
618
619 debug("Final do_dqs_calibration error mask: 0x%x\n", errors);
620
621 return errors;
622 }
623 #endif
624
625 #if defined(CONFIG_MX6SX)
626 /* Configure MX6SX mmdc iomux */
mx6sx_dram_iocfg(unsigned width,const struct mx6sx_iomux_ddr_regs * ddr,const struct mx6sx_iomux_grp_regs * grp)627 void mx6sx_dram_iocfg(unsigned width,
628 const struct mx6sx_iomux_ddr_regs *ddr,
629 const struct mx6sx_iomux_grp_regs *grp)
630 {
631 struct mx6sx_iomux_ddr_regs *mx6_ddr_iomux;
632 struct mx6sx_iomux_grp_regs *mx6_grp_iomux;
633
634 mx6_ddr_iomux = (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
635 mx6_grp_iomux = (struct mx6sx_iomux_grp_regs *)MX6SX_IOM_GRP_BASE;
636
637 /* DDR IO TYPE */
638 writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
639 writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
640
641 /* CLOCK */
642 writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
643
644 /* ADDRESS */
645 writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
646 writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
647 writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
648
649 /* Control */
650 writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
651 writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
652 writel(ddr->dram_sdcke0, &mx6_ddr_iomux->dram_sdcke0);
653 writel(ddr->dram_sdcke1, &mx6_ddr_iomux->dram_sdcke1);
654 writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
655 writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
656 writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
657
658 /* Data Strobes */
659 writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
660 writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
661 writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
662 if (width >= 32) {
663 writel(ddr->dram_sdqs2, &mx6_ddr_iomux->dram_sdqs2);
664 writel(ddr->dram_sdqs3, &mx6_ddr_iomux->dram_sdqs3);
665 }
666
667 /* Data */
668 writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
669 writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
670 writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
671 if (width >= 32) {
672 writel(grp->grp_b2ds, &mx6_grp_iomux->grp_b2ds);
673 writel(grp->grp_b3ds, &mx6_grp_iomux->grp_b3ds);
674 }
675 writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
676 writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
677 if (width >= 32) {
678 writel(ddr->dram_dqm2, &mx6_ddr_iomux->dram_dqm2);
679 writel(ddr->dram_dqm3, &mx6_ddr_iomux->dram_dqm3);
680 }
681 }
682 #endif
683
684 #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
mx6ul_dram_iocfg(unsigned width,const struct mx6ul_iomux_ddr_regs * ddr,const struct mx6ul_iomux_grp_regs * grp)685 void mx6ul_dram_iocfg(unsigned width,
686 const struct mx6ul_iomux_ddr_regs *ddr,
687 const struct mx6ul_iomux_grp_regs *grp)
688 {
689 struct mx6ul_iomux_ddr_regs *mx6_ddr_iomux;
690 struct mx6ul_iomux_grp_regs *mx6_grp_iomux;
691
692 mx6_ddr_iomux = (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
693 mx6_grp_iomux = (struct mx6ul_iomux_grp_regs *)MX6UL_IOM_GRP_BASE;
694
695 /* DDR IO TYPE */
696 writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
697 writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
698
699 /* CLOCK */
700 writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
701
702 /* ADDRESS */
703 writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
704 writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
705 writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
706
707 /* Control */
708 writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
709 writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
710 writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
711 writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
712 writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
713
714 /* Data Strobes */
715 writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
716 writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
717 writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
718
719 /* Data */
720 writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
721 writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
722 writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
723 writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
724 writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
725 }
726 #endif
727
728 #if defined(CONFIG_MX6SL)
mx6sl_dram_iocfg(unsigned width,const struct mx6sl_iomux_ddr_regs * ddr,const struct mx6sl_iomux_grp_regs * grp)729 void mx6sl_dram_iocfg(unsigned width,
730 const struct mx6sl_iomux_ddr_regs *ddr,
731 const struct mx6sl_iomux_grp_regs *grp)
732 {
733 struct mx6sl_iomux_ddr_regs *mx6_ddr_iomux;
734 struct mx6sl_iomux_grp_regs *mx6_grp_iomux;
735
736 mx6_ddr_iomux = (struct mx6sl_iomux_ddr_regs *)MX6SL_IOM_DDR_BASE;
737 mx6_grp_iomux = (struct mx6sl_iomux_grp_regs *)MX6SL_IOM_GRP_BASE;
738
739 /* DDR IO TYPE */
740 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
741 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
742
743 /* CLOCK */
744 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
745
746 /* ADDRESS */
747 mx6_ddr_iomux->dram_cas = ddr->dram_cas;
748 mx6_ddr_iomux->dram_ras = ddr->dram_ras;
749 mx6_grp_iomux->grp_addds = grp->grp_addds;
750
751 /* Control */
752 mx6_ddr_iomux->dram_reset = ddr->dram_reset;
753 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
754 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
755
756 /* Data Strobes */
757 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
758 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
759 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
760 if (width >= 32) {
761 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
762 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
763 }
764
765 /* Data */
766 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
767 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
768 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
769 if (width >= 32) {
770 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
771 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
772 }
773
774 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
775 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
776 if (width >= 32) {
777 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
778 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
779 }
780 }
781 #endif
782
783 #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
784 /* Configure MX6DQ mmdc iomux */
mx6dq_dram_iocfg(unsigned width,const struct mx6dq_iomux_ddr_regs * ddr,const struct mx6dq_iomux_grp_regs * grp)785 void mx6dq_dram_iocfg(unsigned width,
786 const struct mx6dq_iomux_ddr_regs *ddr,
787 const struct mx6dq_iomux_grp_regs *grp)
788 {
789 volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux;
790 volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux;
791
792 mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
793 mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE;
794
795 /* DDR IO Type */
796 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
797 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
798
799 /* Clock */
800 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
801 mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
802
803 /* Address */
804 mx6_ddr_iomux->dram_cas = ddr->dram_cas;
805 mx6_ddr_iomux->dram_ras = ddr->dram_ras;
806 mx6_grp_iomux->grp_addds = grp->grp_addds;
807
808 /* Control */
809 mx6_ddr_iomux->dram_reset = ddr->dram_reset;
810 mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
811 mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
812 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
813 mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
814 mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
815 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
816
817 /* Data Strobes */
818 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
819 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
820 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
821 if (width >= 32) {
822 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
823 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
824 }
825 if (width >= 64) {
826 mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
827 mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
828 mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
829 mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
830 }
831
832 /* Data */
833 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
834 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
835 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
836 if (width >= 32) {
837 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
838 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
839 }
840 if (width >= 64) {
841 mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
842 mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
843 mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
844 mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
845 }
846 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
847 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
848 if (width >= 32) {
849 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
850 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
851 }
852 if (width >= 64) {
853 mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
854 mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
855 mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
856 mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
857 }
858 }
859 #endif
860
861 #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
862 /* Configure MX6SDL mmdc iomux */
mx6sdl_dram_iocfg(unsigned width,const struct mx6sdl_iomux_ddr_regs * ddr,const struct mx6sdl_iomux_grp_regs * grp)863 void mx6sdl_dram_iocfg(unsigned width,
864 const struct mx6sdl_iomux_ddr_regs *ddr,
865 const struct mx6sdl_iomux_grp_regs *grp)
866 {
867 volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux;
868 volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux;
869
870 mx6_ddr_iomux = (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
871 mx6_grp_iomux = (struct mx6sdl_iomux_grp_regs *)MX6SDL_IOM_GRP_BASE;
872
873 /* DDR IO Type */
874 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
875 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
876
877 /* Clock */
878 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
879 mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
880
881 /* Address */
882 mx6_ddr_iomux->dram_cas = ddr->dram_cas;
883 mx6_ddr_iomux->dram_ras = ddr->dram_ras;
884 mx6_grp_iomux->grp_addds = grp->grp_addds;
885
886 /* Control */
887 mx6_ddr_iomux->dram_reset = ddr->dram_reset;
888 mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
889 mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
890 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
891 mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
892 mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
893 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
894
895 /* Data Strobes */
896 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
897 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
898 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
899 if (width >= 32) {
900 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
901 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
902 }
903 if (width >= 64) {
904 mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
905 mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
906 mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
907 mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
908 }
909
910 /* Data */
911 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
912 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
913 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
914 if (width >= 32) {
915 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
916 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
917 }
918 if (width >= 64) {
919 mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
920 mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
921 mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
922 mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
923 }
924 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
925 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
926 if (width >= 32) {
927 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
928 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
929 }
930 if (width >= 64) {
931 mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
932 mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
933 mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
934 mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
935 }
936 }
937 #endif
938
939 /*
940 * Configure mx6 mmdc registers based on:
941 * - board-specific memory configuration
942 * - board-specific calibration data
943 * - ddr3/lpddr2 chip details
944 *
945 * The various calculations here are derived from the Freescale
946 * 1. i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate
947 * MMDC configuration registers based on memory system and memory chip
948 * parameters.
949 *
950 * 2. i.Mx6SL LPDDR2 Script Aid spreadsheet V0.04 designed to generate MMDC
951 * configuration registers based on memory system and memory chip
952 * parameters.
953 *
954 * The defaults here are those which were specified in the spreadsheet.
955 * For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM
956 * and/or IMX6SLRM section titled MMDC initialization.
957 */
958 #define MR(val, ba, cmd, cs1) \
959 ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
960 #define MMDC1(entry, value) do { \
961 if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl()) \
962 mmdc1->entry = value; \
963 } while (0)
964
965 /* see BOOT_CFG3 description Table 5-4. EIM Boot Fusemap */
966 #define BOOT_CFG3_DDR_MASK 0x30
967 #define BOOT_CFG3_EXT_DDR_MASK 0x33
968
969 #define DDR_MMAP_NOC_SINGLE 0
970 #define DDR_MMAP_NOC_DUAL 0x31
971
972 /* NoC ACTIVATE shifts */
973 #define NOC_RD_SHIFT 0
974 #define NOC_FAW_PERIOD_SHIFT 4
975 #define NOC_FAW_BANKS_SHIFT 10
976
977 /* NoC DdrTiming shifts */
978 #define NOC_ACT_TO_ACT_SHIFT 0
979 #define NOC_RD_TO_MISS_SHIFT 6
980 #define NOC_WR_TO_MISS_SHIFT 12
981 #define NOC_BURST_LEN_SHIFT 18
982 #define NOC_RD_TO_WR_SHIFT 21
983 #define NOC_WR_TO_RD_SHIFT 26
984 #define NOC_BW_RATIO_SHIFT 31
985
986 /*
987 * According JESD209-2B-LPDDR2: Table 103
988 * WL: write latency
989 */
lpddr2_wl(uint32_t mem_speed)990 static int lpddr2_wl(uint32_t mem_speed)
991 {
992 switch (mem_speed) {
993 case 1066:
994 case 933:
995 return 4;
996 case 800:
997 return 3;
998 case 677:
999 case 533:
1000 return 2;
1001 case 400:
1002 case 333:
1003 return 1;
1004 default:
1005 puts("invalid memory speed\n");
1006 hang();
1007 }
1008
1009 return 0;
1010 }
1011
1012 /*
1013 * According JESD209-2B-LPDDR2: Table 103
1014 * RL: read latency
1015 */
lpddr2_rl(uint32_t mem_speed)1016 static int lpddr2_rl(uint32_t mem_speed)
1017 {
1018 switch (mem_speed) {
1019 case 1066:
1020 return 8;
1021 case 933:
1022 return 7;
1023 case 800:
1024 return 6;
1025 case 677:
1026 return 5;
1027 case 533:
1028 return 4;
1029 case 400:
1030 case 333:
1031 return 3;
1032 default:
1033 puts("invalid memory speed\n");
1034 hang();
1035 }
1036
1037 return 0;
1038 }
1039
mx6_lpddr2_cfg(const struct mx6_ddr_sysinfo * sysinfo,const struct mx6_mmdc_calibration * calib,const struct mx6_lpddr2_cfg * lpddr2_cfg)1040 void mx6_lpddr2_cfg(const struct mx6_ddr_sysinfo *sysinfo,
1041 const struct mx6_mmdc_calibration *calib,
1042 const struct mx6_lpddr2_cfg *lpddr2_cfg)
1043 {
1044 volatile struct mmdc_p_regs *mmdc0;
1045 u32 val;
1046 u8 tcke, tcksrx, tcksre, trrd;
1047 u8 twl, txp, tfaw, tcl;
1048 u16 tras, twr, tmrd, trtp, twtr, trfc, txsr;
1049 u16 trcd_lp, trppb_lp, trpab_lp, trc_lp;
1050 u16 cs0_end;
1051 u8 coladdr;
1052 int clkper; /* clock period in picoseconds */
1053 int clock; /* clock freq in mHz */
1054 int cs;
1055
1056 /* only support 16/32 bits */
1057 if (sysinfo->dsize > 1)
1058 hang();
1059
1060 mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
1061
1062 clock = mxc_get_clock(MXC_DDR_CLK) / 1000000U;
1063 clkper = (1000 * 1000) / clock; /* pico seconds */
1064
1065 twl = lpddr2_wl(lpddr2_cfg->mem_speed) - 1;
1066
1067 /* LPDDR2-S2 and LPDDR2-S4 have the same tRFC value. */
1068 switch (lpddr2_cfg->density) {
1069 case 1:
1070 case 2:
1071 case 4:
1072 trfc = DIV_ROUND_UP(130000, clkper) - 1;
1073 txsr = DIV_ROUND_UP(140000, clkper) - 1;
1074 break;
1075 case 8:
1076 trfc = DIV_ROUND_UP(210000, clkper) - 1;
1077 txsr = DIV_ROUND_UP(220000, clkper) - 1;
1078 break;
1079 default:
1080 /*
1081 * 64Mb, 128Mb, 256Mb, 512Mb are not supported currently.
1082 */
1083 hang();
1084 break;
1085 }
1086 /*
1087 * txpdll, txpr, taonpd and taofpd are not relevant in LPDDR2 mode,
1088 * set them to 0. */
1089 txp = DIV_ROUND_UP(7500, clkper) - 1;
1090 tcke = 3;
1091 if (lpddr2_cfg->mem_speed == 333)
1092 tfaw = DIV_ROUND_UP(60000, clkper) - 1;
1093 else
1094 tfaw = DIV_ROUND_UP(50000, clkper) - 1;
1095 trrd = DIV_ROUND_UP(10000, clkper) - 1;
1096
1097 /* tckesr for LPDDR2 */
1098 tcksre = DIV_ROUND_UP(15000, clkper);
1099 tcksrx = tcksre;
1100 twr = DIV_ROUND_UP(15000, clkper) - 1;
1101 /*
1102 * tMRR: 2, tMRW: 5
1103 * tMRD should be set to max(tMRR, tMRW)
1104 */
1105 tmrd = 5;
1106 tras = DIV_ROUND_UP(lpddr2_cfg->trasmin, clkper / 10) - 1;
1107 /* LPDDR2 mode use tRCD_LP filed in MDCFG3. */
1108 trcd_lp = DIV_ROUND_UP(lpddr2_cfg->trcd_lp, clkper / 10) - 1;
1109 trc_lp = DIV_ROUND_UP(lpddr2_cfg->trasmin + lpddr2_cfg->trppb_lp,
1110 clkper / 10) - 1;
1111 trppb_lp = DIV_ROUND_UP(lpddr2_cfg->trppb_lp, clkper / 10) - 1;
1112 trpab_lp = DIV_ROUND_UP(lpddr2_cfg->trpab_lp, clkper / 10) - 1;
1113 /* To LPDDR2, CL in MDCFG0 refers to RL */
1114 tcl = lpddr2_rl(lpddr2_cfg->mem_speed) - 3;
1115 twtr = DIV_ROUND_UP(7500, clkper) - 1;
1116 trtp = DIV_ROUND_UP(7500, clkper) - 1;
1117
1118 cs0_end = 4 * sysinfo->cs_density - 1;
1119
1120 debug("density:%d Gb (%d Gb per chip)\n",
1121 sysinfo->cs_density, lpddr2_cfg->density);
1122 debug("clock: %dMHz (%d ps)\n", clock, clkper);
1123 debug("memspd:%d\n", lpddr2_cfg->mem_speed);
1124 debug("trcd_lp=%d\n", trcd_lp);
1125 debug("trppb_lp=%d\n", trppb_lp);
1126 debug("trpab_lp=%d\n", trpab_lp);
1127 debug("trc_lp=%d\n", trc_lp);
1128 debug("tcke=%d\n", tcke);
1129 debug("tcksrx=%d\n", tcksrx);
1130 debug("tcksre=%d\n", tcksre);
1131 debug("trfc=%d\n", trfc);
1132 debug("txsr=%d\n", txsr);
1133 debug("txp=%d\n", txp);
1134 debug("tfaw=%d\n", tfaw);
1135 debug("tcl=%d\n", tcl);
1136 debug("tras=%d\n", tras);
1137 debug("twr=%d\n", twr);
1138 debug("tmrd=%d\n", tmrd);
1139 debug("twl=%d\n", twl);
1140 debug("trtp=%d\n", trtp);
1141 debug("twtr=%d\n", twtr);
1142 debug("trrd=%d\n", trrd);
1143 debug("cs0_end=%d\n", cs0_end);
1144 debug("ncs=%d\n", sysinfo->ncs);
1145
1146 /*
1147 * board-specific configuration:
1148 * These values are determined empirically and vary per board layout
1149 */
1150 mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
1151 mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
1152 mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
1153 mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
1154 mmdc0->mprddlctl = calib->p0_mprddlctl;
1155 mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
1156 mmdc0->mpzqlp2ctl = calib->mpzqlp2ctl;
1157
1158 /* Read data DQ Byte0-3 delay */
1159 mmdc0->mprddqby0dl = 0x33333333;
1160 mmdc0->mprddqby1dl = 0x33333333;
1161 if (sysinfo->dsize > 0) {
1162 mmdc0->mprddqby2dl = 0x33333333;
1163 mmdc0->mprddqby3dl = 0x33333333;
1164 }
1165
1166 /* Write data DQ Byte0-3 delay */
1167 mmdc0->mpwrdqby0dl = 0xf3333333;
1168 mmdc0->mpwrdqby1dl = 0xf3333333;
1169 if (sysinfo->dsize > 0) {
1170 mmdc0->mpwrdqby2dl = 0xf3333333;
1171 mmdc0->mpwrdqby3dl = 0xf3333333;
1172 }
1173
1174 /*
1175 * In LPDDR2 mode this register should be cleared,
1176 * so no termination will be activated.
1177 */
1178 mmdc0->mpodtctrl = 0;
1179
1180 /* complete calibration */
1181 val = (1 << 11); /* Force measurement on delay-lines */
1182 mmdc0->mpmur0 = val;
1183
1184 /* Step 1: configuration request */
1185 mmdc0->mdscr = (u32)(1 << 15); /* config request */
1186
1187 /* Step 2: Timing configuration */
1188 mmdc0->mdcfg0 = (trfc << 24) | (txsr << 16) | (txp << 13) |
1189 (tfaw << 4) | tcl;
1190 mmdc0->mdcfg1 = (tras << 16) | (twr << 9) | (tmrd << 5) | twl;
1191 mmdc0->mdcfg2 = (trtp << 6) | (twtr << 3) | trrd;
1192 mmdc0->mdcfg3lp = (trc_lp << 16) | (trcd_lp << 8) |
1193 (trppb_lp << 4) | trpab_lp;
1194 mmdc0->mdotc = 0;
1195
1196 mmdc0->mdasp = cs0_end; /* CS addressing */
1197
1198 /* Step 3: Configure DDR type */
1199 mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
1200 (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
1201 (sysinfo->ralat << 6) | (1 << 3);
1202
1203 /* Step 4: Configure delay while leaving reset */
1204 mmdc0->mdor = (sysinfo->sde_to_rst << 8) |
1205 (sysinfo->rst_to_cke << 0);
1206
1207 /* Step 5: Configure DDR physical parameters (density and burst len) */
1208 coladdr = lpddr2_cfg->coladdr;
1209 if (lpddr2_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
1210 coladdr += 4;
1211 else if (lpddr2_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
1212 coladdr += 1;
1213 mmdc0->mdctl = (lpddr2_cfg->rowaddr - 11) << 24 | /* ROW */
1214 (coladdr - 9) << 20 | /* COL */
1215 (0 << 19) | /* Burst Length = 4 for LPDDR2 */
1216 (sysinfo->dsize << 16); /* DDR data bus size */
1217
1218 /* Step 6: Perform ZQ calibration */
1219 val = 0xa1390003; /* one-time HW ZQ calib */
1220 mmdc0->mpzqhwctrl = val;
1221
1222 /* Step 7: Enable MMDC with desired chip select */
1223 mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
1224 ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
1225
1226 /* Step 8: Write Mode Registers to Init LPDDR2 devices */
1227 for (cs = 0; cs < sysinfo->ncs; cs++) {
1228 /* MR63: reset */
1229 mmdc0->mdscr = MR(63, 0, 3, cs);
1230 /* MR10: calibration,
1231 * 0xff is calibration command after intilization.
1232 */
1233 val = 0xA | (0xff << 8);
1234 mmdc0->mdscr = MR(val, 0, 3, cs);
1235 /* MR1 */
1236 val = 0x1 | (0x82 << 8);
1237 mmdc0->mdscr = MR(val, 0, 3, cs);
1238 /* MR2 */
1239 val = 0x2 | (0x04 << 8);
1240 mmdc0->mdscr = MR(val, 0, 3, cs);
1241 /* MR3 */
1242 val = 0x3 | (0x02 << 8);
1243 mmdc0->mdscr = MR(val, 0, 3, cs);
1244 }
1245
1246 /* Step 10: Power down control and self-refresh */
1247 mmdc0->mdpdc = (tcke & 0x7) << 16 |
1248 5 << 12 | /* PWDT_1: 256 cycles */
1249 5 << 8 | /* PWDT_0: 256 cycles */
1250 1 << 6 | /* BOTH_CS_PD */
1251 (tcksrx & 0x7) << 3 |
1252 (tcksre & 0x7);
1253 mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
1254
1255 /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
1256 val = 0xa1310003;
1257 mmdc0->mpzqhwctrl = val;
1258
1259 /* Step 12: Configure and activate periodic refresh */
1260 mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
1261
1262 /* Step 13: Deassert config request - init complete */
1263 mmdc0->mdscr = 0x00000000;
1264
1265 /* wait for auto-ZQ calibration to complete */
1266 mdelay(1);
1267 }
1268
mx6_ddr3_cfg(const struct mx6_ddr_sysinfo * sysinfo,const struct mx6_mmdc_calibration * calib,const struct mx6_ddr3_cfg * ddr3_cfg)1269 void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
1270 const struct mx6_mmdc_calibration *calib,
1271 const struct mx6_ddr3_cfg *ddr3_cfg)
1272 {
1273 volatile struct mmdc_p_regs *mmdc0;
1274 volatile struct mmdc_p_regs *mmdc1;
1275 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
1276 u8 soc_boot_cfg3 = (readl(&src_regs->sbmr1) >> 16) & 0xff;
1277 u32 val;
1278 u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
1279 u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
1280 u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
1281 u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
1282 u16 cs0_end;
1283 u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
1284 u8 coladdr;
1285 int clkper; /* clock period in picoseconds */
1286 int clock; /* clock freq in MHz */
1287 int cs;
1288 u16 mem_speed = ddr3_cfg->mem_speed;
1289
1290 mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
1291 if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl())
1292 mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
1293
1294 /* Limit mem_speed for MX6D/MX6Q */
1295 if (is_mx6dq() || is_mx6dqp()) {
1296 if (mem_speed > 1066)
1297 mem_speed = 1066; /* 1066 MT/s */
1298
1299 tcwl = 4;
1300 }
1301 /* Limit mem_speed for MX6S/MX6DL */
1302 else {
1303 if (mem_speed > 800)
1304 mem_speed = 800; /* 800 MT/s */
1305
1306 tcwl = 3;
1307 }
1308
1309 clock = mem_speed / 2;
1310 /*
1311 * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports
1312 * up to 528 MHz, so reduce the clock to fit chip specs
1313 */
1314 if (is_mx6dq() || is_mx6dqp()) {
1315 if (clock > 528)
1316 clock = 528; /* 528 MHz */
1317 }
1318
1319 clkper = (1000 * 1000) / clock; /* pico seconds */
1320 todtlon = tcwl;
1321 taxpd = tcwl;
1322 tanpd = tcwl;
1323
1324 switch (ddr3_cfg->density) {
1325 case 1: /* 1Gb per chip */
1326 trfc = DIV_ROUND_UP(110000, clkper) - 1;
1327 txs = DIV_ROUND_UP(120000, clkper) - 1;
1328 break;
1329 case 2: /* 2Gb per chip */
1330 trfc = DIV_ROUND_UP(160000, clkper) - 1;
1331 txs = DIV_ROUND_UP(170000, clkper) - 1;
1332 break;
1333 case 4: /* 4Gb per chip */
1334 trfc = DIV_ROUND_UP(260000, clkper) - 1;
1335 txs = DIV_ROUND_UP(270000, clkper) - 1;
1336 break;
1337 case 8: /* 8Gb per chip */
1338 trfc = DIV_ROUND_UP(350000, clkper) - 1;
1339 txs = DIV_ROUND_UP(360000, clkper) - 1;
1340 break;
1341 default:
1342 /* invalid density */
1343 puts("invalid chip density\n");
1344 hang();
1345 break;
1346 }
1347 txpr = txs;
1348
1349 switch (mem_speed) {
1350 case 800:
1351 txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
1352 tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
1353 if (ddr3_cfg->pagesz == 1) {
1354 tfaw = DIV_ROUND_UP(40000, clkper) - 1;
1355 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
1356 } else {
1357 tfaw = DIV_ROUND_UP(50000, clkper) - 1;
1358 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
1359 }
1360 break;
1361 case 1066:
1362 txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
1363 tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
1364 if (ddr3_cfg->pagesz == 1) {
1365 tfaw = DIV_ROUND_UP(37500, clkper) - 1;
1366 trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
1367 } else {
1368 tfaw = DIV_ROUND_UP(50000, clkper) - 1;
1369 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
1370 }
1371 break;
1372 default:
1373 puts("invalid memory speed\n");
1374 hang();
1375 break;
1376 }
1377 txpdll = DIV_ROUND_UP(max(10 * clkper, 24000), clkper) - 1;
1378 tcksre = DIV_ROUND_UP(max(5 * clkper, 10000), clkper);
1379 taonpd = DIV_ROUND_UP(2000, clkper) - 1;
1380 tcksrx = tcksre;
1381 taofpd = taonpd;
1382 twr = DIV_ROUND_UP(15000, clkper) - 1;
1383 tmrd = DIV_ROUND_UP(max(12 * clkper, 15000), clkper) - 1;
1384 trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;
1385 tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;
1386 tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;
1387 trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;
1388 twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1;
1389 trcd = trp;
1390 trtp = twtr;
1391 cs0_end = 4 * sysinfo->cs_density - 1;
1392
1393 debug("density:%d Gb (%d Gb per chip)\n",
1394 sysinfo->cs_density, ddr3_cfg->density);
1395 debug("clock: %dMHz (%d ps)\n", clock, clkper);
1396 debug("memspd:%d\n", mem_speed);
1397 debug("tcke=%d\n", tcke);
1398 debug("tcksrx=%d\n", tcksrx);
1399 debug("tcksre=%d\n", tcksre);
1400 debug("taofpd=%d\n", taofpd);
1401 debug("taonpd=%d\n", taonpd);
1402 debug("todtlon=%d\n", todtlon);
1403 debug("tanpd=%d\n", tanpd);
1404 debug("taxpd=%d\n", taxpd);
1405 debug("trfc=%d\n", trfc);
1406 debug("txs=%d\n", txs);
1407 debug("txp=%d\n", txp);
1408 debug("txpdll=%d\n", txpdll);
1409 debug("tfaw=%d\n", tfaw);
1410 debug("tcl=%d\n", tcl);
1411 debug("trcd=%d\n", trcd);
1412 debug("trp=%d\n", trp);
1413 debug("trc=%d\n", trc);
1414 debug("tras=%d\n", tras);
1415 debug("twr=%d\n", twr);
1416 debug("tmrd=%d\n", tmrd);
1417 debug("tcwl=%d\n", tcwl);
1418 debug("tdllk=%d\n", tdllk);
1419 debug("trtp=%d\n", trtp);
1420 debug("twtr=%d\n", twtr);
1421 debug("trrd=%d\n", trrd);
1422 debug("txpr=%d\n", txpr);
1423 debug("cs0_end=%d\n", cs0_end);
1424 debug("ncs=%d\n", sysinfo->ncs);
1425 debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
1426 debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
1427 debug("SRT=%d\n", ddr3_cfg->SRT);
1428 debug("twr=%d\n", twr);
1429
1430 /*
1431 * board-specific configuration:
1432 * These values are determined empirically and vary per board layout
1433 * see:
1434 * appnote, ddr3 spreadsheet
1435 */
1436 mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
1437 mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
1438 mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
1439 mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
1440 mmdc0->mprddlctl = calib->p0_mprddlctl;
1441 mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
1442 if (sysinfo->dsize > 1) {
1443 MMDC1(mpwldectrl0, calib->p1_mpwldectrl0);
1444 MMDC1(mpwldectrl1, calib->p1_mpwldectrl1);
1445 MMDC1(mpdgctrl0, calib->p1_mpdgctrl0);
1446 MMDC1(mpdgctrl1, calib->p1_mpdgctrl1);
1447 MMDC1(mprddlctl, calib->p1_mprddlctl);
1448 MMDC1(mpwrdlctl, calib->p1_mpwrdlctl);
1449 }
1450
1451 /* Read data DQ Byte0-3 delay */
1452 mmdc0->mprddqby0dl = 0x33333333;
1453 mmdc0->mprddqby1dl = 0x33333333;
1454 if (sysinfo->dsize > 0) {
1455 mmdc0->mprddqby2dl = 0x33333333;
1456 mmdc0->mprddqby3dl = 0x33333333;
1457 }
1458
1459 if (sysinfo->dsize > 1) {
1460 MMDC1(mprddqby0dl, 0x33333333);
1461 MMDC1(mprddqby1dl, 0x33333333);
1462 MMDC1(mprddqby2dl, 0x33333333);
1463 MMDC1(mprddqby3dl, 0x33333333);
1464 }
1465
1466 /* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
1467 val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
1468 mmdc0->mpodtctrl = val;
1469 if (sysinfo->dsize > 1)
1470 MMDC1(mpodtctrl, val);
1471
1472 /* complete calibration */
1473 val = (1 << 11); /* Force measurement on delay-lines */
1474 mmdc0->mpmur0 = val;
1475 if (sysinfo->dsize > 1)
1476 MMDC1(mpmur0, val);
1477
1478 /* Step 1: configuration request */
1479 mmdc0->mdscr = (u32)(1 << 15); /* config request */
1480
1481 /* Step 2: Timing configuration */
1482 mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |
1483 (txpdll << 9) | (tfaw << 4) | tcl;
1484 mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |
1485 (tras << 16) | (1 << 15) /* trpa */ |
1486 (twr << 9) | (tmrd << 5) | tcwl;
1487 mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
1488 mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |
1489 (taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4);
1490 mmdc0->mdasp = cs0_end; /* CS addressing */
1491
1492 /* Step 3: Configure DDR type */
1493 mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
1494 (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
1495 (sysinfo->ralat << 6);
1496
1497 /* Step 4: Configure delay while leaving reset */
1498 mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |
1499 (sysinfo->rst_to_cke << 0);
1500
1501 /* Step 5: Configure DDR physical parameters (density and burst len) */
1502 coladdr = ddr3_cfg->coladdr;
1503 if (ddr3_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
1504 coladdr += 4;
1505 else if (ddr3_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
1506 coladdr += 1;
1507 mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */
1508 (coladdr - 9) << 20 | /* COL */
1509 (1 << 19) | /* Burst Length = 8 for DDR3 */
1510 (sysinfo->dsize << 16); /* DDR data bus size */
1511
1512 /* Step 6: Perform ZQ calibration */
1513 val = 0xa1390001; /* one-time HW ZQ calib */
1514 mmdc0->mpzqhwctrl = val;
1515 if (sysinfo->dsize > 1)
1516 MMDC1(mpzqhwctrl, val);
1517
1518 /* Step 7: Enable MMDC with desired chip select */
1519 mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
1520 ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
1521
1522 /* Step 8: Write Mode Registers to Init DDR3 devices */
1523 for (cs = 0; cs < sysinfo->ncs; cs++) {
1524 /* MR2 */
1525 val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
1526 ((tcwl - 3) & 3) << 3;
1527 debug("MR2 CS%d: 0x%08x\n", cs, (u32)MR(val, 2, 3, cs));
1528 mmdc0->mdscr = MR(val, 2, 3, cs);
1529 /* MR3 */
1530 debug("MR3 CS%d: 0x%08x\n", cs, (u32)MR(0, 3, 3, cs));
1531 mmdc0->mdscr = MR(0, 3, 3, cs);
1532 /* MR1 */
1533 val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
1534 ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
1535 debug("MR1 CS%d: 0x%08x\n", cs, (u32)MR(val, 1, 3, cs));
1536 mmdc0->mdscr = MR(val, 1, 3, cs);
1537 /* MR0 */
1538 val = ((tcl - 1) << 4) | /* CAS */
1539 (1 << 8) | /* DLL Reset */
1540 ((twr - 3) << 9) | /* Write Recovery */
1541 (sysinfo->pd_fast_exit << 12); /* Precharge PD PLL on */
1542 debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs));
1543 mmdc0->mdscr = MR(val, 0, 3, cs);
1544 /* ZQ calibration */
1545 val = (1 << 10);
1546 mmdc0->mdscr = MR(val, 0, 4, cs);
1547 }
1548
1549 /* Step 10: Power down control and self-refresh */
1550 mmdc0->mdpdc = (tcke & 0x7) << 16 |
1551 5 << 12 | /* PWDT_1: 256 cycles */
1552 5 << 8 | /* PWDT_0: 256 cycles */
1553 1 << 6 | /* BOTH_CS_PD */
1554 (tcksrx & 0x7) << 3 |
1555 (tcksre & 0x7);
1556 if (!sysinfo->pd_fast_exit)
1557 mmdc0->mdpdc |= (1 << 7); /* SLOW_PD */
1558 mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
1559
1560 /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
1561 val = 0xa1390003;
1562 mmdc0->mpzqhwctrl = val;
1563 if (sysinfo->dsize > 1)
1564 MMDC1(mpzqhwctrl, val);
1565
1566 /* Step 12: Configure and activate periodic refresh */
1567 mmdc0->mdref = (sysinfo->refsel << 14) | (sysinfo->refr << 11);
1568
1569 /*
1570 * Step 13: i.MX6DQP only: If the NoC scheduler is enabled,
1571 * configure it and disable MMDC arbitration/reordering (see EB828)
1572 */
1573 if (is_mx6dqp() &&
1574 ((soc_boot_cfg3 & BOOT_CFG3_DDR_MASK) == DDR_MMAP_NOC_SINGLE ||
1575 (soc_boot_cfg3 & BOOT_CFG3_EXT_DDR_MASK) == DDR_MMAP_NOC_DUAL)) {
1576 struct mx6dqp_noc_sched_regs *noc_sched =
1577 (struct mx6dqp_noc_sched_regs *)MX6DQP_NOC_SCHED_BASE;
1578
1579 /*
1580 * These values are fixed based on integration parameters and
1581 * should not be modified
1582 */
1583 noc_sched->rlat = 0x00000040;
1584 noc_sched->ipu1 = 0x00000020;
1585 noc_sched->ipu2 = 0x00000020;
1586
1587 noc_sched->activate = (1 << NOC_FAW_BANKS_SHIFT) |
1588 (tfaw << NOC_FAW_PERIOD_SHIFT) |
1589 (trrd << NOC_RD_SHIFT);
1590 noc_sched->ddrtiming = (((sysinfo->dsize == 1) ? 1 : 0)
1591 << NOC_BW_RATIO_SHIFT) |
1592 ((tcwl + twtr) << NOC_WR_TO_RD_SHIFT) |
1593 ((tcl - tcwl + 2) << NOC_RD_TO_WR_SHIFT) |
1594 (4 << NOC_BURST_LEN_SHIFT) | /* BL8 */
1595 ((tcwl + twr + trp + trcd)
1596 << NOC_WR_TO_MISS_SHIFT) |
1597 ((trtp + trp + trcd - 4)
1598 << NOC_RD_TO_MISS_SHIFT) |
1599 (trc << NOC_ACT_TO_ACT_SHIFT);
1600
1601 if (sysinfo->dsize == 2) {
1602 if (ddr3_cfg->coladdr == 10) {
1603 if (ddr3_cfg->rowaddr == 15 &&
1604 sysinfo->ncs == 2)
1605 noc_sched->ddrconf = 4;
1606 else
1607 noc_sched->ddrconf = 0;
1608 } else if (ddr3_cfg->coladdr == 11) {
1609 noc_sched->ddrconf = 1;
1610 }
1611 } else {
1612 if (ddr3_cfg->coladdr == 9) {
1613 if (ddr3_cfg->rowaddr == 13)
1614 noc_sched->ddrconf = 2;
1615 else if (ddr3_cfg->rowaddr == 14)
1616 noc_sched->ddrconf = 15;
1617 } else if (ddr3_cfg->coladdr == 10) {
1618 if (ddr3_cfg->rowaddr == 14 &&
1619 sysinfo->ncs == 2)
1620 noc_sched->ddrconf = 14;
1621 else if (ddr3_cfg->rowaddr == 15 &&
1622 sysinfo->ncs == 2)
1623 noc_sched->ddrconf = 9;
1624 else
1625 noc_sched->ddrconf = 3;
1626 } else if (ddr3_cfg->coladdr == 11) {
1627 if (ddr3_cfg->rowaddr == 15 &&
1628 sysinfo->ncs == 2)
1629 noc_sched->ddrconf = 4;
1630 else
1631 noc_sched->ddrconf = 0;
1632 } else if (ddr3_cfg->coladdr == 12) {
1633 if (ddr3_cfg->rowaddr == 14)
1634 noc_sched->ddrconf = 1;
1635 }
1636 }
1637
1638 /* Disable MMDC arbitration/reordering */
1639 mmdc0->maarcr = 0x14420000;
1640 }
1641
1642 /* Step 13: Deassert config request - init complete */
1643 mmdc0->mdscr = 0x00000000;
1644
1645 /* wait for auto-ZQ calibration to complete */
1646 mdelay(1);
1647 }
1648
mmdc_read_calibration(struct mx6_ddr_sysinfo const * sysinfo,struct mx6_mmdc_calibration * calib)1649 void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
1650 struct mx6_mmdc_calibration *calib)
1651 {
1652 struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
1653 struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
1654
1655 calib->p0_mpwldectrl0 = readl(&mmdc0->mpwldectrl0);
1656 calib->p0_mpwldectrl1 = readl(&mmdc0->mpwldectrl1);
1657 calib->p0_mpdgctrl0 = readl(&mmdc0->mpdgctrl0);
1658 calib->p0_mpdgctrl1 = readl(&mmdc0->mpdgctrl1);
1659 calib->p0_mprddlctl = readl(&mmdc0->mprddlctl);
1660 calib->p0_mpwrdlctl = readl(&mmdc0->mpwrdlctl);
1661
1662 if (sysinfo->dsize == 2) {
1663 calib->p1_mpwldectrl0 = readl(&mmdc1->mpwldectrl0);
1664 calib->p1_mpwldectrl1 = readl(&mmdc1->mpwldectrl1);
1665 calib->p1_mpdgctrl0 = readl(&mmdc1->mpdgctrl0);
1666 calib->p1_mpdgctrl1 = readl(&mmdc1->mpdgctrl1);
1667 calib->p1_mprddlctl = readl(&mmdc1->mprddlctl);
1668 calib->p1_mpwrdlctl = readl(&mmdc1->mpwrdlctl);
1669 }
1670 }
1671
mx6_dram_cfg(const struct mx6_ddr_sysinfo * sysinfo,const struct mx6_mmdc_calibration * calib,const void * ddr_cfg)1672 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
1673 const struct mx6_mmdc_calibration *calib,
1674 const void *ddr_cfg)
1675 {
1676 if (sysinfo->ddr_type == DDR_TYPE_DDR3) {
1677 mx6_ddr3_cfg(sysinfo, calib, ddr_cfg);
1678 } else if (sysinfo->ddr_type == DDR_TYPE_LPDDR2) {
1679 mx6_lpddr2_cfg(sysinfo, calib, ddr_cfg);
1680 } else {
1681 puts("Unsupported ddr type\n");
1682 hang();
1683 }
1684 }
1685