1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * K3: AM64 SoC definitions, structures etc. 4 * 5 * (C) Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 #ifndef __ASM_ARCH_AM64_HARDWARE_H 8 #define __ASM_ARCH_AM64_HARDWARE_H 9 10 #include <config.h> 11 12 #define CTRL_MMR0_BASE 0x43000000 13 #define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) 14 15 #define PADCFG_MMR1_BASE 0xf0000 16 17 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK 0x00000078 18 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 19 20 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK 0x00000380 21 #define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7 22 23 #define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK 0x00001c00 24 #define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10 25 26 #define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK 0x00002000 27 #define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13 28 29 /* After the cfg mask and shifts have been applied */ 30 #define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2 31 #define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x04 32 33 /* 34 * The CTRL_MMR and PADCFG_MMR memory space is divided into several 35 * equally-spaced partitions, so defining the partition size allows us to 36 * determine register addresses common to those partitions. 37 */ 38 #define CTRL_MMR0_PARTITION_SIZE 0x4000 39 40 /* 41 * CTRL_MMR and PADCFG_MMR lock/kick-mechanism shared register definitions. 42 */ 43 #define CTRLMMR_LOCK_KICK0 0x01008 44 #define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 45 #define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0) 46 #define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0 47 #define CTRLMMR_LOCK_KICK1 0x0100c 48 #define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a 49 50 #define ROM_ENTENDED_BOOT_DATA_INFO 0x701beb00 51 52 /* Use Last 1K as Scratch pad */ 53 #define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x701bfc00 54 55 #endif /* __ASM_ARCH_DRA8_HARDWARE_H */ 56