1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 *
5 * Dave Liu <daveliu@freescale.com>
6 */
7
8 #include <common.h>
9 #include <fdt_support.h>
10 #include <init.h>
11 #include <ioports.h>
12 #include <mpc83xx.h>
13 #include <i2c.h>
14 #include <miiphy.h>
15 #include <command.h>
16 #if defined(CONFIG_PCI)
17 #include <pci.h>
18 #endif
19 #include <asm/global_data.h>
20 #include <asm/mmu.h>
21 #if defined(CONFIG_OF_LIBFDT)
22 #include <linux/libfdt.h>
23 #endif
24 #if defined(CONFIG_PQ_MDS_PIB)
25 #include "../common/pq-mds-pib.h"
26 #endif
27 #include <linux/delay.h>
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 const qe_iop_conf_t qe_iop_conf_tab[] = {
32 /* ETH3 */
33 {1, 0, 1, 0, 1}, /* TxD0 */
34 {1, 1, 1, 0, 1}, /* TxD1 */
35 {1, 2, 1, 0, 1}, /* TxD2 */
36 {1, 3, 1, 0, 1}, /* TxD3 */
37 {1, 9, 1, 0, 1}, /* TxER */
38 {1, 12, 1, 0, 1}, /* TxEN */
39 {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
40
41 {1, 4, 2, 0, 1}, /* RxD0 */
42 {1, 5, 2, 0, 1}, /* RxD1 */
43 {1, 6, 2, 0, 1}, /* RxD2 */
44 {1, 7, 2, 0, 1}, /* RxD3 */
45 {1, 8, 2, 0, 1}, /* RxER */
46 {1, 10, 2, 0, 1}, /* RxDV */
47 {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
48 {1, 11, 2, 0, 1}, /* COL */
49 {1, 13, 2, 0, 1}, /* CRS */
50
51 /* ETH4 */
52 {1, 18, 1, 0, 1}, /* TxD0 */
53 {1, 19, 1, 0, 1}, /* TxD1 */
54 {1, 20, 1, 0, 1}, /* TxD2 */
55 {1, 21, 1, 0, 1}, /* TxD3 */
56 {1, 27, 1, 0, 1}, /* TxER */
57 {1, 30, 1, 0, 1}, /* TxEN */
58 {3, 6, 2, 0, 1}, /* TxCLK->CLK8 */
59
60 {1, 22, 2, 0, 1}, /* RxD0 */
61 {1, 23, 2, 0, 1}, /* RxD1 */
62 {1, 24, 2, 0, 1}, /* RxD2 */
63 {1, 25, 2, 0, 1}, /* RxD3 */
64 {1, 26, 1, 0, 1}, /* RxER */
65 {1, 28, 2, 0, 1}, /* Rx_DV */
66 {3, 31, 2, 0, 1}, /* RxCLK->CLK7 */
67 {1, 29, 2, 0, 1}, /* COL */
68 {1, 31, 2, 0, 1}, /* CRS */
69
70 {3, 4, 3, 0, 2}, /* MDIO */
71 {3, 5, 1, 0, 2}, /* MDC */
72
73 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
74 };
75
board_early_init_f(void)76 int board_early_init_f(void)
77 {
78 volatile u8 *bcsr = (volatile u8 *)CONFIG_SYS_BCSR;
79
80 /* Enable flash write */
81 bcsr[9] &= ~0x08;
82
83 return 0;
84 }
85
board_early_init_r(void)86 int board_early_init_r(void)
87 {
88 #ifdef CONFIG_PQ_MDS_PIB
89 pib_init();
90 #endif
91 return 0;
92 }
93
94 int fixed_sdram(void);
95
dram_init(void)96 int dram_init(void)
97 {
98 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
99 u32 msize = 0;
100
101 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
102 return -ENXIO;
103
104 /* DDR SDRAM - Main SODIMM */
105 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
106
107 msize = fixed_sdram();
108
109 /* set total bus SDRAM size(bytes) -- DDR */
110 gd->ram_size = msize * 1024 * 1024;
111
112 return 0;
113 }
114
115 /*************************************************************************
116 * fixed sdram init -- doesn't use serial presence detect.
117 ************************************************************************/
fixed_sdram(void)118 int fixed_sdram(void)
119 {
120 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
121 u32 msize = 0;
122 u32 ddr_size;
123 u32 ddr_size_log2;
124
125 msize = CONFIG_SYS_DDR_SIZE;
126 for (ddr_size = msize << 20, ddr_size_log2 = 0;
127 (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
128 if (ddr_size & 1) {
129 return -1;
130 }
131 }
132 im->sysconf.ddrlaw[0].ar =
133 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
134 #if (CONFIG_SYS_DDR_SIZE != 128)
135 #warning Currenly any ddr size other than 128 is not supported
136 #endif
137 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
138 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
139 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
140 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
141 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
142 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
143 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
144 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
145 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
146 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
147 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
148 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
149 __asm__ __volatile__ ("sync");
150 udelay(200);
151
152 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
153 __asm__ __volatile__ ("sync");
154 return msize;
155 }
156
checkboard(void)157 int checkboard(void)
158 {
159 puts("Board: Freescale MPC832XEMDS\n");
160 return 0;
161 }
162
163 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,struct bd_info * bd)164 int ft_board_setup(void *blob, struct bd_info *bd)
165 {
166 ft_cpu_setup(blob, bd);
167 #ifdef CONFIG_PCI
168 ft_pci_setup(blob, bd);
169 #endif
170
171 return 0;
172 }
173 #endif
174