1config ARCH_LS1012A 2 bool 3 select ARMV8_SET_SMPEN 4 select ARM_ERRATA_855873 if !TFABOOT 5 select FSL_LAYERSCAPE 6 select FSL_LSCH2 7 select SYS_FSL_SRDS_1 8 select SYS_HAS_SERDES 9 select SYS_FSL_DDR_BE 10 select SYS_FSL_MMDC 11 select SYS_FSL_ERRATUM_A010315 12 select SYS_FSL_ERRATUM_A009798 13 select SYS_FSL_ERRATUM_A008997 14 select SYS_FSL_ERRATUM_A009007 15 select SYS_FSL_ERRATUM_A009008 16 select ARCH_EARLY_INIT_R 17 select BOARD_EARLY_INIT_F 18 select SYS_I2C_MXC 19 select SYS_I2C_MXC_I2C1 if !DM_I2C 20 select SYS_I2C_MXC_I2C2 if !DM_I2C 21 imply PANIC_HANG 22 23config ARCH_LS1028A 24 bool 25 select ARMV8_SET_SMPEN 26 select FSL_LAYERSCAPE 27 select FSL_LSCH3 28 select NXP_LSCH3_2 29 select SYS_FSL_HAS_CCI400 30 select SYS_FSL_SRDS_1 31 select SYS_HAS_SERDES 32 select SYS_FSL_DDR 33 select SYS_FSL_DDR_LE 34 select SYS_FSL_DDR_VER_50 35 select SYS_FSL_HAS_DDR3 36 select SYS_FSL_HAS_DDR4 37 select SYS_FSL_HAS_SEC 38 select SYS_FSL_SEC_COMPAT_5 39 select SYS_FSL_SEC_LE 40 select FSL_TZASC_1 41 select ARCH_EARLY_INIT_R 42 select BOARD_EARLY_INIT_F 43 select SYS_I2C_MXC 44 select SYS_FSL_ERRATUM_A008997 45 select SYS_FSL_ERRATUM_A009007 46 select SYS_FSL_ERRATUM_A008514 if !TFABOOT 47 select SYS_FSL_ERRATUM_A009663 if !TFABOOT 48 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 49 select SYS_FSL_ERRATUM_A050382 50 select SYS_FSL_ERRATUM_A011334 51 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND 52 select RESV_RAM if GIC_V3_ITS 53 imply PANIC_HANG 54 55config ARCH_LS1043A 56 bool 57 select ARMV8_SET_SMPEN 58 select ARM_ERRATA_855873 if !TFABOOT 59 select FSL_LAYERSCAPE 60 select FSL_LSCH2 61 select SYS_FSL_SRDS_1 62 select SYS_HAS_SERDES 63 select SYS_FSL_DDR 64 select SYS_FSL_DDR_BE 65 select SYS_FSL_DDR_VER_50 66 select SYS_FSL_ERRATUM_A008850 if !TFABOOT 67 select SYS_FSL_ERRATUM_A008997 68 select SYS_FSL_ERRATUM_A009007 69 select SYS_FSL_ERRATUM_A009008 70 select SYS_FSL_ERRATUM_A009660 if !TFABOOT 71 select SYS_FSL_ERRATUM_A009663 if !TFABOOT 72 select SYS_FSL_ERRATUM_A009798 73 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 74 select SYS_FSL_ERRATUM_A010315 75 select SYS_FSL_ERRATUM_A010539 76 select SYS_FSL_HAS_DDR3 77 select SYS_FSL_HAS_DDR4 78 select ARCH_EARLY_INIT_R 79 select BOARD_EARLY_INIT_F 80 select SYS_I2C_MXC 81 select SYS_I2C_MXC_I2C1 if !DM_I2C 82 select SYS_I2C_MXC_I2C2 if !DM_I2C 83 select SYS_I2C_MXC_I2C3 if !DM_I2C 84 select SYS_I2C_MXC_I2C4 if !DM_I2C 85 imply CMD_PCI 86 87config ARCH_LS1046A 88 bool 89 select ARMV8_SET_SMPEN 90 select FSL_LAYERSCAPE 91 select FSL_LSCH2 92 select SYS_FSL_SRDS_1 93 select SYS_HAS_SERDES 94 select SYS_FSL_DDR 95 select SYS_FSL_DDR_BE 96 select SYS_FSL_DDR_VER_50 97 select SYS_FSL_ERRATUM_A008336 if !TFABOOT 98 select SYS_FSL_ERRATUM_A008511 if !TFABOOT 99 select SYS_FSL_ERRATUM_A008850 if !TFABOOT 100 select SYS_FSL_ERRATUM_A008997 101 select SYS_FSL_ERRATUM_A009007 102 select SYS_FSL_ERRATUM_A009008 103 select SYS_FSL_ERRATUM_A009798 104 select SYS_FSL_ERRATUM_A009801 105 select SYS_FSL_ERRATUM_A009803 if !TFABOOT 106 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 107 select SYS_FSL_ERRATUM_A010165 if !TFABOOT 108 select SYS_FSL_ERRATUM_A010539 109 select SYS_FSL_HAS_DDR4 110 select SYS_FSL_SRDS_2 111 select ARCH_EARLY_INIT_R 112 select BOARD_EARLY_INIT_F 113 select SYS_I2C_MXC 114 select SYS_I2C_MXC_I2C1 if !DM_I2C 115 select SYS_I2C_MXC_I2C2 if !DM_I2C 116 select SYS_I2C_MXC_I2C3 if !DM_I2C 117 select SYS_I2C_MXC_I2C4 if !DM_I2C 118 imply SCSI 119 imply SCSI_AHCI 120 121config ARCH_LS1088A 122 bool 123 select ARMV8_SET_SMPEN 124 select ARM_ERRATA_855873 if !TFABOOT 125 select FSL_LAYERSCAPE 126 select FSL_LSCH3 127 select SYS_FSL_SRDS_1 128 select SYS_HAS_SERDES 129 select SYS_FSL_DDR 130 select SYS_FSL_DDR_LE 131 select SYS_FSL_DDR_VER_50 132 select SYS_FSL_EC1 133 select SYS_FSL_EC2 134 select SYS_FSL_ERRATUM_A009803 if !TFABOOT 135 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 136 select SYS_FSL_ERRATUM_A010165 if !TFABOOT 137 select SYS_FSL_ERRATUM_A008511 if !TFABOOT 138 select SYS_FSL_ERRATUM_A008850 if !TFABOOT 139 select SYS_FSL_ERRATUM_A009007 140 select SYS_FSL_HAS_CCI400 141 select SYS_FSL_HAS_DDR4 142 select SYS_FSL_HAS_RGMII 143 select SYS_FSL_HAS_SEC 144 select SYS_FSL_SEC_COMPAT_5 145 select SYS_FSL_SEC_LE 146 select SYS_FSL_SRDS_1 147 select SYS_FSL_SRDS_2 148 select FSL_TZASC_1 149 select FSL_TZASC_400 150 select FSL_TZPC_BP147 151 select ARCH_EARLY_INIT_R 152 select BOARD_EARLY_INIT_F 153 select SYS_I2C_MXC 154 select SYS_I2C_MXC_I2C1 if !TFABOOT 155 select SYS_I2C_MXC_I2C2 if !TFABOOT 156 select SYS_I2C_MXC_I2C3 if !TFABOOT 157 select SYS_I2C_MXC_I2C4 if !TFABOOT 158 select RESV_RAM if GIC_V3_ITS 159 imply SCSI 160 imply PANIC_HANG 161 162config ARCH_LS2080A 163 bool 164 select ARMV8_SET_SMPEN 165 select ARM_ERRATA_826974 166 select ARM_ERRATA_828024 167 select ARM_ERRATA_829520 168 select ARM_ERRATA_833471 169 select FSL_LAYERSCAPE 170 select FSL_LSCH3 171 select SYS_FSL_SRDS_1 172 select SYS_HAS_SERDES 173 select SYS_FSL_DDR 174 select SYS_FSL_DDR_LE 175 select SYS_FSL_DDR_VER_50 176 select SYS_FSL_HAS_CCN504 177 select SYS_FSL_HAS_DP_DDR 178 select SYS_FSL_HAS_SEC 179 select SYS_FSL_HAS_DDR4 180 select SYS_FSL_SEC_COMPAT_5 181 select SYS_FSL_SEC_LE 182 select SYS_FSL_SRDS_2 183 select FSL_TZASC_1 184 select FSL_TZASC_2 185 select FSL_TZASC_400 186 select FSL_TZPC_BP147 187 select SYS_FSL_ERRATUM_A008336 if !TFABOOT 188 select SYS_FSL_ERRATUM_A008511 if !TFABOOT 189 select SYS_FSL_ERRATUM_A008514 if !TFABOOT 190 select SYS_FSL_ERRATUM_A008585 191 select SYS_FSL_ERRATUM_A008997 192 select SYS_FSL_ERRATUM_A009007 193 select SYS_FSL_ERRATUM_A009008 194 select SYS_FSL_ERRATUM_A009635 195 select SYS_FSL_ERRATUM_A009663 if !TFABOOT 196 select SYS_FSL_ERRATUM_A009798 197 select SYS_FSL_ERRATUM_A009801 198 select SYS_FSL_ERRATUM_A009803 if !TFABOOT 199 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 200 select SYS_FSL_ERRATUM_A010165 if !TFABOOT 201 select SYS_FSL_ERRATUM_A009203 202 select ARCH_EARLY_INIT_R 203 select BOARD_EARLY_INIT_F 204 select SYS_I2C_MXC 205 select SYS_I2C_MXC_I2C1 if !TFABOOT 206 select SYS_I2C_MXC_I2C2 if !TFABOOT 207 select SYS_I2C_MXC_I2C3 if !TFABOOT 208 select SYS_I2C_MXC_I2C4 if !TFABOOT 209 select RESV_RAM if GIC_V3_ITS 210 imply DISTRO_DEFAULTS 211 imply PANIC_HANG 212 213config ARCH_LX2162A 214 bool 215 select ARMV8_SET_SMPEN 216 select FSL_LSCH3 217 select NXP_LSCH3_2 218 select SYS_HAS_SERDES 219 select SYS_FSL_SRDS_1 220 select SYS_FSL_SRDS_2 221 select SYS_FSL_DDR 222 select SYS_FSL_DDR_LE 223 select SYS_FSL_DDR_VER_50 224 select SYS_FSL_EC1 225 select SYS_FSL_EC2 226 select SYS_FSL_ERRATUM_A050204 227 select SYS_FSL_ERRATUM_A011334 228 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND 229 select SYS_FSL_HAS_RGMII 230 select SYS_FSL_HAS_SEC 231 select SYS_FSL_HAS_CCN508 232 select SYS_FSL_HAS_DDR4 233 select SYS_FSL_SEC_COMPAT_5 234 select SYS_FSL_SEC_LE 235 select ARCH_EARLY_INIT_R 236 select BOARD_EARLY_INIT_F 237 select SYS_I2C_MXC 238 select RESV_RAM if GIC_V3_ITS 239 imply DISTRO_DEFAULTS 240 imply PANIC_HANG 241 imply SCSI 242 imply SCSI_AHCI 243 244config ARCH_LX2160A 245 bool 246 select ARMV8_SET_SMPEN 247 select FSL_LSCH3 248 select NXP_LSCH3_2 249 select SYS_HAS_SERDES 250 select SYS_FSL_SRDS_1 251 select SYS_FSL_SRDS_2 252 select SYS_NXP_SRDS_3 253 select SYS_FSL_DDR 254 select SYS_FSL_DDR_LE 255 select SYS_FSL_DDR_VER_50 256 select SYS_FSL_EC1 257 select SYS_FSL_EC2 258 select SYS_FSL_ERRATUM_A050204 259 select SYS_FSL_ERRATUM_A011334 260 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND 261 select SYS_FSL_HAS_RGMII 262 select SYS_FSL_HAS_SEC 263 select SYS_FSL_HAS_CCN508 264 select SYS_FSL_HAS_DDR4 265 select SYS_FSL_SEC_COMPAT_5 266 select SYS_FSL_SEC_LE 267 select ARCH_EARLY_INIT_R 268 select BOARD_EARLY_INIT_F 269 select SYS_I2C_MXC 270 select RESV_RAM if GIC_V3_ITS 271 imply DISTRO_DEFAULTS 272 imply PANIC_HANG 273 imply SCSI 274 imply SCSI_AHCI 275 276config FSL_LSCH2 277 bool 278 select SYS_FSL_HAS_CCI400 279 select SYS_FSL_HAS_SEC 280 select SYS_FSL_SEC_COMPAT_5 281 select SYS_FSL_SEC_BE 282 283config FSL_LSCH3 284 select ARCH_MISC_INIT 285 bool 286 287config NXP_LSCH3_2 288 bool 289 290menu "Layerscape architecture" 291 depends on FSL_LSCH2 || FSL_LSCH3 292 293config FSL_LAYERSCAPE 294 bool 295 296config HAS_FEATURE_GIC64K_ALIGN 297 bool 298 default y if ARCH_LS1043A 299 300config HAS_FEATURE_ENHANCED_MSI 301 bool 302 default y if ARCH_LS1043A 303 304menu "Layerscape PPA" 305config FSL_LS_PPA 306 bool "FSL Layerscape PPA firmware support" 307 depends on !ARMV8_PSCI 308 select ARMV8_SEC_FIRMWARE_SUPPORT 309 select SEC_FIRMWARE_ARMV8_PSCI 310 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 311 help 312 The FSL Primary Protected Application (PPA) is a software component 313 which is loaded during boot stage, and then remains resident in RAM 314 and runs in the TrustZone after boot. 315 Say y to enable it. 316 317config SPL_FSL_LS_PPA 318 bool "FSL Layerscape PPA firmware support for SPL build" 319 depends on !ARMV8_PSCI 320 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT 321 select SEC_FIRMWARE_ARMV8_PSCI 322 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 323 help 324 The FSL Primary Protected Application (PPA) is a software component 325 which is loaded during boot stage, and then remains resident in RAM 326 and runs in the TrustZone after boot. This is to load PPA during SPL 327 stage instead of the RAM version of U-Boot. Once PPA is initialized, 328 the rest of U-Boot (including RAM version) runs at EL2. 329choice 330 prompt "FSL Layerscape PPA firmware loading-media select" 331 depends on FSL_LS_PPA 332 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT 333 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT 334 default SYS_LS_PPA_FW_IN_XIP 335 336config SYS_LS_PPA_FW_IN_XIP 337 bool "XIP" 338 help 339 Say Y here if the PPA firmware locate at XIP flash, such 340 as NOR or QSPI flash. 341 342config SYS_LS_PPA_FW_IN_MMC 343 bool "eMMC or SD Card" 344 help 345 Say Y here if the PPA firmware locate at eMMC/SD card. 346 347config SYS_LS_PPA_FW_IN_NAND 348 bool "NAND" 349 help 350 Say Y here if the PPA firmware locate at NAND flash. 351 352endchoice 353 354config LS_PPA_ESBC_HDR_SIZE 355 hex "Length of PPA ESBC header" 356 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP 357 default 0x2000 358 help 359 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or 360 NAND to memory to validate PPA image. 361 362endmenu 363 364config SYS_FSL_ERRATUM_A008997 365 bool "Workaround for USB PHY erratum A008997" 366 367config SYS_FSL_ERRATUM_A009007 368 bool 369 help 370 Workaround for USB PHY erratum A009007 371 372config SYS_FSL_ERRATUM_A009008 373 bool "Workaround for USB PHY erratum A009008" 374 375config SYS_FSL_ERRATUM_A009798 376 bool "Workaround for USB PHY erratum A009798" 377 378config SYS_FSL_ERRATUM_A050204 379 bool "Workaround for USB PHY erratum A050204" 380 help 381 USB3.0 Receiver needs to enable fixed equalization 382 for each of PHY instances in an SOC. This is similar 383 to erratum A-009007, but this one is for LX2160A and LX2162A, 384 and the register value is different. 385 386config SYS_FSL_ERRATUM_A010315 387 bool "Workaround for PCIe erratum A010315" 388 389config SYS_FSL_ERRATUM_A010539 390 bool "Workaround for PIN MUX erratum A010539" 391 392config MAX_CPUS 393 int "Maximum number of CPUs permitted for Layerscape" 394 default 2 if ARCH_LS1028A 395 default 4 if ARCH_LS1043A 396 default 4 if ARCH_LS1046A 397 default 16 if ARCH_LS2080A 398 default 8 if ARCH_LS1088A 399 default 16 if ARCH_LX2160A 400 default 16 if ARCH_LX2162A 401 default 1 402 help 403 Set this number to the maximum number of possible CPUs in the SoC. 404 SoCs may have multiple clusters with each cluster may have multiple 405 ports. If some ports are reserved but higher ports are used for 406 cores, count the reserved ports. This will allocate enough memory 407 in spin table to properly handle all cores. 408 409config EMC2305 410 bool "Fan controller" 411 help 412 Enable the EMC2305 fan controller for configuration of fan 413 speed. 414 415config NXP_ESBC 416 bool "NXP_ESBC" 417 help 418 Enable Freescale Secure Boot feature 419 420config QSPI_AHB_INIT 421 bool "Init the QSPI AHB bus" 422 help 423 The default setting for QSPI AHB bus just support 3bytes addressing. 424 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 425 bus for those flashes to support the full QSPI flash size. 426 427config FSPI_AHB_EN_4BYTE 428 bool "Enable 4-byte Fast Read command for AHB mode" 429 default n 430 help 431 The default setting for FlexSPI AHB bus just supports 3-byte addressing. 432 But some FlexSPI flash sizes are up to 64MBytes. 433 This flag enables fast read command for AHB mode and modifies required 434 LUT to support full FlexSPI flash. 435 436config SYS_CCI400_OFFSET 437 hex "Offset for CCI400 base" 438 depends on SYS_FSL_HAS_CCI400 439 default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A 440 default 0x180000 if FSL_LSCH2 441 help 442 Offset for CCI400 base 443 CCI400 base addr = CCSRBAR + CCI400_OFFSET 444 445config SYS_FSL_IFC_BANK_COUNT 446 int "Maximum banks of Integrated flash controller" 447 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A 448 default 4 if ARCH_LS1043A 449 default 4 if ARCH_LS1046A 450 default 8 if ARCH_LS2080A || ARCH_LS1088A 451 452config SYS_FSL_HAS_CCI400 453 bool 454 455config SYS_FSL_HAS_CCN504 456 bool 457 458config SYS_FSL_HAS_CCN508 459 bool 460 461config SYS_FSL_HAS_DP_DDR 462 bool 463 464config SYS_FSL_SRDS_1 465 bool 466 467config SYS_FSL_SRDS_2 468 bool 469 470config SYS_NXP_SRDS_3 471 bool 472 473config SYS_HAS_SERDES 474 bool 475 476config FSL_TZASC_1 477 bool 478 479config FSL_TZASC_2 480 bool 481 482config FSL_TZASC_400 483 bool 484 485config FSL_TZPC_BP147 486 bool 487endmenu 488 489menu "Layerscape clock tree configuration" 490 depends on FSL_LSCH2 || FSL_LSCH3 491 492config SYS_FSL_CLK 493 bool "Enable clock tree initialization" 494 default y 495 496config CLUSTER_CLK_FREQ 497 int "Reference clock of core cluster" 498 depends on ARCH_LS1012A 499 default 100000000 500 help 501 This number is the reference clock frequency of core PLL. 502 For most platforms, the core PLL and Platform PLL have the same 503 reference clock, but for some platforms, LS1012A for instance, 504 they are provided sepatately. 505 506config SYS_FSL_PCLK_DIV 507 int "Platform clock divider" 508 default 1 if ARCH_LS1028A 509 default 1 if ARCH_LS1043A 510 default 1 if ARCH_LS1046A 511 default 1 if ARCH_LS1088A 512 default 2 513 help 514 This is the divider that is used to derive Platform clock from 515 Platform PLL, in another word: 516 Platform_clk = Platform_PLL_freq / this_divider 517 518config SYS_FSL_DSPI_CLK_DIV 519 int "DSPI clock divider" 520 default 1 if ARCH_LS1043A 521 default 2 522 help 523 This is the divider that is used to derive DSPI clock from Platform 524 clock, in another word DSPI_clk = Platform_clk / this_divider. 525 526config SYS_FSL_DUART_CLK_DIV 527 int "DUART clock divider" 528 default 1 if ARCH_LS1043A 529 default 4 if ARCH_LX2160A 530 default 4 if ARCH_LX2162A 531 default 2 532 help 533 This is the divider that is used to derive DUART clock from Platform 534 clock, in another word DUART_clk = Platform_clk / this_divider. 535 536config SYS_FSL_I2C_CLK_DIV 537 int "I2C clock divider" 538 default 1 if ARCH_LS1043A 539 default 4 if ARCH_LS1012A 540 default 4 if ARCH_LS1028A 541 default 8 if ARCH_LX2160A 542 default 8 if ARCH_LX2162A 543 default 8 if ARCH_LS1088A 544 default 2 545 help 546 This is the divider that is used to derive I2C clock from Platform 547 clock, in another word I2C_clk = Platform_clk / this_divider. 548 549config SYS_FSL_IFC_CLK_DIV 550 int "IFC clock divider" 551 default 1 if ARCH_LS1043A 552 default 4 if ARCH_LS1012A 553 default 4 if ARCH_LS1028A 554 default 8 if ARCH_LX2160A 555 default 8 if ARCH_LX2162A 556 default 8 if ARCH_LS1088A 557 default 2 558 help 559 This is the divider that is used to derive IFC clock from Platform 560 clock, in another word IFC_clk = Platform_clk / this_divider. 561 562config SYS_FSL_LPUART_CLK_DIV 563 int "LPUART clock divider" 564 default 1 if ARCH_LS1043A 565 default 2 566 help 567 This is the divider that is used to derive LPUART clock from Platform 568 clock, in another word LPUART_clk = Platform_clk / this_divider. 569 570config SYS_FSL_SDHC_CLK_DIV 571 int "SDHC clock divider" 572 default 1 if ARCH_LS1043A 573 default 1 if ARCH_LS1012A 574 default 2 575 help 576 This is the divider that is used to derive SDHC clock from Platform 577 clock, in another word SDHC_clk = Platform_clk / this_divider. 578 579config SYS_FSL_QMAN_CLK_DIV 580 int "QMAN clock divider" 581 default 1 if ARCH_LS1043A 582 default 2 583 help 584 This is the divider that is used to derive QMAN clock from Platform 585 clock, in another word QMAN_clk = Platform_clk / this_divider. 586endmenu 587 588config RESV_RAM 589 bool 590 help 591 Reserve memory from the top, tracked by gd->arch.resv_ram. This 592 reserved RAM can be used by special driver that resides in memory 593 after U-Boot exits. It's up to implementation to allocate and allow 594 access to this reserved memory. For example, the reserved RAM can 595 be at the high end of physical memory. The reserve RAM may be 596 excluded from memory bank(s) passed to OS, or marked as reserved. 597 598config SYS_FSL_EC1 599 bool 600 help 601 Ethernet controller 1, this is connected to 602 MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs 603 Provides DPAA2 capabilities 604 605config SYS_FSL_EC2 606 bool 607 help 608 Ethernet controller 2, this is connected to 609 MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs 610 Provides DPAA2 capabilities 611 612config SYS_FSL_ERRATUM_A008336 613 bool 614 615config SYS_FSL_ERRATUM_A008514 616 bool 617 618config SYS_FSL_ERRATUM_A008585 619 bool 620 621config SYS_FSL_ERRATUM_A008850 622 bool 623 624config SYS_FSL_ERRATUM_A009203 625 bool 626 627config SYS_FSL_ERRATUM_A009635 628 bool 629 630config SYS_FSL_ERRATUM_A009660 631 bool 632 633config SYS_FSL_ERRATUM_A050382 634 bool 635 636config SYS_FSL_HAS_RGMII 637 bool 638 depends on SYS_FSL_EC1 || SYS_FSL_EC2 639 640config SPL_LDSCRIPT 641 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 642 643config HAS_FSL_XHCI_USB 644 bool 645 default y if ARCH_LS1043A || ARCH_LS1046A 646 help 647 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use 648 pins, select it when the pins are assigned to USB. 649 650config SYS_FSL_BOOTROM_BASE 651 hex 652 depends on FSL_LSCH2 653 default 0 654 655config SYS_FSL_BOOTROM_SIZE 656 hex 657 depends on FSL_LSCH2 658 default 0x1000000 659