1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
5 */
6
7#include <dt-bindings/memory/stm32-sdram.h>
8/{
9	clocks {
10		u-boot,dm-pre-reloc;
11	};
12
13	aliases {
14		/* Aliases for gpios so as to use sequence */
15		gpio0 = &gpioa;
16		gpio1 = &gpiob;
17		gpio2 = &gpioc;
18		gpio3 = &gpiod;
19		gpio4 = &gpioe;
20		gpio5 = &gpiof;
21		gpio6 = &gpiog;
22		gpio7 = &gpioh;
23		gpio8 = &gpioi;
24		gpio9 = &gpioj;
25		gpio10 = &gpiok;
26		spi0 = &qspi;
27	};
28
29	soc {
30		u-boot,dm-pre-reloc;
31		pin-controller {
32			u-boot,dm-pre-reloc;
33		};
34
35		fmc: fmc@A0000000 {
36			compatible = "st,stm32-fmc";
37			reg = <0xA0000000 0x1000>;
38			clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
39			st,syscfg = <&syscfg>;
40			pinctrl-0 = <&fmc_pins_d32>;
41			pinctrl-names = "default";
42			st,mem_remap = <4>;
43			u-boot,dm-pre-reloc;
44
45			/*
46			 * Memory configuration from sdram
47			 * MICRON MT48LC4M32B2B5-6A
48			 */
49			bank0: bank@0 {
50			       st,sdram-control = /bits/ 8 <NO_COL_8
51							    NO_ROW_12
52							    MWIDTH_32
53							    BANKS_4
54							    CAS_3
55							    SDCLK_2
56							    RD_BURST_EN
57							    RD_PIPE_DL_0>;
58			       st,sdram-timing = /bits/ 8 <TMRD_2
59							   TXSR_6
60							   TRAS_4
61							   TRC_6
62							   TWR_2
63							   TRP_2
64							   TRCD_2>;
65			       st,sdram-refcount = < 1292 >;
66		       };
67		};
68
69		qspi: spi@A0001000 {
70			compatible = "st,stm32f469-qspi";
71			#address-cells = <1>;
72			#size-cells = <0>;
73			reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
74			reg-names = "qspi", "qspi_mm";
75			interrupts = <91>;
76			spi-max-frequency = <108000000>;
77			clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>;
78			resets = <&rcc STM32F4_AHB3_RESET(QSPI)>;
79			pinctrl-0 = <&qspi_pins>;
80		};
81	};
82};
83
84&clk_hse {
85	u-boot,dm-pre-reloc;
86};
87
88&clk_i2s_ckin {
89	u-boot,dm-pre-reloc;
90};
91
92&clk_lse {
93	u-boot,dm-pre-reloc;
94};
95
96&gpioa {
97	u-boot,dm-pre-reloc;
98};
99
100&gpiob {
101	u-boot,dm-pre-reloc;
102};
103
104&gpioc {
105	u-boot,dm-pre-reloc;
106};
107
108&gpiod {
109	u-boot,dm-pre-reloc;
110};
111
112&gpioe {
113	u-boot,dm-pre-reloc;
114};
115
116&gpiof {
117	u-boot,dm-pre-reloc;
118};
119
120&gpiog {
121	u-boot,dm-pre-reloc;
122};
123
124&gpioh {
125	u-boot,dm-pre-reloc;
126};
127
128&gpioi {
129	u-boot,dm-pre-reloc;
130};
131
132&gpioj {
133	u-boot,dm-pre-reloc;
134};
135
136&gpiok {
137	u-boot,dm-pre-reloc;
138};
139
140&pinctrl {
141	fmc_pins_d32: fmc_d32@0 {
142		u-boot,dm-pre-reloc;
143		pins
144		{
145			pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
146				 <STM32_PINMUX('I', 9, AF12)>, /* D30 */
147				 <STM32_PINMUX('I', 7, AF12)>, /* D29 */
148				 <STM32_PINMUX('I', 6, AF12)>, /* D28 */
149				 <STM32_PINMUX('I', 3, AF12)>, /* D27 */
150				 <STM32_PINMUX('I', 2, AF12)>, /* D26 */
151				 <STM32_PINMUX('I', 1, AF12)>, /* D25 */
152				 <STM32_PINMUX('I', 0, AF12)>, /* D24 */
153				 <STM32_PINMUX('H',15, AF12)>, /* D23 */
154				 <STM32_PINMUX('H',14, AF12)>, /* D22 */
155				 <STM32_PINMUX('H',13, AF12)>, /* D21 */
156				 <STM32_PINMUX('H',12, AF12)>, /* D20 */
157				 <STM32_PINMUX('H',11, AF12)>, /* D19 */
158				 <STM32_PINMUX('H',10, AF12)>, /* D18 */
159				 <STM32_PINMUX('H', 9, AF12)>, /* D17 */
160				 <STM32_PINMUX('H', 8, AF12)>, /* D16 */
161
162				 <STM32_PINMUX('D',10, AF12)>, /* D15 */
163				 <STM32_PINMUX('D', 9, AF12)>, /* D14 */
164				 <STM32_PINMUX('D', 8, AF12)>, /* D13 */
165				 <STM32_PINMUX('E',15, AF12)>, /* D12 */
166				 <STM32_PINMUX('E',14, AF12)>, /* D11 */
167				 <STM32_PINMUX('E',13, AF12)>, /* D10 */
168				 <STM32_PINMUX('E',12, AF12)>, /* D09 */
169				 <STM32_PINMUX('E',11, AF12)>, /* D08 */
170				 <STM32_PINMUX('E',10, AF12)>, /* D07 */
171				 <STM32_PINMUX('E', 9, AF12)>, /* D06 */
172				 <STM32_PINMUX('E', 8, AF12)>, /* D05 */
173				 <STM32_PINMUX('E', 7, AF12)>, /* D04 */
174				 <STM32_PINMUX('D', 1, AF12)>, /* D03 */
175				 <STM32_PINMUX('D', 0, AF12)>, /* D02 */
176				 <STM32_PINMUX('D',15, AF12)>, /* D01 */
177				 <STM32_PINMUX('D',14, AF12)>, /* D00 */
178
179				 <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
180				 <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
181				 <STM32_PINMUX('I', 4, AF12)>, /* NBL2 */
182				 <STM32_PINMUX('I', 5, AF12)>, /* NBL3 */
183
184				 <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
185				 <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
186
187				 <STM32_PINMUX('G', 1, AF12)>, /* A11 */
188				 <STM32_PINMUX('G', 0, AF12)>, /* A10 */
189				 <STM32_PINMUX('F',15, AF12)>, /* A09 */
190				 <STM32_PINMUX('F',14, AF12)>, /* A08 */
191				 <STM32_PINMUX('F',13, AF12)>, /* A07 */
192				 <STM32_PINMUX('F',12, AF12)>, /* A06 */
193				 <STM32_PINMUX('F', 5, AF12)>, /* A05 */
194				 <STM32_PINMUX('F', 4, AF12)>, /* A04 */
195				 <STM32_PINMUX('F', 3, AF12)>, /* A03 */
196				 <STM32_PINMUX('F', 2, AF12)>, /* A02 */
197				 <STM32_PINMUX('F', 1, AF12)>, /* A01 */
198				 <STM32_PINMUX('F', 0, AF12)>, /* A00 */
199
200				 <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
201				 <STM32_PINMUX('C', 0, AF12)>, /* SDNWE */
202				 <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
203				 <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
204				 <STM32_PINMUX('H', 2, AF12)>, /* SDCKE0 */
205				 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
206			slew-rate = <2>;
207			u-boot,dm-pre-reloc;
208		};
209	};
210
211	qspi_pins: qspi@0 {
212		pins {
213			pinmux = <STM32_PINMUX('F',10, AF9)>, /* CLK */
214				 <STM32_PINMUX('B', 6, AF10)>, /* BK1_NCS */
215				 <STM32_PINMUX('F', 8, AF10)>, /* BK1_IO0 */
216				 <STM32_PINMUX('F', 9, AF10)>, /* BK1_IO1 */
217				 <STM32_PINMUX('F', 7, AF9)>, /* BK1_IO2 */
218				 <STM32_PINMUX('F', 6, AF9)>; /* BK1_IO3 */
219			slew-rate = <2>;
220		};
221	};
222
223	usart3_pins_a: usart3-0	{
224		u-boot,dm-pre-reloc;
225		pins1 {
226			u-boot,dm-pre-reloc;
227		};
228		pins2 {
229			u-boot,dm-pre-reloc;
230		};
231	};
232};
233
234&pwrcfg {
235	u-boot,dm-pre-reloc;
236};
237
238&qspi {
239	reg = <0xA0001000 0x1000>, <0x90000000 0x1000000>;
240	flash0: n25q128a@0 {
241		#address-cells = <1>;
242		#size-cells = <1>;
243		compatible = "jedec,spi-nor";
244		spi-max-frequency = <108000000>;
245		spi-tx-bus-width = <4>;
246		spi-rx-bus-width = <4>;
247		reg = <0>;
248	};
249};
250
251&rcc {
252	u-boot,dm-pre-reloc;
253};
254
255&syscfg {
256	u-boot,dm-pre-reloc;
257};
258
259&timer5 {
260	u-boot,dm-pre-reloc;
261};
262