1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 *
5 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 */
7
8 #include <init.h>
9 #include <net.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/global_data.h>
17 #include <asm/gpio.h>
18 #include <asm/mach-imx/iomux-v3.h>
19 #include <asm/io.h>
20 #include <asm/mach-imx/mxc_i2c.h>
21 #include <env.h>
22 #include <linux/delay.h>
23 #include <linux/sizes.h>
24 #include <common.h>
25 #include <fsl_esdhc_imx.h>
26 #include <mmc.h>
27 #include <i2c.h>
28 #include <miiphy.h>
29 #include <netdev.h>
30 #include <power/pmic.h>
31 #include <power/pfuze100_pmic.h>
32 #include "../common/pfuze.h"
33
34 DECLARE_GLOBAL_DATA_PTR;
35
36 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
37 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
38 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
39
40 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
41 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
42 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
43
44 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
45 PAD_CTL_SPEED_HIGH | \
46 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
47
48 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
49 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
50
51 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
52 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
53
54 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
55 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
56
57 #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
58 PAD_CTL_DSE_40ohm)
59
dram_init(void)60 int dram_init(void)
61 {
62 gd->ram_size = imx_ddr_size();
63
64 return 0;
65 }
66
67 static iomux_v3_cfg_t const uart1_pads[] = {
68 MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
69 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
70 };
71
72 static iomux_v3_cfg_t const wdog_b_pad = {
73 MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
74 };
75 static iomux_v3_cfg_t const fec1_pads[] = {
76 MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
77 MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
78 MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
79 MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
80 MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
81 MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
82 MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
83 MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
84 MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
85 MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
86 MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
87 MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
88 MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
89 MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
90 };
91
92 static iomux_v3_cfg_t const peri_3v3_pads[] = {
93 MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
94 };
95
96 static iomux_v3_cfg_t const phy_control_pads[] = {
97 /* 25MHz Ethernet PHY Clock */
98 MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
99
100 /* ENET PHY Power */
101 MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL),
102
103 /* AR8031 PHY Reset */
104 MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
105 };
106
setup_iomux_uart(void)107 static void setup_iomux_uart(void)
108 {
109 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
110 }
111
setup_fec(void)112 static int setup_fec(void)
113 {
114 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
115 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
116 int reg, ret;
117
118 /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
119 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
120
121 ret = enable_fec_anatop_clock(0, ENET_125MHZ);
122 if (ret)
123 return ret;
124
125 imx_iomux_v3_setup_multiple_pads(phy_control_pads,
126 ARRAY_SIZE(phy_control_pads));
127
128 /* Enable the ENET power, active low */
129 gpio_request(IMX_GPIO_NR(2, 6), "enet_rst");
130 gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
131
132 /* Reset AR8031 PHY */
133 gpio_request(IMX_GPIO_NR(2, 7), "phy_rst");
134 gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
135 mdelay(10);
136 gpio_set_value(IMX_GPIO_NR(2, 7), 1);
137
138 reg = readl(&anatop->pll_enet);
139 reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
140 writel(reg, &anatop->pll_enet);
141
142 return 0;
143 }
144
board_eth_init(struct bd_info * bis)145 int board_eth_init(struct bd_info *bis)
146 {
147 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
148 setup_fec();
149
150 return cpu_eth_init(bis);
151 }
152
power_init_board(void)153 int power_init_board(void)
154 {
155 struct udevice *dev;
156 unsigned int reg;
157 int ret;
158
159 dev = pfuze_common_init();
160 if (!dev)
161 return -ENODEV;
162
163 ret = pfuze_mode_init(dev, APS_PFM);
164 if (ret < 0)
165 return ret;
166
167 /* Enable power of VGEN5 3V3, needed for SD3 */
168 reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
169 reg &= ~LDO_VOL_MASK;
170 reg |= (LDOB_3_30V | (1 << LDO_EN));
171 pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
172
173 return 0;
174 }
175
board_phy_config(struct phy_device * phydev)176 int board_phy_config(struct phy_device *phydev)
177 {
178 /*
179 * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
180 * Phy control debug reg 0
181 */
182 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
183 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
184
185 /* rgmii tx clock delay enable */
186 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
187 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
188
189 if (phydev->drv->config)
190 phydev->drv->config(phydev);
191
192 return 0;
193 }
194
board_early_init_f(void)195 int board_early_init_f(void)
196 {
197 setup_iomux_uart();
198
199 /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
200 imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
201 ARRAY_SIZE(peri_3v3_pads));
202
203 return 0;
204 }
205
board_mmc_get_env_dev(int devno)206 int board_mmc_get_env_dev(int devno)
207 {
208 return devno;
209 }
210
211 #ifdef CONFIG_FSL_QSPI
212
board_qspi_init(void)213 int board_qspi_init(void)
214 {
215 /* Set the clock */
216 enable_qspi_clk(1);
217
218 return 0;
219 }
220 #endif
221
222 #ifdef CONFIG_VIDEO_MXS
223 static iomux_v3_cfg_t const lcd_pads[] = {
224 MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
225 MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
226 MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
227 MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
228 MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
229 MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
230 MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
231 MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
232 MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
233 MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
234 MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
235 MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
236 MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
237 MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
238 MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
239 MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
240 MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
241 MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
242 MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
243 MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
244 MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
245 MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
246 MX6_PAD_LCD1_DATA18__LCDIF1_DATA_18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
247 MX6_PAD_LCD1_DATA19__LCDIF1_DATA_19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
248 MX6_PAD_LCD1_DATA20__LCDIF1_DATA_20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
249 MX6_PAD_LCD1_DATA21__LCDIF1_DATA_21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
250 MX6_PAD_LCD1_DATA22__LCDIF1_DATA_22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
251 MX6_PAD_LCD1_DATA23__LCDIF1_DATA_23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
252 MX6_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
253
254 /* Use GPIO for Brightness adjustment, duty cycle = period */
255 MX6_PAD_SD1_DATA2__GPIO6_IO_4 | MUX_PAD_CTRL(NO_PAD_CTRL),
256 };
257
setup_lcd(void)258 static int setup_lcd(void)
259 {
260 enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
261
262 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
263
264 /* Reset the LCD */
265 gpio_request(IMX_GPIO_NR(3, 27), "lcd_rst");
266 gpio_direction_output(IMX_GPIO_NR(3, 27) , 0);
267 udelay(500);
268 gpio_direction_output(IMX_GPIO_NR(3, 27) , 1);
269
270 /* Set Brightness to high */
271 gpio_request(IMX_GPIO_NR(6, 4), "lcd_bright");
272 gpio_direction_output(IMX_GPIO_NR(6, 4) , 1);
273
274 return 0;
275 }
276 #endif
277
board_init(void)278 int board_init(void)
279 {
280 /* Address of boot parameters */
281 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
282
283 /*
284 * Because kernel set WDOG_B mux before pad with the common pinctrl
285 * framwork now and wdog reset will be triggered once set WDOG_B mux
286 * with default pad setting, we set pad setting here to workaround this.
287 * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
288 * as GPIO mux firstly here to workaround it.
289 */
290 imx_iomux_v3_setup_pad(wdog_b_pad);
291
292 /* Active high for ncp692 */
293 gpio_request(IMX_GPIO_NR(4, 16), "ncp692_en");
294 gpio_direction_output(IMX_GPIO_NR(4, 16), 1);
295
296 #ifdef CONFIG_FSL_QSPI
297 board_qspi_init();
298 #endif
299
300 #ifdef CONFIG_VIDEO_MXS
301 setup_lcd();
302 #endif
303
304 return 0;
305 }
306
is_reva(void)307 static bool is_reva(void)
308 {
309 return (nxp_board_rev() == 1);
310 }
311
board_late_init(void)312 int board_late_init(void)
313 {
314 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
315 if (is_reva())
316 env_set("board_rev", "REVA");
317 #endif
318 return 0;
319 }
320
checkboard(void)321 int checkboard(void)
322 {
323 printf("Board: MX6SX SABRE SDB rev%c\n", nxp_board_rev_string());
324
325 return 0;
326 }
327