1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A77970 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2016 Renesas Electronics Corp.
6 * Copyright (C) 2017 Cogent Embedded, Inc. <source@cogentembedded.com>
7 *
8 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
9 *
10 * R-Car Gen3 processor support - PFC hardware block.
11 *
12 * Copyright (C) 2015 Renesas Electronics Corporation
13 */
14
15 #include <common.h>
16 #include <dm.h>
17 #include <errno.h>
18 #include <dm/pinctrl.h>
19 #include <linux/kernel.h>
20
21 #include "sh_pfc.h"
22
23 #define CPU_ALL_GP(fn, sfx) \
24 PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
25 PORT_GP_28(1, fn, sfx), \
26 PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
27 PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
28 PORT_GP_6(4, fn, sfx), \
29 PORT_GP_15(5, fn, sfx)
30 /*
31 * F_() : just information
32 * FM() : macro for FN_xxx / xxx_MARK
33 */
34
35 /* GPSR0 */
36 #define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20)
37 #define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16)
38 #define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12)
39 #define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8)
40 #define GPSR0_17 F_(DU_DB7, IP2_7_4)
41 #define GPSR0_16 F_(DU_DB6, IP2_3_0)
42 #define GPSR0_15 F_(DU_DB5, IP1_31_28)
43 #define GPSR0_14 F_(DU_DB4, IP1_27_24)
44 #define GPSR0_13 F_(DU_DB3, IP1_23_20)
45 #define GPSR0_12 F_(DU_DB2, IP1_19_16)
46 #define GPSR0_11 F_(DU_DG7, IP1_15_12)
47 #define GPSR0_10 F_(DU_DG6, IP1_11_8)
48 #define GPSR0_9 F_(DU_DG5, IP1_7_4)
49 #define GPSR0_8 F_(DU_DG4, IP1_3_0)
50 #define GPSR0_7 F_(DU_DG3, IP0_31_28)
51 #define GPSR0_6 F_(DU_DG2, IP0_27_24)
52 #define GPSR0_5 F_(DU_DR7, IP0_23_20)
53 #define GPSR0_4 F_(DU_DR6, IP0_19_16)
54 #define GPSR0_3 F_(DU_DR5, IP0_15_12)
55 #define GPSR0_2 F_(DU_DR4, IP0_11_8)
56 #define GPSR0_1 F_(DU_DR3, IP0_7_4)
57 #define GPSR0_0 F_(DU_DR2, IP0_3_0)
58
59 /* GPSR1 */
60 #define GPSR1_27 F_(DIGRF_CLKOUT, IP8_27_24)
61 #define GPSR1_26 F_(DIGRF_CLKIN, IP8_23_20)
62 #define GPSR1_25 F_(CANFD_CLK_A, IP8_19_16)
63 #define GPSR1_24 F_(CANFD1_RX, IP8_15_12)
64 #define GPSR1_23 F_(CANFD1_TX, IP8_11_8)
65 #define GPSR1_22 F_(CANFD0_RX_A, IP8_7_4)
66 #define GPSR1_21 F_(CANFD0_TX_A, IP8_3_0)
67 #define GPSR1_20 F_(AVB0_AVTP_CAPTURE, IP7_31_28)
68 #define GPSR1_19 FM(AVB0_AVTP_MATCH)
69 #define GPSR1_18 FM(AVB0_LINK)
70 #define GPSR1_17 FM(AVB0_PHY_INT)
71 #define GPSR1_16 FM(AVB0_MAGIC)
72 #define GPSR1_15 FM(AVB0_MDC)
73 #define GPSR1_14 FM(AVB0_MDIO)
74 #define GPSR1_13 FM(AVB0_TXCREFCLK)
75 #define GPSR1_12 FM(AVB0_TD3)
76 #define GPSR1_11 FM(AVB0_TD2)
77 #define GPSR1_10 FM(AVB0_TD1)
78 #define GPSR1_9 FM(AVB0_TD0)
79 #define GPSR1_8 FM(AVB0_TXC)
80 #define GPSR1_7 FM(AVB0_TX_CTL)
81 #define GPSR1_6 FM(AVB0_RD3)
82 #define GPSR1_5 FM(AVB0_RD2)
83 #define GPSR1_4 FM(AVB0_RD1)
84 #define GPSR1_3 FM(AVB0_RD0)
85 #define GPSR1_2 FM(AVB0_RXC)
86 #define GPSR1_1 FM(AVB0_RX_CTL)
87 #define GPSR1_0 F_(IRQ0, IP2_27_24)
88
89 /* GPSR2 */
90 #define GPSR2_16 F_(VI0_FIELD, IP4_31_28)
91 #define GPSR2_15 F_(VI0_DATA11, IP4_27_24)
92 #define GPSR2_14 F_(VI0_DATA10, IP4_23_20)
93 #define GPSR2_13 F_(VI0_DATA9, IP4_19_16)
94 #define GPSR2_12 F_(VI0_DATA8, IP4_15_12)
95 #define GPSR2_11 F_(VI0_DATA7, IP4_11_8)
96 #define GPSR2_10 F_(VI0_DATA6, IP4_7_4)
97 #define GPSR2_9 F_(VI0_DATA5, IP4_3_0)
98 #define GPSR2_8 F_(VI0_DATA4, IP3_31_28)
99 #define GPSR2_7 F_(VI0_DATA3, IP3_27_24)
100 #define GPSR2_6 F_(VI0_DATA2, IP3_23_20)
101 #define GPSR2_5 F_(VI0_DATA1, IP3_19_16)
102 #define GPSR2_4 F_(VI0_DATA0, IP3_15_12)
103 #define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8)
104 #define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4)
105 #define GPSR2_1 F_(VI0_CLKENB, IP3_3_0)
106 #define GPSR2_0 F_(VI0_CLK, IP2_31_28)
107
108 /* GPSR3 */
109 #define GPSR3_16 F_(VI1_FIELD, IP7_3_0)
110 #define GPSR3_15 F_(VI1_DATA11, IP6_31_28)
111 #define GPSR3_14 F_(VI1_DATA10, IP6_27_24)
112 #define GPSR3_13 F_(VI1_DATA9, IP6_23_20)
113 #define GPSR3_12 F_(VI1_DATA8, IP6_19_16)
114 #define GPSR3_11 F_(VI1_DATA7, IP6_15_12)
115 #define GPSR3_10 F_(VI1_DATA6, IP6_11_8)
116 #define GPSR3_9 F_(VI1_DATA5, IP6_7_4)
117 #define GPSR3_8 F_(VI1_DATA4, IP6_3_0)
118 #define GPSR3_7 F_(VI1_DATA3, IP5_31_28)
119 #define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
120 #define GPSR3_5 F_(VI1_DATA1, IP5_23_20)
121 #define GPSR3_4 F_(VI1_DATA0, IP5_19_16)
122 #define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12)
123 #define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8)
124 #define GPSR3_1 F_(VI1_CLKENB, IP5_7_4)
125 #define GPSR3_0 F_(VI1_CLK, IP5_3_0)
126
127 /* GPSR4 */
128 #define GPSR4_5 F_(SDA2, IP7_27_24)
129 #define GPSR4_4 F_(SCL2, IP7_23_20)
130 #define GPSR4_3 F_(SDA1, IP7_19_16)
131 #define GPSR4_2 F_(SCL1, IP7_15_12)
132 #define GPSR4_1 F_(SDA0, IP7_11_8)
133 #define GPSR4_0 F_(SCL0, IP7_7_4)
134
135 /* GPSR5 */
136 #define GPSR5_14 FM(RPC_INT_N)
137 #define GPSR5_13 FM(RPC_WP_N)
138 #define GPSR5_12 FM(RPC_RESET_N)
139 #define GPSR5_11 FM(QSPI1_SSL)
140 #define GPSR5_10 FM(QSPI1_IO3)
141 #define GPSR5_9 FM(QSPI1_IO2)
142 #define GPSR5_8 FM(QSPI1_MISO_IO1)
143 #define GPSR5_7 FM(QSPI1_MOSI_IO0)
144 #define GPSR5_6 FM(QSPI1_SPCLK)
145 #define GPSR5_5 FM(QSPI0_SSL)
146 #define GPSR5_4 FM(QSPI0_IO3)
147 #define GPSR5_3 FM(QSPI0_IO2)
148 #define GPSR5_2 FM(QSPI0_MISO_IO1)
149 #define GPSR5_1 FM(QSPI0_MOSI_IO0)
150 #define GPSR5_0 FM(QSPI0_SPCLK)
151
152
153 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
154 #define IP0_3_0 FM(DU_DR2) FM(HSCK0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
155 #define IP0_7_4 FM(DU_DR3) FM(HRTS0_N) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
156 #define IP0_11_8 FM(DU_DR4) FM(HCTS0_N) F_(0, 0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
157 #define IP0_15_12 FM(DU_DR5) FM(HTX0) F_(0, 0) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
158 #define IP0_19_16 FM(DU_DR6) FM(MSIOF3_RXD) F_(0, 0) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
159 #define IP0_23_20 FM(DU_DR7) FM(MSIOF3_TXD) F_(0, 0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
160 #define IP0_27_24 FM(DU_DG2) FM(MSIOF3_SS1) F_(0, 0) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
161 #define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
162 #define IP1_3_0 FM(DU_DG4) F_(0, 0) F_(0, 0) FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
163 #define IP1_7_4 FM(DU_DG5) F_(0, 0) F_(0, 0) FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
164 #define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
165 #define IP1_15_12 FM(DU_DG7) F_(0, 0) F_(0, 0) FM(A11) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
166 #define IP1_19_16 FM(DU_DB2) F_(0, 0) F_(0, 0) FM(A12) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
167 #define IP1_23_20 FM(DU_DB3) F_(0, 0) F_(0, 0) FM(A13) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
168 #define IP1_27_24 FM(DU_DB4) F_(0, 0) F_(0, 0) FM(A14) FM(FXR_CLKOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
169 #define IP1_31_28 FM(DU_DB5) F_(0, 0) F_(0, 0) FM(A15) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
170 #define IP2_3_0 FM(DU_DB6) F_(0, 0) F_(0, 0) FM(A16) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
171 #define IP2_7_4 FM(DU_DB7) F_(0, 0) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
172 #define IP2_11_8 FM(DU_DOTCLKOUT) FM(SCIF_CLK_A) F_(0, 0) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
173 #define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(HRX0) F_(0, 0) FM(A19) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
174 #define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
175 #define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
176 #define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
177 #define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
178 #define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
179 #define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
180 #define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
181 #define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
182 #define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
183 #define IP3_23_20 FM(VI0_DATA2) FM(AVB0_AVTP_PPS) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
184 #define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
185 #define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
186 #define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
187 #define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
188 #define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
189 #define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) FM(PWM0_A) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
190 #define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) FM(A23) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
191 #define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) FM(A24) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
192 #define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) FM(A25) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
193 #define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
194 #define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
195 #define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
196 #define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
197 #define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
198 #define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
199 #define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
200 #define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
201 #define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
202 #define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
203 #define IP6_7_4 FM(VI1_DATA5) F_(0, 0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204 #define IP6_11_8 FM(VI1_DATA6) F_(0, 0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205 #define IP6_15_12 FM(VI1_DATA7) F_(0, 0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206 #define IP6_19_16 FM(VI1_DATA8) F_(0, 0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207 #define IP6_23_20 FM(VI1_DATA9) F_(0, 0) FM(RTS4_N) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208 #define IP6_27_24 FM(VI1_DATA10) F_(0, 0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209 #define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210 #define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211 #define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212 #define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213 #define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214 #define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP7_23_20 FM(SCL2) FM(DU_DB0) FM(TCLK1_A) FM(WE1_N) FM(RX0) FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP7_27_24 FM(SDA2) FM(DU_DB1) FM(TCLK2_A) FM(EX_WAIT0) FM(TX0) FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP7_31_28 FM(AVB0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSCLKST2_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP8_3_0 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) FM(FSCLKST2_N_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP8_7_4 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP8_11_8 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP8_15_12 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP8_19_16 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP8_23_20 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP8_27_24 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP8_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226
227 #define PINMUX_GPSR \
228 \
229 GPSR1_27 \
230 GPSR1_26 \
231 GPSR1_25 \
232 GPSR1_24 \
233 GPSR1_23 \
234 GPSR1_22 \
235 GPSR0_21 GPSR1_21 \
236 GPSR0_20 GPSR1_20 \
237 GPSR0_19 GPSR1_19 \
238 GPSR0_18 GPSR1_18 \
239 GPSR0_17 GPSR1_17 \
240 GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 \
241 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 \
242 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 \
243 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 \
244 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 \
245 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 \
246 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR5_10 \
247 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR5_9 \
248 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR5_8 \
249 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR5_7 \
250 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR5_6 \
251 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 \
252 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 \
253 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 \
254 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 \
255 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 \
256 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0
257
258 #define PINMUX_IPSR \
259 \
260 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
261 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
262 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
263 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
264 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
265 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
266 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
267 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
268 \
269 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
270 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
271 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
272 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
273 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
274 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
275 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
276 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
277 \
278 FM(IP8_3_0) IP8_3_0 \
279 FM(IP8_7_4) IP8_7_4 \
280 FM(IP8_11_8) IP8_11_8 \
281 FM(IP8_15_12) IP8_15_12 \
282 FM(IP8_19_16) IP8_19_16 \
283 FM(IP8_23_20) IP8_23_20 \
284 FM(IP8_27_24) IP8_27_24 \
285 FM(IP8_31_28) IP8_31_28
286
287 /* MOD_SEL0 */ /* 0 */ /* 1 */
288 #define MOD_SEL0_11 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
289 #define MOD_SEL0_10 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
290 #define MOD_SEL0_9 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
291 #define MOD_SEL0_8 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
292 #define MOD_SEL0_7 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
293 #define MOD_SEL0_6 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
294 #define MOD_SEL0_5 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
295 #define MOD_SEL0_4 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
296 #define MOD_SEL0_3 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
297 #define MOD_SEL0_2 FM(SEL_RFSO_0) FM(SEL_RFSO_1)
298 #define MOD_SEL0_1 FM(SEL_RSP_0) FM(SEL_RSP_1)
299 #define MOD_SEL0_0 FM(SEL_TMU_0) FM(SEL_TMU_1)
300
301 #define PINMUX_MOD_SELS \
302 \
303 MOD_SEL0_11 \
304 MOD_SEL0_10 \
305 MOD_SEL0_9 \
306 MOD_SEL0_8 \
307 MOD_SEL0_7 \
308 MOD_SEL0_6 \
309 MOD_SEL0_5 \
310 MOD_SEL0_4 \
311 MOD_SEL0_3 \
312 MOD_SEL0_2 \
313 MOD_SEL0_1 \
314 MOD_SEL0_0
315
316 enum {
317 PINMUX_RESERVED = 0,
318
319 PINMUX_DATA_BEGIN,
320 GP_ALL(DATA),
321 PINMUX_DATA_END,
322
323 #define F_(x, y)
324 #define FM(x) FN_##x,
325 PINMUX_FUNCTION_BEGIN,
326 GP_ALL(FN),
327 PINMUX_GPSR
328 PINMUX_IPSR
329 PINMUX_MOD_SELS
330 PINMUX_FUNCTION_END,
331 #undef F_
332 #undef FM
333
334 #define F_(x, y)
335 #define FM(x) x##_MARK,
336 PINMUX_MARK_BEGIN,
337 PINMUX_GPSR
338 PINMUX_IPSR
339 PINMUX_MOD_SELS
340 PINMUX_MARK_END,
341 #undef F_
342 #undef FM
343 };
344
345 static const u16 pinmux_data[] = {
346 PINMUX_DATA_GP_ALL(),
347
348 PINMUX_SINGLE(AVB0_RX_CTL),
349 PINMUX_SINGLE(AVB0_RXC),
350 PINMUX_SINGLE(AVB0_RD0),
351 PINMUX_SINGLE(AVB0_RD1),
352 PINMUX_SINGLE(AVB0_RD2),
353 PINMUX_SINGLE(AVB0_RD3),
354 PINMUX_SINGLE(AVB0_TX_CTL),
355 PINMUX_SINGLE(AVB0_TXC),
356 PINMUX_SINGLE(AVB0_TD0),
357 PINMUX_SINGLE(AVB0_TD1),
358 PINMUX_SINGLE(AVB0_TD2),
359 PINMUX_SINGLE(AVB0_TD3),
360 PINMUX_SINGLE(AVB0_TXCREFCLK),
361 PINMUX_SINGLE(AVB0_MDIO),
362 PINMUX_SINGLE(AVB0_MDC),
363 PINMUX_SINGLE(AVB0_MAGIC),
364 PINMUX_SINGLE(AVB0_PHY_INT),
365 PINMUX_SINGLE(AVB0_LINK),
366 PINMUX_SINGLE(AVB0_AVTP_MATCH),
367
368 PINMUX_SINGLE(QSPI0_SPCLK),
369 PINMUX_SINGLE(QSPI0_MOSI_IO0),
370 PINMUX_SINGLE(QSPI0_MISO_IO1),
371 PINMUX_SINGLE(QSPI0_IO2),
372 PINMUX_SINGLE(QSPI0_IO3),
373 PINMUX_SINGLE(QSPI0_SSL),
374 PINMUX_SINGLE(QSPI1_SPCLK),
375 PINMUX_SINGLE(QSPI1_MOSI_IO0),
376 PINMUX_SINGLE(QSPI1_MISO_IO1),
377 PINMUX_SINGLE(QSPI1_IO2),
378 PINMUX_SINGLE(QSPI1_IO3),
379 PINMUX_SINGLE(QSPI1_SSL),
380 PINMUX_SINGLE(RPC_RESET_N),
381 PINMUX_SINGLE(RPC_WP_N),
382 PINMUX_SINGLE(RPC_INT_N),
383
384 /* IPSR0 */
385 PINMUX_IPSR_GPSR(IP0_3_0, DU_DR2),
386 PINMUX_IPSR_GPSR(IP0_3_0, HSCK0),
387 PINMUX_IPSR_GPSR(IP0_3_0, A0),
388
389 PINMUX_IPSR_GPSR(IP0_7_4, DU_DR3),
390 PINMUX_IPSR_GPSR(IP0_7_4, HRTS0_N),
391 PINMUX_IPSR_GPSR(IP0_7_4, A1),
392
393 PINMUX_IPSR_GPSR(IP0_11_8, DU_DR4),
394 PINMUX_IPSR_GPSR(IP0_11_8, HCTS0_N),
395 PINMUX_IPSR_GPSR(IP0_11_8, A2),
396
397 PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5),
398 PINMUX_IPSR_GPSR(IP0_15_12, HTX0),
399 PINMUX_IPSR_GPSR(IP0_15_12, A3),
400
401 PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6),
402 PINMUX_IPSR_GPSR(IP0_19_16, MSIOF3_RXD),
403 PINMUX_IPSR_GPSR(IP0_19_16, A4),
404
405 PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7),
406 PINMUX_IPSR_GPSR(IP0_23_20, MSIOF3_TXD),
407 PINMUX_IPSR_GPSR(IP0_23_20, A5),
408
409 PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2),
410 PINMUX_IPSR_GPSR(IP0_27_24, MSIOF3_SS1),
411 PINMUX_IPSR_GPSR(IP0_27_24, A6),
412
413 PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
414 PINMUX_IPSR_GPSR(IP0_31_28, MSIOF3_SS2),
415 PINMUX_IPSR_GPSR(IP0_31_28, A7),
416 PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
417
418 /* IPSR1 */
419 PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4),
420 PINMUX_IPSR_GPSR(IP1_3_0, A8),
421 PINMUX_IPSR_MSEL(IP1_3_0, FSO_CFE_0_N_A, SEL_RFSO_0),
422
423 PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5),
424 PINMUX_IPSR_GPSR(IP1_7_4, A9),
425 PINMUX_IPSR_MSEL(IP1_7_4, FSO_CFE_1_N_A, SEL_RFSO_0),
426
427 PINMUX_IPSR_GPSR(IP1_11_8, DU_DG6),
428 PINMUX_IPSR_GPSR(IP1_11_8, A10),
429 PINMUX_IPSR_MSEL(IP1_11_8, FSO_TOE_N_A, SEL_RFSO_0),
430
431 PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
432 PINMUX_IPSR_GPSR(IP1_15_12, A11),
433 PINMUX_IPSR_GPSR(IP1_15_12, IRQ1),
434
435 PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2),
436 PINMUX_IPSR_GPSR(IP1_19_16, A12),
437 PINMUX_IPSR_GPSR(IP1_19_16, IRQ2),
438
439 PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3),
440 PINMUX_IPSR_GPSR(IP1_23_20, A13),
441 PINMUX_IPSR_GPSR(IP1_23_20, FXR_CLKOUT1),
442
443 PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4),
444 PINMUX_IPSR_GPSR(IP1_27_24, A14),
445 PINMUX_IPSR_GPSR(IP1_27_24, FXR_CLKOUT2),
446
447 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5),
448 PINMUX_IPSR_GPSR(IP1_31_28, A15),
449 PINMUX_IPSR_GPSR(IP1_31_28, FXR_TXENA_N),
450
451 /* IPSR2 */
452 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB6),
453 PINMUX_IPSR_GPSR(IP2_3_0, A16),
454 PINMUX_IPSR_GPSR(IP2_3_0, FXR_TXENB_N),
455
456 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7),
457 PINMUX_IPSR_GPSR(IP2_7_4, A17),
458
459 PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT),
460 PINMUX_IPSR_MSEL(IP2_11_8, SCIF_CLK_A, SEL_HSCIF0_0),
461 PINMUX_IPSR_GPSR(IP2_11_8, A18),
462
463 PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC),
464 PINMUX_IPSR_GPSR(IP2_15_12, HRX0),
465 PINMUX_IPSR_GPSR(IP2_15_12, A19),
466 PINMUX_IPSR_GPSR(IP2_15_12, IRQ3),
467
468 PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC),
469 PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK),
470
471 PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE),
472 PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
473
474 PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
475
476 PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
477 PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
478 PINMUX_IPSR_GPSR(IP2_31_28, SCK3),
479 PINMUX_IPSR_GPSR(IP2_31_28, HSCK3),
480
481 /* IPSR3 */
482 PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB),
483 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD),
484 PINMUX_IPSR_GPSR(IP3_3_0, RX3),
485 PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N),
486 PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N),
487
488 PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N),
489 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
490 PINMUX_IPSR_GPSR(IP3_7_4, TX3),
491 PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N),
492
493 PINMUX_IPSR_GPSR(IP3_11_8, VI0_VSYNC_N),
494 PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_SYNC),
495 PINMUX_IPSR_GPSR(IP3_11_8, CTS3_N),
496 PINMUX_IPSR_GPSR(IP3_11_8, HTX3),
497
498 PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
499 PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
500 PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N),
501 PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
502
503 PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
504 PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2),
505 PINMUX_IPSR_GPSR(IP3_19_16, SCK1),
506 PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0),
507
508 PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2),
509 PINMUX_IPSR_GPSR(IP3_23_20, AVB0_AVTP_PPS),
510 PINMUX_IPSR_MSEL(IP3_23_20, SDA3_A, SEL_I2C3_0),
511
512 PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3),
513 PINMUX_IPSR_GPSR(IP3_27_24, HSCK1),
514 PINMUX_IPSR_MSEL(IP3_27_24, SCL3_A, SEL_I2C3_0),
515
516 PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4),
517 PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N),
518 PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0),
519
520 /* IPSR4 */
521 PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5),
522 PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N),
523 PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0),
524
525 PINMUX_IPSR_GPSR(IP4_7_4, VI0_DATA6),
526 PINMUX_IPSR_GPSR(IP4_7_4, HTX1),
527 PINMUX_IPSR_GPSR(IP4_7_4, CTS1_N),
528
529 PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7),
530 PINMUX_IPSR_GPSR(IP4_11_8, HRX1),
531 PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N),
532
533 PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
534 PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
535 PINMUX_IPSR_MSEL(IP4_15_12, PWM0_A, SEL_PWM0_0),
536
537 PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9),
538 PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N),
539 PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0),
540 PINMUX_IPSR_MSEL(IP4_19_16, FSO_CFE_0_N_B, SEL_RFSO_1),
541
542 PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10),
543 PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N),
544 PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0),
545 PINMUX_IPSR_MSEL(IP4_23_20, FSO_CFE_1_N_B, SEL_RFSO_1),
546
547 PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11),
548 PINMUX_IPSR_GPSR(IP4_27_24, HTX2),
549 PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0),
550 PINMUX_IPSR_MSEL(IP4_27_24, FSO_TOE_N_B, SEL_RFSO_1),
551
552 PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD),
553 PINMUX_IPSR_GPSR(IP4_31_28, HRX2),
554 PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0),
555 PINMUX_IPSR_GPSR(IP4_31_28, CS1_N),
556 PINMUX_IPSR_GPSR(IP4_31_28, FSCLKST2_N_A),
557
558 /* IPSR5 */
559 PINMUX_IPSR_GPSR(IP5_3_0, VI1_CLK),
560 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
561 PINMUX_IPSR_GPSR(IP5_3_0, CS0_N),
562
563 PINMUX_IPSR_GPSR(IP5_7_4, VI1_CLKENB),
564 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
565 PINMUX_IPSR_GPSR(IP5_7_4, D0),
566
567 PINMUX_IPSR_GPSR(IP5_11_8, VI1_HSYNC_N),
568 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
569 PINMUX_IPSR_GPSR(IP5_11_8, D1),
570
571 PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N),
572 PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC),
573 PINMUX_IPSR_GPSR(IP5_15_12, D2),
574
575 PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0),
576 PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1),
577 PINMUX_IPSR_GPSR(IP5_19_16, D3),
578
579 PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1),
580 PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2),
581 PINMUX_IPSR_GPSR(IP5_23_20, D4),
582 PINMUX_IPSR_GPSR(IP5_23_20, MMC_CMD),
583
584 PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
585 PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
586 PINMUX_IPSR_GPSR(IP5_27_24, D5),
587 PINMUX_IPSR_GPSR(IP5_27_24, MMC_D0),
588
589 PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3),
590 PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1),
591 PINMUX_IPSR_GPSR(IP5_31_28, D6),
592 PINMUX_IPSR_GPSR(IP5_31_28, MMC_D1),
593
594 /* IPSR6 */
595 PINMUX_IPSR_GPSR(IP6_3_0, VI1_DATA4),
596 PINMUX_IPSR_MSEL(IP6_3_0, CANFD_CLK_B, SEL_CANFD0_1),
597 PINMUX_IPSR_GPSR(IP6_3_0, D7),
598 PINMUX_IPSR_GPSR(IP6_3_0, MMC_D2),
599
600 PINMUX_IPSR_GPSR(IP6_7_4, VI1_DATA5),
601 PINMUX_IPSR_GPSR(IP6_7_4, SCK4),
602 PINMUX_IPSR_GPSR(IP6_7_4, D8),
603 PINMUX_IPSR_GPSR(IP6_7_4, MMC_D3),
604
605 PINMUX_IPSR_GPSR(IP6_11_8, VI1_DATA6),
606 PINMUX_IPSR_GPSR(IP6_11_8, RX4),
607 PINMUX_IPSR_GPSR(IP6_11_8, D9),
608 PINMUX_IPSR_GPSR(IP6_11_8, MMC_CLK),
609
610 PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7),
611 PINMUX_IPSR_GPSR(IP6_15_12, TX4),
612 PINMUX_IPSR_GPSR(IP6_15_12, D10),
613 PINMUX_IPSR_GPSR(IP6_15_12, MMC_D4),
614
615 PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8),
616 PINMUX_IPSR_GPSR(IP6_19_16, CTS4_N),
617 PINMUX_IPSR_GPSR(IP6_19_16, D11),
618 PINMUX_IPSR_GPSR(IP6_19_16, MMC_D5),
619
620 PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9),
621 PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N),
622 PINMUX_IPSR_GPSR(IP6_23_20, D12),
623 PINMUX_IPSR_GPSR(IP6_23_20, MMC_D6),
624 PINMUX_IPSR_MSEL(IP6_23_20, SCL3_B, SEL_I2C3_1),
625
626 PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10),
627 PINMUX_IPSR_GPSR(IP6_27_24, D13),
628 PINMUX_IPSR_GPSR(IP6_27_24, MMC_D7),
629 PINMUX_IPSR_MSEL(IP6_27_24, SDA3_B, SEL_I2C3_1),
630
631 PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11),
632 PINMUX_IPSR_GPSR(IP6_31_28, SCL4),
633 PINMUX_IPSR_GPSR(IP6_31_28, IRQ4),
634 PINMUX_IPSR_GPSR(IP6_31_28, D14),
635
636 /* IPSR7 */
637 PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD),
638 PINMUX_IPSR_GPSR(IP7_3_0, SDA4),
639 PINMUX_IPSR_GPSR(IP7_3_0, IRQ5),
640 PINMUX_IPSR_GPSR(IP7_3_0, D15),
641
642 PINMUX_IPSR_GPSR(IP7_7_4, SCL0),
643 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR0),
644 PINMUX_IPSR_GPSR(IP7_7_4, TPU0TO0),
645 PINMUX_IPSR_GPSR(IP7_7_4, CLKOUT),
646 PINMUX_IPSR_GPSR(IP7_7_4, MSIOF0_RXD),
647
648 PINMUX_IPSR_GPSR(IP7_11_8, SDA0),
649 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR1),
650 PINMUX_IPSR_GPSR(IP7_11_8, TPU0TO1),
651 PINMUX_IPSR_GPSR(IP7_11_8, BS_N),
652 PINMUX_IPSR_GPSR(IP7_11_8, SCK0),
653 PINMUX_IPSR_GPSR(IP7_11_8, MSIOF0_TXD),
654
655 PINMUX_IPSR_GPSR(IP7_15_12, SCL1),
656 PINMUX_IPSR_GPSR(IP7_15_12, DU_DG0),
657 PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2),
658 PINMUX_IPSR_GPSR(IP7_15_12, RD_N),
659 PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N),
660 PINMUX_IPSR_GPSR(IP7_15_12, MSIOF0_SCK),
661
662 PINMUX_IPSR_GPSR(IP7_19_16, SDA1),
663 PINMUX_IPSR_GPSR(IP7_19_16, DU_DG1),
664 PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
665 PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
666 PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N),
667 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF0_SYNC),
668
669 PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
670 PINMUX_IPSR_GPSR(IP7_23_20, DU_DB0),
671 PINMUX_IPSR_MSEL(IP7_23_20, TCLK1_A, SEL_TMU_0),
672 PINMUX_IPSR_GPSR(IP7_23_20, WE1_N),
673 PINMUX_IPSR_GPSR(IP7_23_20, RX0),
674 PINMUX_IPSR_GPSR(IP7_23_20, MSIOF0_SS1),
675
676 PINMUX_IPSR_GPSR(IP7_27_24, SDA2),
677 PINMUX_IPSR_GPSR(IP7_27_24, DU_DB1),
678 PINMUX_IPSR_MSEL(IP7_27_24, TCLK2_A, SEL_TMU_0),
679 PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0),
680 PINMUX_IPSR_GPSR(IP7_27_24, TX0),
681 PINMUX_IPSR_GPSR(IP7_27_24, MSIOF0_SS2),
682
683 PINMUX_IPSR_GPSR(IP7_31_28, AVB0_AVTP_CAPTURE),
684 PINMUX_IPSR_GPSR(IP7_31_28, FSCLKST2_N_B),
685
686 /* IPSR8 */
687 PINMUX_IPSR_MSEL(IP8_3_0, CANFD0_TX_A, SEL_CANFD0_0),
688 PINMUX_IPSR_GPSR(IP8_3_0, FXR_TXDA),
689 PINMUX_IPSR_MSEL(IP8_3_0, PWM0_B, SEL_PWM0_1),
690 PINMUX_IPSR_GPSR(IP8_3_0, DU_DISP),
691 PINMUX_IPSR_GPSR(IP8_3_0, FSCLKST2_N_C),
692
693 PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_RX_A, SEL_CANFD0_0),
694 PINMUX_IPSR_GPSR(IP8_7_4, RXDA_EXTFXR),
695 PINMUX_IPSR_MSEL(IP8_7_4, PWM1_B, SEL_PWM1_1),
696 PINMUX_IPSR_GPSR(IP8_7_4, DU_CDE),
697
698 PINMUX_IPSR_GPSR(IP8_11_8, CANFD1_TX),
699 PINMUX_IPSR_GPSR(IP8_11_8, FXR_TXDB),
700 PINMUX_IPSR_MSEL(IP8_11_8, PWM2_B, SEL_PWM2_1),
701 PINMUX_IPSR_MSEL(IP8_11_8, TCLK1_B, SEL_TMU_1),
702 PINMUX_IPSR_MSEL(IP8_11_8, TX1_B, SEL_SCIF1_1),
703
704 PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_RX),
705 PINMUX_IPSR_GPSR(IP8_15_12, RXDB_EXTFXR),
706 PINMUX_IPSR_MSEL(IP8_15_12, PWM3_B, SEL_PWM3_1),
707 PINMUX_IPSR_MSEL(IP8_15_12, TCLK2_B, SEL_TMU_1),
708 PINMUX_IPSR_MSEL(IP8_15_12, RX1_B, SEL_SCIF1_1),
709
710 PINMUX_IPSR_MSEL(IP8_19_16, CANFD_CLK_A, SEL_CANFD0_0),
711 PINMUX_IPSR_GPSR(IP8_19_16, CLK_EXTFXR),
712 PINMUX_IPSR_MSEL(IP8_19_16, PWM4_B, SEL_PWM4_1),
713 PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_B, SEL_RSP_1),
714 PINMUX_IPSR_MSEL(IP8_19_16, SCIF_CLK_B, SEL_HSCIF0_1),
715
716 PINMUX_IPSR_GPSR(IP8_23_20, DIGRF_CLKIN),
717 PINMUX_IPSR_GPSR(IP8_23_20, DIGRF_CLKEN_IN),
718
719 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKOUT),
720 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_OUT),
721 };
722
723 static const struct sh_pfc_pin pinmux_pins[] = {
724 PINMUX_GPIO_GP_ALL(),
725 };
726
727 /* - AVB0 ------------------------------------------------------------------- */
728 static const unsigned int avb0_link_pins[] = {
729 /* AVB0_LINK */
730 RCAR_GP_PIN(1, 18),
731 };
732 static const unsigned int avb0_link_mux[] = {
733 AVB0_LINK_MARK,
734 };
735 static const unsigned int avb0_magic_pins[] = {
736 /* AVB0_MAGIC */
737 RCAR_GP_PIN(1, 16),
738 };
739 static const unsigned int avb0_magic_mux[] = {
740 AVB0_MAGIC_MARK,
741 };
742 static const unsigned int avb0_phy_int_pins[] = {
743 /* AVB0_PHY_INT */
744 RCAR_GP_PIN(1, 17),
745 };
746 static const unsigned int avb0_phy_int_mux[] = {
747 AVB0_PHY_INT_MARK,
748 };
749 static const unsigned int avb0_mdio_pins[] = {
750 /* AVB0_MDC, AVB0_MDIO */
751 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
752 };
753 static const unsigned int avb0_mdio_mux[] = {
754 AVB0_MDC_MARK, AVB0_MDIO_MARK,
755 };
756 static const unsigned int avb0_rgmii_pins[] = {
757 /*
758 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
759 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3
760 */
761 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
762 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
763 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
764 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
765 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
766 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
767 };
768 static const unsigned int avb0_rgmii_mux[] = {
769 AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
770 AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
771 AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
772 AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
773 };
774 static const unsigned int avb0_txcrefclk_pins[] = {
775 /* AVB0_TXCREFCLK */
776 RCAR_GP_PIN(1, 13),
777 };
778 static const unsigned int avb0_txcrefclk_mux[] = {
779 AVB0_TXCREFCLK_MARK,
780 };
781 static const unsigned int avb0_avtp_pps_pins[] = {
782 /* AVB0_AVTP_PPS */
783 RCAR_GP_PIN(2, 6),
784 };
785 static const unsigned int avb0_avtp_pps_mux[] = {
786 AVB0_AVTP_PPS_MARK,
787 };
788 static const unsigned int avb0_avtp_capture_pins[] = {
789 /* AVB0_AVTP_CAPTURE */
790 RCAR_GP_PIN(1, 20),
791 };
792 static const unsigned int avb0_avtp_capture_mux[] = {
793 AVB0_AVTP_CAPTURE_MARK,
794 };
795 static const unsigned int avb0_avtp_match_pins[] = {
796 /* AVB0_AVTP_MATCH */
797 RCAR_GP_PIN(1, 19),
798 };
799 static const unsigned int avb0_avtp_match_mux[] = {
800 AVB0_AVTP_MATCH_MARK,
801 };
802
803 /* - CANFD Clock ------------------------------------------------------------ */
804 static const unsigned int canfd_clk_a_pins[] = {
805 /* CANFD_CLK */
806 RCAR_GP_PIN(1, 25),
807 };
808 static const unsigned int canfd_clk_a_mux[] = {
809 CANFD_CLK_A_MARK,
810 };
811 static const unsigned int canfd_clk_b_pins[] = {
812 /* CANFD_CLK */
813 RCAR_GP_PIN(3, 8),
814 };
815 static const unsigned int canfd_clk_b_mux[] = {
816 CANFD_CLK_B_MARK,
817 };
818
819 /* - CANFD0 ----------------------------------------------------------------- */
820 static const unsigned int canfd0_data_a_pins[] = {
821 /* TX, RX */
822 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
823 };
824 static const unsigned int canfd0_data_a_mux[] = {
825 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
826 };
827 static const unsigned int canfd0_data_b_pins[] = {
828 /* TX, RX */
829 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
830 };
831 static const unsigned int canfd0_data_b_mux[] = {
832 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
833 };
834
835 /* - CANFD1 ----------------------------------------------------------------- */
836 static const unsigned int canfd1_data_pins[] = {
837 /* TX, RX */
838 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
839 };
840 static const unsigned int canfd1_data_mux[] = {
841 CANFD1_TX_MARK, CANFD1_RX_MARK,
842 };
843
844 /* - DU --------------------------------------------------------------------- */
845 static const unsigned int du_rgb666_pins[] = {
846 /* R[7:2], G[7:2], B[7:2] */
847 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
848 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
849 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
850 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
851 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
852 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
853 };
854 static const unsigned int du_rgb666_mux[] = {
855 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
856 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
857 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
858 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
859 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
860 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
861 };
862 static const unsigned int du_clk_out_pins[] = {
863 /* DOTCLKOUT */
864 RCAR_GP_PIN(0, 18),
865 };
866 static const unsigned int du_clk_out_mux[] = {
867 DU_DOTCLKOUT_MARK,
868 };
869 static const unsigned int du_sync_pins[] = {
870 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
871 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
872 };
873 static const unsigned int du_sync_mux[] = {
874 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
875 };
876 static const unsigned int du_oddf_pins[] = {
877 /* EXODDF/ODDF/DISP/CDE */
878 RCAR_GP_PIN(0, 21),
879 };
880 static const unsigned int du_oddf_mux[] = {
881 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
882 };
883 static const unsigned int du_cde_pins[] = {
884 /* CDE */
885 RCAR_GP_PIN(1, 22),
886 };
887 static const unsigned int du_cde_mux[] = {
888 DU_CDE_MARK,
889 };
890 static const unsigned int du_disp_pins[] = {
891 /* DISP */
892 RCAR_GP_PIN(1, 21),
893 };
894 static const unsigned int du_disp_mux[] = {
895 DU_DISP_MARK,
896 };
897
898 /* - HSCIF0 ----------------------------------------------------------------- */
899 static const unsigned int hscif0_data_pins[] = {
900 /* HRX, HTX */
901 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 3),
902 };
903 static const unsigned int hscif0_data_mux[] = {
904 HRX0_MARK, HTX0_MARK,
905 };
906 static const unsigned int hscif0_clk_pins[] = {
907 /* HSCK */
908 RCAR_GP_PIN(0, 0),
909 };
910 static const unsigned int hscif0_clk_mux[] = {
911 HSCK0_MARK,
912 };
913 static const unsigned int hscif0_ctrl_pins[] = {
914 /* HRTS#, HCTS# */
915 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
916 };
917 static const unsigned int hscif0_ctrl_mux[] = {
918 HRTS0_N_MARK, HCTS0_N_MARK,
919 };
920
921 /* - HSCIF1 ----------------------------------------------------------------- */
922 static const unsigned int hscif1_data_pins[] = {
923 /* HRX, HTX */
924 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
925 };
926 static const unsigned int hscif1_data_mux[] = {
927 HRX1_MARK, HTX1_MARK,
928 };
929 static const unsigned int hscif1_clk_pins[] = {
930 /* HSCK */
931 RCAR_GP_PIN(2, 7),
932 };
933 static const unsigned int hscif1_clk_mux[] = {
934 HSCK1_MARK,
935 };
936 static const unsigned int hscif1_ctrl_pins[] = {
937 /* HRTS#, HCTS# */
938 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
939 };
940 static const unsigned int hscif1_ctrl_mux[] = {
941 HRTS1_N_MARK, HCTS1_N_MARK,
942 };
943
944 /* - HSCIF2 ----------------------------------------------------------------- */
945 static const unsigned int hscif2_data_pins[] = {
946 /* HRX, HTX */
947 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
948 };
949 static const unsigned int hscif2_data_mux[] = {
950 HRX2_MARK, HTX2_MARK,
951 };
952 static const unsigned int hscif2_clk_pins[] = {
953 /* HSCK */
954 RCAR_GP_PIN(2, 12),
955 };
956 static const unsigned int hscif2_clk_mux[] = {
957 HSCK2_MARK,
958 };
959 static const unsigned int hscif2_ctrl_pins[] = {
960 /* HRTS#, HCTS# */
961 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
962 };
963 static const unsigned int hscif2_ctrl_mux[] = {
964 HRTS2_N_MARK, HCTS2_N_MARK,
965 };
966
967 /* - HSCIF3 ----------------------------------------------------------------- */
968 static const unsigned int hscif3_data_pins[] = {
969 /* HRX, HTX */
970 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
971 };
972 static const unsigned int hscif3_data_mux[] = {
973 HRX3_MARK, HTX3_MARK,
974 };
975 static const unsigned int hscif3_clk_pins[] = {
976 /* HSCK */
977 RCAR_GP_PIN(2, 0),
978 };
979 static const unsigned int hscif3_clk_mux[] = {
980 HSCK3_MARK,
981 };
982 static const unsigned int hscif3_ctrl_pins[] = {
983 /* HRTS#, HCTS# */
984 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
985 };
986 static const unsigned int hscif3_ctrl_mux[] = {
987 HRTS3_N_MARK, HCTS3_N_MARK,
988 };
989
990 /* - I2C0 ------------------------------------------------------------------- */
991 static const unsigned int i2c0_pins[] = {
992 /* SDA, SCL */
993 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
994 };
995 static const unsigned int i2c0_mux[] = {
996 SDA0_MARK, SCL0_MARK,
997 };
998
999 /* - I2C1 ------------------------------------------------------------------- */
1000 static const unsigned int i2c1_pins[] = {
1001 /* SDA, SCL */
1002 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1003 };
1004 static const unsigned int i2c1_mux[] = {
1005 SDA1_MARK, SCL1_MARK,
1006 };
1007
1008 /* - I2C2 ------------------------------------------------------------------- */
1009 static const unsigned int i2c2_pins[] = {
1010 /* SDA, SCL */
1011 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1012 };
1013 static const unsigned int i2c2_mux[] = {
1014 SDA2_MARK, SCL2_MARK,
1015 };
1016
1017 /* - I2C3 ------------------------------------------------------------------- */
1018 static const unsigned int i2c3_a_pins[] = {
1019 /* SDA, SCL */
1020 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1021 };
1022 static const unsigned int i2c3_a_mux[] = {
1023 SDA3_A_MARK, SCL3_A_MARK,
1024 };
1025 static const unsigned int i2c3_b_pins[] = {
1026 /* SDA, SCL */
1027 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1028 };
1029 static const unsigned int i2c3_b_mux[] = {
1030 SDA3_B_MARK, SCL3_B_MARK,
1031 };
1032
1033 /* - I2C4 ------------------------------------------------------------------- */
1034 static const unsigned int i2c4_pins[] = {
1035 /* SDA, SCL */
1036 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
1037 };
1038 static const unsigned int i2c4_mux[] = {
1039 SDA4_MARK, SCL4_MARK,
1040 };
1041
1042 /* - INTC-EX ---------------------------------------------------------------- */
1043 static const unsigned int intc_ex_irq0_pins[] = {
1044 /* IRQ0 */
1045 RCAR_GP_PIN(1, 0),
1046 };
1047 static const unsigned int intc_ex_irq0_mux[] = {
1048 IRQ0_MARK,
1049 };
1050 static const unsigned int intc_ex_irq1_pins[] = {
1051 /* IRQ1 */
1052 RCAR_GP_PIN(0, 11),
1053 };
1054 static const unsigned int intc_ex_irq1_mux[] = {
1055 IRQ1_MARK,
1056 };
1057 static const unsigned int intc_ex_irq2_pins[] = {
1058 /* IRQ2 */
1059 RCAR_GP_PIN(0, 12),
1060 };
1061 static const unsigned int intc_ex_irq2_mux[] = {
1062 IRQ2_MARK,
1063 };
1064 static const unsigned int intc_ex_irq3_pins[] = {
1065 /* IRQ3 */
1066 RCAR_GP_PIN(0, 19),
1067 };
1068 static const unsigned int intc_ex_irq3_mux[] = {
1069 IRQ3_MARK,
1070 };
1071 static const unsigned int intc_ex_irq4_pins[] = {
1072 /* IRQ4 */
1073 RCAR_GP_PIN(3, 15),
1074 };
1075 static const unsigned int intc_ex_irq4_mux[] = {
1076 IRQ4_MARK,
1077 };
1078 static const unsigned int intc_ex_irq5_pins[] = {
1079 /* IRQ5 */
1080 RCAR_GP_PIN(3, 16),
1081 };
1082 static const unsigned int intc_ex_irq5_mux[] = {
1083 IRQ5_MARK,
1084 };
1085
1086 /* - MMC -------------------------------------------------------------------- */
1087 static const unsigned int mmc_data1_pins[] = {
1088 /* D0 */
1089 RCAR_GP_PIN(3, 6),
1090 };
1091 static const unsigned int mmc_data1_mux[] = {
1092 MMC_D0_MARK,
1093 };
1094 static const unsigned int mmc_data4_pins[] = {
1095 /* D[0:3] */
1096 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1097 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1098 };
1099 static const unsigned int mmc_data4_mux[] = {
1100 MMC_D0_MARK, MMC_D1_MARK,
1101 MMC_D2_MARK, MMC_D3_MARK,
1102 };
1103 static const unsigned int mmc_data8_pins[] = {
1104 /* D[0:7] */
1105 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1106 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1107 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1108 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1109 };
1110 static const unsigned int mmc_data8_mux[] = {
1111 MMC_D0_MARK, MMC_D1_MARK,
1112 MMC_D2_MARK, MMC_D3_MARK,
1113 MMC_D4_MARK, MMC_D5_MARK,
1114 MMC_D6_MARK, MMC_D7_MARK,
1115 };
1116 static const unsigned int mmc_ctrl_pins[] = {
1117 /* CLK, CMD */
1118 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 5),
1119 };
1120 static const unsigned int mmc_ctrl_mux[] = {
1121 MMC_CLK_MARK, MMC_CMD_MARK,
1122 };
1123
1124 /* - MSIOF0 ----------------------------------------------------------------- */
1125 static const unsigned int msiof0_clk_pins[] = {
1126 /* SCK */
1127 RCAR_GP_PIN(4, 2),
1128 };
1129 static const unsigned int msiof0_clk_mux[] = {
1130 MSIOF0_SCK_MARK,
1131 };
1132 static const unsigned int msiof0_sync_pins[] = {
1133 /* SYNC */
1134 RCAR_GP_PIN(4, 3),
1135 };
1136 static const unsigned int msiof0_sync_mux[] = {
1137 MSIOF0_SYNC_MARK,
1138 };
1139 static const unsigned int msiof0_ss1_pins[] = {
1140 /* SS1 */
1141 RCAR_GP_PIN(4, 4),
1142 };
1143 static const unsigned int msiof0_ss1_mux[] = {
1144 MSIOF0_SS1_MARK,
1145 };
1146 static const unsigned int msiof0_ss2_pins[] = {
1147 /* SS2 */
1148 RCAR_GP_PIN(4, 5),
1149 };
1150 static const unsigned int msiof0_ss2_mux[] = {
1151 MSIOF0_SS2_MARK,
1152 };
1153 static const unsigned int msiof0_txd_pins[] = {
1154 /* TXD */
1155 RCAR_GP_PIN(4, 1),
1156 };
1157 static const unsigned int msiof0_txd_mux[] = {
1158 MSIOF0_TXD_MARK,
1159 };
1160 static const unsigned int msiof0_rxd_pins[] = {
1161 /* RXD */
1162 RCAR_GP_PIN(4, 0),
1163 };
1164 static const unsigned int msiof0_rxd_mux[] = {
1165 MSIOF0_RXD_MARK,
1166 };
1167
1168 /* - MSIOF1 ----------------------------------------------------------------- */
1169 static const unsigned int msiof1_clk_pins[] = {
1170 /* SCK */
1171 RCAR_GP_PIN(3, 2),
1172 };
1173 static const unsigned int msiof1_clk_mux[] = {
1174 MSIOF1_SCK_MARK,
1175 };
1176 static const unsigned int msiof1_sync_pins[] = {
1177 /* SYNC */
1178 RCAR_GP_PIN(3, 3),
1179 };
1180 static const unsigned int msiof1_sync_mux[] = {
1181 MSIOF1_SYNC_MARK,
1182 };
1183 static const unsigned int msiof1_ss1_pins[] = {
1184 /* SS1 */
1185 RCAR_GP_PIN(3, 4),
1186 };
1187 static const unsigned int msiof1_ss1_mux[] = {
1188 MSIOF1_SS1_MARK,
1189 };
1190 static const unsigned int msiof1_ss2_pins[] = {
1191 /* SS2 */
1192 RCAR_GP_PIN(3, 5),
1193 };
1194 static const unsigned int msiof1_ss2_mux[] = {
1195 MSIOF1_SS2_MARK,
1196 };
1197 static const unsigned int msiof1_txd_pins[] = {
1198 /* TXD */
1199 RCAR_GP_PIN(3, 1),
1200 };
1201 static const unsigned int msiof1_txd_mux[] = {
1202 MSIOF1_TXD_MARK,
1203 };
1204 static const unsigned int msiof1_rxd_pins[] = {
1205 /* RXD */
1206 RCAR_GP_PIN(3, 0),
1207 };
1208 static const unsigned int msiof1_rxd_mux[] = {
1209 MSIOF1_RXD_MARK,
1210 };
1211
1212 /* - MSIOF2 ----------------------------------------------------------------- */
1213 static const unsigned int msiof2_clk_pins[] = {
1214 /* SCK */
1215 RCAR_GP_PIN(2, 0),
1216 };
1217 static const unsigned int msiof2_clk_mux[] = {
1218 MSIOF2_SCK_MARK,
1219 };
1220 static const unsigned int msiof2_sync_pins[] = {
1221 /* SYNC */
1222 RCAR_GP_PIN(2, 3),
1223 };
1224 static const unsigned int msiof2_sync_mux[] = {
1225 MSIOF2_SYNC_MARK,
1226 };
1227 static const unsigned int msiof2_ss1_pins[] = {
1228 /* SS1 */
1229 RCAR_GP_PIN(2, 4),
1230 };
1231 static const unsigned int msiof2_ss1_mux[] = {
1232 MSIOF2_SS1_MARK,
1233 };
1234 static const unsigned int msiof2_ss2_pins[] = {
1235 /* SS2 */
1236 RCAR_GP_PIN(2, 5),
1237 };
1238 static const unsigned int msiof2_ss2_mux[] = {
1239 MSIOF2_SS2_MARK,
1240 };
1241 static const unsigned int msiof2_txd_pins[] = {
1242 /* TXD */
1243 RCAR_GP_PIN(2, 2),
1244 };
1245 static const unsigned int msiof2_txd_mux[] = {
1246 MSIOF2_TXD_MARK,
1247 };
1248 static const unsigned int msiof2_rxd_pins[] = {
1249 /* RXD */
1250 RCAR_GP_PIN(2, 1),
1251 };
1252 static const unsigned int msiof2_rxd_mux[] = {
1253 MSIOF2_RXD_MARK,
1254 };
1255
1256 /* - MSIOF3 ----------------------------------------------------------------- */
1257 static const unsigned int msiof3_clk_pins[] = {
1258 /* SCK */
1259 RCAR_GP_PIN(0, 20),
1260 };
1261 static const unsigned int msiof3_clk_mux[] = {
1262 MSIOF3_SCK_MARK,
1263 };
1264 static const unsigned int msiof3_sync_pins[] = {
1265 /* SYNC */
1266 RCAR_GP_PIN(0, 21),
1267 };
1268 static const unsigned int msiof3_sync_mux[] = {
1269 MSIOF3_SYNC_MARK,
1270 };
1271 static const unsigned int msiof3_ss1_pins[] = {
1272 /* SS1 */
1273 RCAR_GP_PIN(0, 6),
1274 };
1275 static const unsigned int msiof3_ss1_mux[] = {
1276 MSIOF3_SS1_MARK,
1277 };
1278 static const unsigned int msiof3_ss2_pins[] = {
1279 /* SS2 */
1280 RCAR_GP_PIN(0, 7),
1281 };
1282 static const unsigned int msiof3_ss2_mux[] = {
1283 MSIOF3_SS2_MARK,
1284 };
1285 static const unsigned int msiof3_txd_pins[] = {
1286 /* TXD */
1287 RCAR_GP_PIN(0, 5),
1288 };
1289 static const unsigned int msiof3_txd_mux[] = {
1290 MSIOF3_TXD_MARK,
1291 };
1292 static const unsigned int msiof3_rxd_pins[] = {
1293 /* RXD */
1294 RCAR_GP_PIN(0, 4),
1295 };
1296 static const unsigned int msiof3_rxd_mux[] = {
1297 MSIOF3_RXD_MARK,
1298 };
1299
1300 /* - PWM0 ------------------------------------------------------------------- */
1301 static const unsigned int pwm0_a_pins[] = {
1302 RCAR_GP_PIN(2, 12),
1303 };
1304 static const unsigned int pwm0_a_mux[] = {
1305 PWM0_A_MARK,
1306 };
1307 static const unsigned int pwm0_b_pins[] = {
1308 RCAR_GP_PIN(1, 21),
1309 };
1310 static const unsigned int pwm0_b_mux[] = {
1311 PWM0_B_MARK,
1312 };
1313
1314 /* - PWM1 ------------------------------------------------------------------- */
1315 static const unsigned int pwm1_a_pins[] = {
1316 RCAR_GP_PIN(2, 13),
1317 };
1318 static const unsigned int pwm1_a_mux[] = {
1319 PWM1_A_MARK,
1320 };
1321 static const unsigned int pwm1_b_pins[] = {
1322 RCAR_GP_PIN(1, 22),
1323 };
1324 static const unsigned int pwm1_b_mux[] = {
1325 PWM1_B_MARK,
1326 };
1327
1328 /* - PWM2 ------------------------------------------------------------------- */
1329 static const unsigned int pwm2_a_pins[] = {
1330 RCAR_GP_PIN(2, 14),
1331 };
1332 static const unsigned int pwm2_a_mux[] = {
1333 PWM2_A_MARK,
1334 };
1335 static const unsigned int pwm2_b_pins[] = {
1336 RCAR_GP_PIN(1, 23),
1337 };
1338 static const unsigned int pwm2_b_mux[] = {
1339 PWM2_B_MARK,
1340 };
1341
1342 /* - PWM3 ------------------------------------------------------------------- */
1343 static const unsigned int pwm3_a_pins[] = {
1344 RCAR_GP_PIN(2, 15),
1345 };
1346 static const unsigned int pwm3_a_mux[] = {
1347 PWM3_A_MARK,
1348 };
1349 static const unsigned int pwm3_b_pins[] = {
1350 RCAR_GP_PIN(1, 24),
1351 };
1352 static const unsigned int pwm3_b_mux[] = {
1353 PWM3_B_MARK,
1354 };
1355
1356 /* - PWM4 ------------------------------------------------------------------- */
1357 static const unsigned int pwm4_a_pins[] = {
1358 RCAR_GP_PIN(2, 16),
1359 };
1360 static const unsigned int pwm4_a_mux[] = {
1361 PWM4_A_MARK,
1362 };
1363 static const unsigned int pwm4_b_pins[] = {
1364 RCAR_GP_PIN(1, 25),
1365 };
1366 static const unsigned int pwm4_b_mux[] = {
1367 PWM4_B_MARK,
1368 };
1369
1370 /* - QSPI0 ------------------------------------------------------------------ */
1371 static const unsigned int qspi0_ctrl_pins[] = {
1372 /* SPCLK, SSL */
1373 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
1374 };
1375 static const unsigned int qspi0_ctrl_mux[] = {
1376 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
1377 };
1378 static const unsigned int qspi0_data2_pins[] = {
1379 /* MOSI_IO0, MISO_IO1 */
1380 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1381 };
1382 static const unsigned int qspi0_data2_mux[] = {
1383 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1384 };
1385 static const unsigned int qspi0_data4_pins[] = {
1386 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1387 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1388 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
1389 };
1390 static const unsigned int qspi0_data4_mux[] = {
1391 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1392 QSPI0_IO2_MARK, QSPI0_IO3_MARK
1393 };
1394
1395 /* - QSPI1 ------------------------------------------------------------------ */
1396 static const unsigned int qspi1_ctrl_pins[] = {
1397 /* SPCLK, SSL */
1398 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
1399 };
1400 static const unsigned int qspi1_ctrl_mux[] = {
1401 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
1402 };
1403 static const unsigned int qspi1_data2_pins[] = {
1404 /* MOSI_IO0, MISO_IO1 */
1405 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1406 };
1407 static const unsigned int qspi1_data2_mux[] = {
1408 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1409 };
1410 static const unsigned int qspi1_data4_pins[] = {
1411 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1412 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1413 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1414 };
1415 static const unsigned int qspi1_data4_mux[] = {
1416 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1417 QSPI1_IO2_MARK, QSPI1_IO3_MARK
1418 };
1419
1420 /* - RPC -------------------------------------------------------------------- */
1421 static const unsigned int rpc_clk1_pins[] = {
1422 /* Octal-SPI flash: C/SCLK */
1423 RCAR_GP_PIN(5, 0),
1424 };
1425 static const unsigned int rpc_clk1_mux[] = {
1426 QSPI0_SPCLK_MARK,
1427 };
1428 static const unsigned int rpc_clk2_pins[] = {
1429 /* HyperFlash: CK, CK# */
1430 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
1431 };
1432 static const unsigned int rpc_clk2_mux[] = {
1433 QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
1434 };
1435 static const unsigned int rpc_ctrl_pins[] = {
1436 /* Octal-SPI flash: S#/CS, DQS */
1437 /* HyperFlash: CS#, RDS */
1438 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1439 };
1440 static const unsigned int rpc_ctrl_mux[] = {
1441 QSPI0_SSL_MARK, QSPI1_SSL_MARK,
1442 };
1443 static const unsigned int rpc_data_pins[] = {
1444 /* DQ[0:7] */
1445 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1446 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
1447 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1448 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1449 };
1450 static const unsigned int rpc_data_mux[] = {
1451 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1452 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
1453 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1454 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
1455 };
1456 static const unsigned int rpc_reset_pins[] = {
1457 /* RPC_RESET# */
1458 RCAR_GP_PIN(5, 12),
1459 };
1460 static const unsigned int rpc_reset_mux[] = {
1461 RPC_RESET_N_MARK,
1462 };
1463 static const unsigned int rpc_int_pins[] = {
1464 /* RPC_INT# */
1465 RCAR_GP_PIN(5, 14),
1466 };
1467 static const unsigned int rpc_int_mux[] = {
1468 RPC_INT_N_MARK,
1469 };
1470 static const unsigned int rpc_wp_pins[] = {
1471 /* RPC_WP# */
1472 RCAR_GP_PIN(5, 13),
1473 };
1474 static const unsigned int rpc_wp_mux[] = {
1475 RPC_WP_N_MARK,
1476 };
1477
1478 /* - SCIF Clock ------------------------------------------------------------- */
1479 static const unsigned int scif_clk_a_pins[] = {
1480 /* SCIF_CLK */
1481 RCAR_GP_PIN(0, 18),
1482 };
1483 static const unsigned int scif_clk_a_mux[] = {
1484 SCIF_CLK_A_MARK,
1485 };
1486 static const unsigned int scif_clk_b_pins[] = {
1487 /* SCIF_CLK */
1488 RCAR_GP_PIN(1, 25),
1489 };
1490 static const unsigned int scif_clk_b_mux[] = {
1491 SCIF_CLK_B_MARK,
1492 };
1493
1494 /* - SCIF0 ------------------------------------------------------------------ */
1495 static const unsigned int scif0_data_pins[] = {
1496 /* RX, TX */
1497 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1498 };
1499 static const unsigned int scif0_data_mux[] = {
1500 RX0_MARK, TX0_MARK,
1501 };
1502 static const unsigned int scif0_clk_pins[] = {
1503 /* SCK */
1504 RCAR_GP_PIN(4, 1),
1505 };
1506 static const unsigned int scif0_clk_mux[] = {
1507 SCK0_MARK,
1508 };
1509 static const unsigned int scif0_ctrl_pins[] = {
1510 /* RTS#, CTS# */
1511 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1512 };
1513 static const unsigned int scif0_ctrl_mux[] = {
1514 RTS0_N_MARK, CTS0_N_MARK,
1515 };
1516
1517 /* - SCIF1 ------------------------------------------------------------------ */
1518 static const unsigned int scif1_data_a_pins[] = {
1519 /* RX, TX */
1520 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1521 };
1522 static const unsigned int scif1_data_a_mux[] = {
1523 RX1_A_MARK, TX1_A_MARK,
1524 };
1525 static const unsigned int scif1_clk_pins[] = {
1526 /* SCK */
1527 RCAR_GP_PIN(2, 5),
1528 };
1529 static const unsigned int scif1_clk_mux[] = {
1530 SCK1_MARK,
1531 };
1532 static const unsigned int scif1_ctrl_pins[] = {
1533 /* RTS#, CTS# */
1534 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1535 };
1536 static const unsigned int scif1_ctrl_mux[] = {
1537 RTS1_N_MARK, CTS1_N_MARK,
1538 };
1539 static const unsigned int scif1_data_b_pins[] = {
1540 /* RX, TX */
1541 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
1542 };
1543 static const unsigned int scif1_data_b_mux[] = {
1544 RX1_B_MARK, TX1_B_MARK,
1545 };
1546
1547 /* - SCIF3 ------------------------------------------------------------------ */
1548 static const unsigned int scif3_data_pins[] = {
1549 /* RX, TX */
1550 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
1551 };
1552 static const unsigned int scif3_data_mux[] = {
1553 RX3_MARK, TX3_MARK,
1554 };
1555 static const unsigned int scif3_clk_pins[] = {
1556 /* SCK */
1557 RCAR_GP_PIN(2, 0),
1558 };
1559 static const unsigned int scif3_clk_mux[] = {
1560 SCK3_MARK,
1561 };
1562 static const unsigned int scif3_ctrl_pins[] = {
1563 /* RTS#, CTS# */
1564 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1565 };
1566 static const unsigned int scif3_ctrl_mux[] = {
1567 RTS3_N_MARK, CTS3_N_MARK,
1568 };
1569
1570 /* - SCIF4 ------------------------------------------------------------------ */
1571 static const unsigned int scif4_data_pins[] = {
1572 /* RX, TX */
1573 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1574 };
1575 static const unsigned int scif4_data_mux[] = {
1576 RX4_MARK, TX4_MARK,
1577 };
1578 static const unsigned int scif4_clk_pins[] = {
1579 /* SCK */
1580 RCAR_GP_PIN(3, 9),
1581 };
1582 static const unsigned int scif4_clk_mux[] = {
1583 SCK4_MARK,
1584 };
1585 static const unsigned int scif4_ctrl_pins[] = {
1586 /* RTS#, CTS# */
1587 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
1588 };
1589 static const unsigned int scif4_ctrl_mux[] = {
1590 RTS4_N_MARK, CTS4_N_MARK,
1591 };
1592
1593 /* - TMU -------------------------------------------------------------------- */
1594 static const unsigned int tmu_tclk1_a_pins[] = {
1595 /* TCLK1 */
1596 RCAR_GP_PIN(4, 4),
1597 };
1598 static const unsigned int tmu_tclk1_a_mux[] = {
1599 TCLK1_A_MARK,
1600 };
1601 static const unsigned int tmu_tclk1_b_pins[] = {
1602 /* TCLK1 */
1603 RCAR_GP_PIN(1, 23),
1604 };
1605 static const unsigned int tmu_tclk1_b_mux[] = {
1606 TCLK1_B_MARK,
1607 };
1608 static const unsigned int tmu_tclk2_a_pins[] = {
1609 /* TCLK2 */
1610 RCAR_GP_PIN(4, 5),
1611 };
1612 static const unsigned int tmu_tclk2_a_mux[] = {
1613 TCLK2_A_MARK,
1614 };
1615 static const unsigned int tmu_tclk2_b_pins[] = {
1616 /* TCLK2 */
1617 RCAR_GP_PIN(1, 24),
1618 };
1619 static const unsigned int tmu_tclk2_b_mux[] = {
1620 TCLK2_B_MARK,
1621 };
1622
1623 /* - VIN0 ------------------------------------------------------------------- */
1624 static const union vin_data12 vin0_data_pins = {
1625 .data12 = {
1626 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1627 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1628 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1629 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1630 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1631 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1632 },
1633 };
1634 static const union vin_data12 vin0_data_mux = {
1635 .data12 = {
1636 VI0_DATA0_MARK, VI0_DATA1_MARK,
1637 VI0_DATA2_MARK, VI0_DATA3_MARK,
1638 VI0_DATA4_MARK, VI0_DATA5_MARK,
1639 VI0_DATA6_MARK, VI0_DATA7_MARK,
1640 VI0_DATA8_MARK, VI0_DATA9_MARK,
1641 VI0_DATA10_MARK, VI0_DATA11_MARK,
1642 },
1643 };
1644 static const unsigned int vin0_sync_pins[] = {
1645 /* HSYNC#, VSYNC# */
1646 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1647 };
1648 static const unsigned int vin0_sync_mux[] = {
1649 VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
1650 };
1651 static const unsigned int vin0_field_pins[] = {
1652 /* FIELD */
1653 RCAR_GP_PIN(2, 16),
1654 };
1655 static const unsigned int vin0_field_mux[] = {
1656 VI0_FIELD_MARK,
1657 };
1658 static const unsigned int vin0_clkenb_pins[] = {
1659 /* CLKENB */
1660 RCAR_GP_PIN(2, 1),
1661 };
1662 static const unsigned int vin0_clkenb_mux[] = {
1663 VI0_CLKENB_MARK,
1664 };
1665 static const unsigned int vin0_clk_pins[] = {
1666 /* CLK */
1667 RCAR_GP_PIN(2, 0),
1668 };
1669 static const unsigned int vin0_clk_mux[] = {
1670 VI0_CLK_MARK,
1671 };
1672
1673 /* - VIN1 ------------------------------------------------------------------- */
1674 static const union vin_data12 vin1_data_pins = {
1675 .data12 = {
1676 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1677 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1678 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1679 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1680 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1681 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
1682 },
1683 };
1684 static const union vin_data12 vin1_data_mux = {
1685 .data12 = {
1686 VI1_DATA0_MARK, VI1_DATA1_MARK,
1687 VI1_DATA2_MARK, VI1_DATA3_MARK,
1688 VI1_DATA4_MARK, VI1_DATA5_MARK,
1689 VI1_DATA6_MARK, VI1_DATA7_MARK,
1690 VI1_DATA8_MARK, VI1_DATA9_MARK,
1691 VI1_DATA10_MARK, VI1_DATA11_MARK,
1692 },
1693 };
1694 static const unsigned int vin1_sync_pins[] = {
1695 /* HSYNC#, VSYNC# */
1696 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1697 };
1698 static const unsigned int vin1_sync_mux[] = {
1699 VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
1700 };
1701 static const unsigned int vin1_field_pins[] = {
1702 RCAR_GP_PIN(3, 16),
1703 };
1704 static const unsigned int vin1_field_mux[] = {
1705 /* FIELD */
1706 VI1_FIELD_MARK,
1707 };
1708 static const unsigned int vin1_clkenb_pins[] = {
1709 RCAR_GP_PIN(3, 1),
1710 };
1711 static const unsigned int vin1_clkenb_mux[] = {
1712 /* CLKENB */
1713 VI1_CLKENB_MARK,
1714 };
1715 static const unsigned int vin1_clk_pins[] = {
1716 RCAR_GP_PIN(3, 0),
1717 };
1718 static const unsigned int vin1_clk_mux[] = {
1719 /* CLK */
1720 VI1_CLK_MARK,
1721 };
1722
1723 static const struct sh_pfc_pin_group pinmux_groups[] = {
1724 SH_PFC_PIN_GROUP(avb0_link),
1725 SH_PFC_PIN_GROUP(avb0_magic),
1726 SH_PFC_PIN_GROUP(avb0_phy_int),
1727 SH_PFC_PIN_GROUP(avb0_mdio),
1728 SH_PFC_PIN_GROUP(avb0_rgmii),
1729 SH_PFC_PIN_GROUP(avb0_txcrefclk),
1730 SH_PFC_PIN_GROUP(avb0_avtp_pps),
1731 SH_PFC_PIN_GROUP(avb0_avtp_capture),
1732 SH_PFC_PIN_GROUP(avb0_avtp_match),
1733 SH_PFC_PIN_GROUP(canfd_clk_a),
1734 SH_PFC_PIN_GROUP(canfd_clk_b),
1735 SH_PFC_PIN_GROUP(canfd0_data_a),
1736 SH_PFC_PIN_GROUP(canfd0_data_b),
1737 SH_PFC_PIN_GROUP(canfd1_data),
1738 SH_PFC_PIN_GROUP(du_rgb666),
1739 SH_PFC_PIN_GROUP(du_clk_out),
1740 SH_PFC_PIN_GROUP(du_sync),
1741 SH_PFC_PIN_GROUP(du_oddf),
1742 SH_PFC_PIN_GROUP(du_cde),
1743 SH_PFC_PIN_GROUP(du_disp),
1744 SH_PFC_PIN_GROUP(hscif0_data),
1745 SH_PFC_PIN_GROUP(hscif0_clk),
1746 SH_PFC_PIN_GROUP(hscif0_ctrl),
1747 SH_PFC_PIN_GROUP(hscif1_data),
1748 SH_PFC_PIN_GROUP(hscif1_clk),
1749 SH_PFC_PIN_GROUP(hscif1_ctrl),
1750 SH_PFC_PIN_GROUP(hscif2_data),
1751 SH_PFC_PIN_GROUP(hscif2_clk),
1752 SH_PFC_PIN_GROUP(hscif2_ctrl),
1753 SH_PFC_PIN_GROUP(hscif3_data),
1754 SH_PFC_PIN_GROUP(hscif3_clk),
1755 SH_PFC_PIN_GROUP(hscif3_ctrl),
1756 SH_PFC_PIN_GROUP(i2c0),
1757 SH_PFC_PIN_GROUP(i2c1),
1758 SH_PFC_PIN_GROUP(i2c2),
1759 SH_PFC_PIN_GROUP(i2c3_a),
1760 SH_PFC_PIN_GROUP(i2c3_b),
1761 SH_PFC_PIN_GROUP(i2c4),
1762 SH_PFC_PIN_GROUP(intc_ex_irq0),
1763 SH_PFC_PIN_GROUP(intc_ex_irq1),
1764 SH_PFC_PIN_GROUP(intc_ex_irq2),
1765 SH_PFC_PIN_GROUP(intc_ex_irq3),
1766 SH_PFC_PIN_GROUP(intc_ex_irq4),
1767 SH_PFC_PIN_GROUP(intc_ex_irq5),
1768 SH_PFC_PIN_GROUP(mmc_data1),
1769 SH_PFC_PIN_GROUP(mmc_data4),
1770 SH_PFC_PIN_GROUP(mmc_data8),
1771 SH_PFC_PIN_GROUP(mmc_ctrl),
1772 SH_PFC_PIN_GROUP(msiof0_clk),
1773 SH_PFC_PIN_GROUP(msiof0_sync),
1774 SH_PFC_PIN_GROUP(msiof0_ss1),
1775 SH_PFC_PIN_GROUP(msiof0_ss2),
1776 SH_PFC_PIN_GROUP(msiof0_txd),
1777 SH_PFC_PIN_GROUP(msiof0_rxd),
1778 SH_PFC_PIN_GROUP(msiof1_clk),
1779 SH_PFC_PIN_GROUP(msiof1_sync),
1780 SH_PFC_PIN_GROUP(msiof1_ss1),
1781 SH_PFC_PIN_GROUP(msiof1_ss2),
1782 SH_PFC_PIN_GROUP(msiof1_txd),
1783 SH_PFC_PIN_GROUP(msiof1_rxd),
1784 SH_PFC_PIN_GROUP(msiof2_clk),
1785 SH_PFC_PIN_GROUP(msiof2_sync),
1786 SH_PFC_PIN_GROUP(msiof2_ss1),
1787 SH_PFC_PIN_GROUP(msiof2_ss2),
1788 SH_PFC_PIN_GROUP(msiof2_txd),
1789 SH_PFC_PIN_GROUP(msiof2_rxd),
1790 SH_PFC_PIN_GROUP(msiof3_clk),
1791 SH_PFC_PIN_GROUP(msiof3_sync),
1792 SH_PFC_PIN_GROUP(msiof3_ss1),
1793 SH_PFC_PIN_GROUP(msiof3_ss2),
1794 SH_PFC_PIN_GROUP(msiof3_txd),
1795 SH_PFC_PIN_GROUP(msiof3_rxd),
1796 SH_PFC_PIN_GROUP(pwm0_a),
1797 SH_PFC_PIN_GROUP(pwm0_b),
1798 SH_PFC_PIN_GROUP(pwm1_a),
1799 SH_PFC_PIN_GROUP(pwm1_b),
1800 SH_PFC_PIN_GROUP(pwm2_a),
1801 SH_PFC_PIN_GROUP(pwm2_b),
1802 SH_PFC_PIN_GROUP(pwm3_a),
1803 SH_PFC_PIN_GROUP(pwm3_b),
1804 SH_PFC_PIN_GROUP(pwm4_a),
1805 SH_PFC_PIN_GROUP(pwm4_b),
1806 SH_PFC_PIN_GROUP(qspi0_ctrl),
1807 SH_PFC_PIN_GROUP(qspi0_data2),
1808 SH_PFC_PIN_GROUP(qspi0_data4),
1809 SH_PFC_PIN_GROUP(qspi1_ctrl),
1810 SH_PFC_PIN_GROUP(qspi1_data2),
1811 SH_PFC_PIN_GROUP(qspi1_data4),
1812 SH_PFC_PIN_GROUP(rpc_clk1),
1813 SH_PFC_PIN_GROUP(rpc_clk2),
1814 SH_PFC_PIN_GROUP(rpc_ctrl),
1815 SH_PFC_PIN_GROUP(rpc_data),
1816 SH_PFC_PIN_GROUP(rpc_reset),
1817 SH_PFC_PIN_GROUP(rpc_int),
1818 SH_PFC_PIN_GROUP(rpc_wp),
1819 SH_PFC_PIN_GROUP(scif_clk_a),
1820 SH_PFC_PIN_GROUP(scif_clk_b),
1821 SH_PFC_PIN_GROUP(scif0_data),
1822 SH_PFC_PIN_GROUP(scif0_clk),
1823 SH_PFC_PIN_GROUP(scif0_ctrl),
1824 SH_PFC_PIN_GROUP(scif1_data_a),
1825 SH_PFC_PIN_GROUP(scif1_clk),
1826 SH_PFC_PIN_GROUP(scif1_ctrl),
1827 SH_PFC_PIN_GROUP(scif1_data_b),
1828 SH_PFC_PIN_GROUP(scif3_data),
1829 SH_PFC_PIN_GROUP(scif3_clk),
1830 SH_PFC_PIN_GROUP(scif3_ctrl),
1831 SH_PFC_PIN_GROUP(scif4_data),
1832 SH_PFC_PIN_GROUP(scif4_clk),
1833 SH_PFC_PIN_GROUP(scif4_ctrl),
1834 SH_PFC_PIN_GROUP(tmu_tclk1_a),
1835 SH_PFC_PIN_GROUP(tmu_tclk1_b),
1836 SH_PFC_PIN_GROUP(tmu_tclk2_a),
1837 SH_PFC_PIN_GROUP(tmu_tclk2_b),
1838 VIN_DATA_PIN_GROUP(vin0_data, 8),
1839 VIN_DATA_PIN_GROUP(vin0_data, 10),
1840 VIN_DATA_PIN_GROUP(vin0_data, 12),
1841 SH_PFC_PIN_GROUP(vin0_sync),
1842 SH_PFC_PIN_GROUP(vin0_field),
1843 SH_PFC_PIN_GROUP(vin0_clkenb),
1844 SH_PFC_PIN_GROUP(vin0_clk),
1845 VIN_DATA_PIN_GROUP(vin1_data, 8),
1846 VIN_DATA_PIN_GROUP(vin1_data, 10),
1847 VIN_DATA_PIN_GROUP(vin1_data, 12),
1848 SH_PFC_PIN_GROUP(vin1_sync),
1849 SH_PFC_PIN_GROUP(vin1_field),
1850 SH_PFC_PIN_GROUP(vin1_clkenb),
1851 SH_PFC_PIN_GROUP(vin1_clk),
1852 };
1853
1854 static const char * const avb0_groups[] = {
1855 "avb0_link",
1856 "avb0_magic",
1857 "avb0_phy_int",
1858 "avb0_mdio",
1859 "avb0_rgmii",
1860 "avb0_txcrefclk",
1861 "avb0_avtp_pps",
1862 "avb0_avtp_capture",
1863 "avb0_avtp_match",
1864 };
1865
1866 static const char * const canfd_clk_groups[] = {
1867 "canfd_clk_a",
1868 "canfd_clk_b",
1869 };
1870
1871 static const char * const canfd0_groups[] = {
1872 "canfd0_data_a",
1873 "canfd0_data_b",
1874 };
1875
1876 static const char * const canfd1_groups[] = {
1877 "canfd1_data",
1878 };
1879
1880 static const char * const du_groups[] = {
1881 "du_rgb666",
1882 "du_clk_out",
1883 "du_sync",
1884 "du_oddf",
1885 "du_cde",
1886 "du_disp",
1887 };
1888
1889 static const char * const hscif0_groups[] = {
1890 "hscif0_data",
1891 "hscif0_clk",
1892 "hscif0_ctrl",
1893 };
1894
1895 static const char * const hscif1_groups[] = {
1896 "hscif1_data",
1897 "hscif1_clk",
1898 "hscif1_ctrl",
1899 };
1900
1901 static const char * const hscif2_groups[] = {
1902 "hscif2_data",
1903 "hscif2_clk",
1904 "hscif2_ctrl",
1905 };
1906
1907 static const char * const hscif3_groups[] = {
1908 "hscif3_data",
1909 "hscif3_clk",
1910 "hscif3_ctrl",
1911 };
1912
1913 static const char * const i2c0_groups[] = {
1914 "i2c0",
1915 };
1916
1917 static const char * const i2c1_groups[] = {
1918 "i2c1",
1919 };
1920
1921 static const char * const i2c2_groups[] = {
1922 "i2c2",
1923 };
1924
1925 static const char * const i2c3_groups[] = {
1926 "i2c3_a",
1927 "i2c3_b",
1928 };
1929
1930 static const char * const i2c4_groups[] = {
1931 "i2c4",
1932 };
1933
1934 static const char * const intc_ex_groups[] = {
1935 "intc_ex_irq0",
1936 "intc_ex_irq1",
1937 "intc_ex_irq2",
1938 "intc_ex_irq3",
1939 "intc_ex_irq4",
1940 "intc_ex_irq5",
1941 };
1942
1943 static const char * const mmc_groups[] = {
1944 "mmc_data1",
1945 "mmc_data4",
1946 "mmc_data8",
1947 "mmc_ctrl",
1948 };
1949
1950 static const char * const msiof0_groups[] = {
1951 "msiof0_clk",
1952 "msiof0_sync",
1953 "msiof0_ss1",
1954 "msiof0_ss2",
1955 "msiof0_txd",
1956 "msiof0_rxd",
1957 };
1958
1959 static const char * const msiof1_groups[] = {
1960 "msiof1_clk",
1961 "msiof1_sync",
1962 "msiof1_ss1",
1963 "msiof1_ss2",
1964 "msiof1_txd",
1965 "msiof1_rxd",
1966 };
1967
1968 static const char * const msiof2_groups[] = {
1969 "msiof2_clk",
1970 "msiof2_sync",
1971 "msiof2_ss1",
1972 "msiof2_ss2",
1973 "msiof2_txd",
1974 "msiof2_rxd",
1975 };
1976
1977 static const char * const msiof3_groups[] = {
1978 "msiof3_clk",
1979 "msiof3_sync",
1980 "msiof3_ss1",
1981 "msiof3_ss2",
1982 "msiof3_txd",
1983 "msiof3_rxd",
1984 };
1985
1986 static const char * const pwm0_groups[] = {
1987 "pwm0_a",
1988 "pwm0_b",
1989 };
1990
1991 static const char * const pwm1_groups[] = {
1992 "pwm1_a",
1993 "pwm1_b",
1994 };
1995
1996 static const char * const pwm2_groups[] = {
1997 "pwm2_a",
1998 "pwm2_b",
1999 };
2000
2001 static const char * const pwm3_groups[] = {
2002 "pwm3_a",
2003 "pwm3_b",
2004 };
2005
2006 static const char * const pwm4_groups[] = {
2007 "pwm4_a",
2008 "pwm4_b",
2009 };
2010
2011 static const char * const qspi0_groups[] = {
2012 "qspi0_ctrl",
2013 "qspi0_data2",
2014 "qspi0_data4",
2015 };
2016
2017 static const char * const qspi1_groups[] = {
2018 "qspi1_ctrl",
2019 "qspi1_data2",
2020 "qspi1_data4",
2021 };
2022
2023 static const char * const rpc_groups[] = {
2024 "rpc_clk1",
2025 "rpc_clk2",
2026 "rpc_ctrl",
2027 "rpc_data",
2028 "rpc_reset",
2029 "rpc_int",
2030 "rpc_wp",
2031 };
2032
2033 static const char * const scif_clk_groups[] = {
2034 "scif_clk_a",
2035 "scif_clk_b",
2036 };
2037
2038 static const char * const scif0_groups[] = {
2039 "scif0_data",
2040 "scif0_clk",
2041 "scif0_ctrl",
2042 };
2043
2044 static const char * const scif1_groups[] = {
2045 "scif1_data_a",
2046 "scif1_clk",
2047 "scif1_ctrl",
2048 "scif1_data_b",
2049 };
2050
2051 static const char * const scif3_groups[] = {
2052 "scif3_data",
2053 "scif3_clk",
2054 "scif3_ctrl",
2055 };
2056
2057 static const char * const scif4_groups[] = {
2058 "scif4_data",
2059 "scif4_clk",
2060 "scif4_ctrl",
2061 };
2062
2063 static const char * const tmu_groups[] = {
2064 "tmu_tclk1_a",
2065 "tmu_tclk1_b",
2066 "tmu_tclk2_a",
2067 "tmu_tclk2_b",
2068 };
2069
2070 static const char * const vin0_groups[] = {
2071 "vin0_data8",
2072 "vin0_data10",
2073 "vin0_data12",
2074 "vin0_sync",
2075 "vin0_field",
2076 "vin0_clkenb",
2077 "vin0_clk",
2078 };
2079
2080 static const char * const vin1_groups[] = {
2081 "vin1_data8",
2082 "vin1_data10",
2083 "vin1_data12",
2084 "vin1_sync",
2085 "vin1_field",
2086 "vin1_clkenb",
2087 "vin1_clk",
2088 };
2089
2090 static const struct sh_pfc_function pinmux_functions[] = {
2091 SH_PFC_FUNCTION(avb0),
2092 SH_PFC_FUNCTION(canfd_clk),
2093 SH_PFC_FUNCTION(canfd0),
2094 SH_PFC_FUNCTION(canfd1),
2095 SH_PFC_FUNCTION(du),
2096 SH_PFC_FUNCTION(hscif0),
2097 SH_PFC_FUNCTION(hscif1),
2098 SH_PFC_FUNCTION(hscif2),
2099 SH_PFC_FUNCTION(hscif3),
2100 SH_PFC_FUNCTION(i2c0),
2101 SH_PFC_FUNCTION(i2c1),
2102 SH_PFC_FUNCTION(i2c2),
2103 SH_PFC_FUNCTION(i2c3),
2104 SH_PFC_FUNCTION(i2c4),
2105 SH_PFC_FUNCTION(intc_ex),
2106 SH_PFC_FUNCTION(mmc),
2107 SH_PFC_FUNCTION(msiof0),
2108 SH_PFC_FUNCTION(msiof1),
2109 SH_PFC_FUNCTION(msiof2),
2110 SH_PFC_FUNCTION(msiof3),
2111 SH_PFC_FUNCTION(pwm0),
2112 SH_PFC_FUNCTION(pwm1),
2113 SH_PFC_FUNCTION(pwm2),
2114 SH_PFC_FUNCTION(pwm3),
2115 SH_PFC_FUNCTION(pwm4),
2116 SH_PFC_FUNCTION(qspi0),
2117 SH_PFC_FUNCTION(qspi1),
2118 SH_PFC_FUNCTION(rpc),
2119 SH_PFC_FUNCTION(scif_clk),
2120 SH_PFC_FUNCTION(scif0),
2121 SH_PFC_FUNCTION(scif1),
2122 SH_PFC_FUNCTION(scif3),
2123 SH_PFC_FUNCTION(scif4),
2124 SH_PFC_FUNCTION(tmu),
2125 SH_PFC_FUNCTION(vin0),
2126 SH_PFC_FUNCTION(vin1),
2127 };
2128
2129 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2130 #define F_(x, y) FN_##y
2131 #define FM(x) FN_##x
2132 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
2133 0, 0,
2134 0, 0,
2135 0, 0,
2136 0, 0,
2137 0, 0,
2138 0, 0,
2139 0, 0,
2140 0, 0,
2141 0, 0,
2142 0, 0,
2143 GP_0_21_FN, GPSR0_21,
2144 GP_0_20_FN, GPSR0_20,
2145 GP_0_19_FN, GPSR0_19,
2146 GP_0_18_FN, GPSR0_18,
2147 GP_0_17_FN, GPSR0_17,
2148 GP_0_16_FN, GPSR0_16,
2149 GP_0_15_FN, GPSR0_15,
2150 GP_0_14_FN, GPSR0_14,
2151 GP_0_13_FN, GPSR0_13,
2152 GP_0_12_FN, GPSR0_12,
2153 GP_0_11_FN, GPSR0_11,
2154 GP_0_10_FN, GPSR0_10,
2155 GP_0_9_FN, GPSR0_9,
2156 GP_0_8_FN, GPSR0_8,
2157 GP_0_7_FN, GPSR0_7,
2158 GP_0_6_FN, GPSR0_6,
2159 GP_0_5_FN, GPSR0_5,
2160 GP_0_4_FN, GPSR0_4,
2161 GP_0_3_FN, GPSR0_3,
2162 GP_0_2_FN, GPSR0_2,
2163 GP_0_1_FN, GPSR0_1,
2164 GP_0_0_FN, GPSR0_0, ))
2165 },
2166 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
2167 0, 0,
2168 0, 0,
2169 0, 0,
2170 0, 0,
2171 GP_1_27_FN, GPSR1_27,
2172 GP_1_26_FN, GPSR1_26,
2173 GP_1_25_FN, GPSR1_25,
2174 GP_1_24_FN, GPSR1_24,
2175 GP_1_23_FN, GPSR1_23,
2176 GP_1_22_FN, GPSR1_22,
2177 GP_1_21_FN, GPSR1_21,
2178 GP_1_20_FN, GPSR1_20,
2179 GP_1_19_FN, GPSR1_19,
2180 GP_1_18_FN, GPSR1_18,
2181 GP_1_17_FN, GPSR1_17,
2182 GP_1_16_FN, GPSR1_16,
2183 GP_1_15_FN, GPSR1_15,
2184 GP_1_14_FN, GPSR1_14,
2185 GP_1_13_FN, GPSR1_13,
2186 GP_1_12_FN, GPSR1_12,
2187 GP_1_11_FN, GPSR1_11,
2188 GP_1_10_FN, GPSR1_10,
2189 GP_1_9_FN, GPSR1_9,
2190 GP_1_8_FN, GPSR1_8,
2191 GP_1_7_FN, GPSR1_7,
2192 GP_1_6_FN, GPSR1_6,
2193 GP_1_5_FN, GPSR1_5,
2194 GP_1_4_FN, GPSR1_4,
2195 GP_1_3_FN, GPSR1_3,
2196 GP_1_2_FN, GPSR1_2,
2197 GP_1_1_FN, GPSR1_1,
2198 GP_1_0_FN, GPSR1_0, ))
2199 },
2200 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
2201 0, 0,
2202 0, 0,
2203 0, 0,
2204 0, 0,
2205 0, 0,
2206 0, 0,
2207 0, 0,
2208 0, 0,
2209 0, 0,
2210 0, 0,
2211 0, 0,
2212 0, 0,
2213 0, 0,
2214 0, 0,
2215 0, 0,
2216 GP_2_16_FN, GPSR2_16,
2217 GP_2_15_FN, GPSR2_15,
2218 GP_2_14_FN, GPSR2_14,
2219 GP_2_13_FN, GPSR2_13,
2220 GP_2_12_FN, GPSR2_12,
2221 GP_2_11_FN, GPSR2_11,
2222 GP_2_10_FN, GPSR2_10,
2223 GP_2_9_FN, GPSR2_9,
2224 GP_2_8_FN, GPSR2_8,
2225 GP_2_7_FN, GPSR2_7,
2226 GP_2_6_FN, GPSR2_6,
2227 GP_2_5_FN, GPSR2_5,
2228 GP_2_4_FN, GPSR2_4,
2229 GP_2_3_FN, GPSR2_3,
2230 GP_2_2_FN, GPSR2_2,
2231 GP_2_1_FN, GPSR2_1,
2232 GP_2_0_FN, GPSR2_0, ))
2233 },
2234 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
2235 0, 0,
2236 0, 0,
2237 0, 0,
2238 0, 0,
2239 0, 0,
2240 0, 0,
2241 0, 0,
2242 0, 0,
2243 0, 0,
2244 0, 0,
2245 0, 0,
2246 0, 0,
2247 0, 0,
2248 0, 0,
2249 0, 0,
2250 GP_3_16_FN, GPSR3_16,
2251 GP_3_15_FN, GPSR3_15,
2252 GP_3_14_FN, GPSR3_14,
2253 GP_3_13_FN, GPSR3_13,
2254 GP_3_12_FN, GPSR3_12,
2255 GP_3_11_FN, GPSR3_11,
2256 GP_3_10_FN, GPSR3_10,
2257 GP_3_9_FN, GPSR3_9,
2258 GP_3_8_FN, GPSR3_8,
2259 GP_3_7_FN, GPSR3_7,
2260 GP_3_6_FN, GPSR3_6,
2261 GP_3_5_FN, GPSR3_5,
2262 GP_3_4_FN, GPSR3_4,
2263 GP_3_3_FN, GPSR3_3,
2264 GP_3_2_FN, GPSR3_2,
2265 GP_3_1_FN, GPSR3_1,
2266 GP_3_0_FN, GPSR3_0, ))
2267 },
2268 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
2269 0, 0,
2270 0, 0,
2271 0, 0,
2272 0, 0,
2273 0, 0,
2274 0, 0,
2275 0, 0,
2276 0, 0,
2277 0, 0,
2278 0, 0,
2279 0, 0,
2280 0, 0,
2281 0, 0,
2282 0, 0,
2283 0, 0,
2284 0, 0,
2285 0, 0,
2286 0, 0,
2287 0, 0,
2288 0, 0,
2289 0, 0,
2290 0, 0,
2291 0, 0,
2292 0, 0,
2293 0, 0,
2294 0, 0,
2295 GP_4_5_FN, GPSR4_5,
2296 GP_4_4_FN, GPSR4_4,
2297 GP_4_3_FN, GPSR4_3,
2298 GP_4_2_FN, GPSR4_2,
2299 GP_4_1_FN, GPSR4_1,
2300 GP_4_0_FN, GPSR4_0, ))
2301 },
2302 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
2303 0, 0,
2304 0, 0,
2305 0, 0,
2306 0, 0,
2307 0, 0,
2308 0, 0,
2309 0, 0,
2310 0, 0,
2311 0, 0,
2312 0, 0,
2313 0, 0,
2314 0, 0,
2315 0, 0,
2316 0, 0,
2317 0, 0,
2318 0, 0,
2319 0, 0,
2320 GP_5_14_FN, GPSR5_14,
2321 GP_5_13_FN, GPSR5_13,
2322 GP_5_12_FN, GPSR5_12,
2323 GP_5_11_FN, GPSR5_11,
2324 GP_5_10_FN, GPSR5_10,
2325 GP_5_9_FN, GPSR5_9,
2326 GP_5_8_FN, GPSR5_8,
2327 GP_5_7_FN, GPSR5_7,
2328 GP_5_6_FN, GPSR5_6,
2329 GP_5_5_FN, GPSR5_5,
2330 GP_5_4_FN, GPSR5_4,
2331 GP_5_3_FN, GPSR5_3,
2332 GP_5_2_FN, GPSR5_2,
2333 GP_5_1_FN, GPSR5_1,
2334 GP_5_0_FN, GPSR5_0, ))
2335 },
2336 #undef F_
2337 #undef FM
2338
2339 #define F_(x, y) x,
2340 #define FM(x) FN_##x,
2341 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
2342 IP0_31_28
2343 IP0_27_24
2344 IP0_23_20
2345 IP0_19_16
2346 IP0_15_12
2347 IP0_11_8
2348 IP0_7_4
2349 IP0_3_0 ))
2350 },
2351 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
2352 IP1_31_28
2353 IP1_27_24
2354 IP1_23_20
2355 IP1_19_16
2356 IP1_15_12
2357 IP1_11_8
2358 IP1_7_4
2359 IP1_3_0 ))
2360 },
2361 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
2362 IP2_31_28
2363 IP2_27_24
2364 IP2_23_20
2365 IP2_19_16
2366 IP2_15_12
2367 IP2_11_8
2368 IP2_7_4
2369 IP2_3_0 ))
2370 },
2371 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
2372 IP3_31_28
2373 IP3_27_24
2374 IP3_23_20
2375 IP3_19_16
2376 IP3_15_12
2377 IP3_11_8
2378 IP3_7_4
2379 IP3_3_0 ))
2380 },
2381 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
2382 IP4_31_28
2383 IP4_27_24
2384 IP4_23_20
2385 IP4_19_16
2386 IP4_15_12
2387 IP4_11_8
2388 IP4_7_4
2389 IP4_3_0 ))
2390 },
2391 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
2392 IP5_31_28
2393 IP5_27_24
2394 IP5_23_20
2395 IP5_19_16
2396 IP5_15_12
2397 IP5_11_8
2398 IP5_7_4
2399 IP5_3_0 ))
2400 },
2401 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
2402 IP6_31_28
2403 IP6_27_24
2404 IP6_23_20
2405 IP6_19_16
2406 IP6_15_12
2407 IP6_11_8
2408 IP6_7_4
2409 IP6_3_0 ))
2410 },
2411 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
2412 IP7_31_28
2413 IP7_27_24
2414 IP7_23_20
2415 IP7_19_16
2416 IP7_15_12
2417 IP7_11_8
2418 IP7_7_4
2419 IP7_3_0 ))
2420 },
2421 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
2422 IP8_31_28
2423 IP8_27_24
2424 IP8_23_20
2425 IP8_19_16
2426 IP8_15_12
2427 IP8_11_8
2428 IP8_7_4
2429 IP8_3_0 ))
2430 },
2431 #undef F_
2432 #undef FM
2433
2434 #define F_(x, y) x,
2435 #define FM(x) FN_##x,
2436 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2437 GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1,
2438 1, 1, 1, 1, 1),
2439 GROUP(
2440 /* RESERVED 31, 30, 29, 28 */
2441 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2442 /* RESERVED 27, 26, 25, 24 */
2443 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2444 /* RESERVED 23, 22, 21, 20 */
2445 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2446 /* RESERVED 19, 18, 17, 16 */
2447 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2448 /* RESERVED 15, 14, 13, 12 */
2449 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2450 MOD_SEL0_11
2451 MOD_SEL0_10
2452 MOD_SEL0_9
2453 MOD_SEL0_8
2454 MOD_SEL0_7
2455 MOD_SEL0_6
2456 MOD_SEL0_5
2457 MOD_SEL0_4
2458 MOD_SEL0_3
2459 MOD_SEL0_2
2460 MOD_SEL0_1
2461 MOD_SEL0_0 ))
2462 },
2463 { },
2464 };
2465
2466 enum ioctrl_regs {
2467 POCCTRL0,
2468 POCCTRL1,
2469 POCCTRL2,
2470 TDSELCTRL,
2471 };
2472
2473 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
2474 [POCCTRL0] = { 0xe6060380 },
2475 [POCCTRL1] = { 0xe6060384 },
2476 [POCCTRL2] = { 0xe6060388 },
2477 [TDSELCTRL] = { 0xe60603c0, },
2478 { /* sentinel */ },
2479 };
2480
r8a77970_pin_to_pocctrl(struct sh_pfc * pfc,unsigned int pin,u32 * pocctrl)2481 static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
2482 u32 *pocctrl)
2483 {
2484 int bit = pin & 0x1f;
2485
2486 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
2487 if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
2488 return bit;
2489 if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
2490 return bit + 22;
2491
2492 *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
2493 if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
2494 return bit - 10;
2495 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
2496 return bit + 7;
2497
2498 return -EINVAL;
2499 }
2500
2501 static const struct sh_pfc_soc_operations pinmux_ops = {
2502 .pin_to_pocctrl = r8a77970_pin_to_pocctrl,
2503 };
2504
2505 const struct sh_pfc_soc_info r8a77970_pinmux_info = {
2506 .name = "r8a77970_pfc",
2507 .ops = &pinmux_ops,
2508 .unlock_reg = 0xe6060000, /* PMMR */
2509
2510 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2511
2512 .pins = pinmux_pins,
2513 .nr_pins = ARRAY_SIZE(pinmux_pins),
2514 .groups = pinmux_groups,
2515 .nr_groups = ARRAY_SIZE(pinmux_groups),
2516 .functions = pinmux_functions,
2517 .nr_functions = ARRAY_SIZE(pinmux_functions),
2518
2519 .cfg_regs = pinmux_config_regs,
2520 .ioctrl_regs = pinmux_ioctrl_regs,
2521
2522 .pinmux_data = pinmux_data,
2523 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2524 };
2525