1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 *  armboot - Startup Code for ARM926EJS CPU-core
4 *
5 *  Copyright (c) 2003  Texas Instruments
6 *
7 *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
8 *
9 *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
10 *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
11 *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
12 *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
13 *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
14 */
15
16
17#include <config.h>
18
19/*
20 *************************************************************************
21 *
22 * Startup Code (reset vector)
23 *
24 * The BootROM already initialized its own stack in the [0-0xb00] reserved
25 * range of the SRAM. The SPL (in _main) will update the stack pointer to
26 * its own SRAM area (right before the gd section).
27 *
28 *************************************************************************
29 */
30
31	.globl	reset
32	.globl	back_to_bootrom
33
34reset:
35	/*
36	* SPL has to return back to BootROM in a few cases (eg. Ethernet boot,
37	* UART boot, USB boot): save registers in BootROM's stack and then the
38	* BootROM's stack pointer in the SPL's data section.
39	*/
40	push	{r0-r12,lr}
41	ldr	r0, =bootrom_stash_sp
42	str	sp, [r0]
43
44	/*
45	 * Flush v4 I/D caches
46	 */
47	mov	r0, #0
48	mcr	p15, 0, r0, c7, c7, 0	/* Flush v3/v4 cache */
49	mcr	p15, 0, r0, c8, c7, 0	/* Flush v4 TLB */
50
51	/*
52	 * Enable instruction cache
53	 */
54	mrc	p15, 0, r0, c1, c0, 0
55	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
56	mcr	p15, 0, r0, c1, c0, 0
57
58	/*
59	 * Go setup Memory and board specific bits prior to relocation.
60	 * This call is not supposed to return.
61	 */
62	b	_main	/* _main will call board_init_f */
63
64back_to_bootrom:
65	pop	{r0-r12,pc}
66