1config RISCV_NDS
2	bool
3	select ARCH_EARLY_INIT_R
4	imply CPU
5	imply CPU_RISCV
6	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
7	imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
8	imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE)
9	imply SPL_CPU
10	imply SPL_OPENSBI
11	imply SPL_LOAD_FIT
12	help
13	  Run U-Boot on AndeStar V5 platforms and use some specific features
14	  which are provided by Andes Technology AndeStar V5 families.
15
16if RISCV_NDS
17
18config RISCV_NDS_CACHE
19	bool "AndeStar V5 families specific cache support"
20	depends on RISCV_MMODE || SPL_RISCV_MMODE
21	help
22	  Provide Andes Technology AndeStar V5 families specific cache support.
23
24endif
25