1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MediaTek clock driver for MT8512 SoC
4 *
5 * Copyright (C) 2019 BayLibre, SAS
6 * Author: Chen Zhong <chen.zhong@mediatek.com>
7 */
8
9 #include <common.h>
10 #include <dm.h>
11 #include <asm/io.h>
12 #include <dt-bindings/clock/mt8512-clk.h>
13 #include <linux/bitops.h>
14
15 #include "clk-mtk.h"
16
17 #define MT8512_PLL_FMAX (3800UL * MHZ)
18 #define MT8512_PLL_FMIN (1500UL * MHZ)
19 #define MT8512_CON0_RST_BAR BIT(23)
20
21 /* apmixedsys */
22 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
23 _pd_shift, _pcw_reg, _pcw_shift, _pcw_chg_reg) { \
24 .id = _id, \
25 .reg = _reg, \
26 .pwr_reg = _pwr_reg, \
27 .en_mask = _en_mask, \
28 .rst_bar_mask = MT8512_CON0_RST_BAR, \
29 .fmax = MT8512_PLL_FMAX, \
30 .fmin = MT8512_PLL_FMIN, \
31 .flags = _flags, \
32 .pcwbits = _pcwbits, \
33 .pcwibits = 8, \
34 .pd_reg = _pd_reg, \
35 .pd_shift = _pd_shift, \
36 .pcw_reg = _pcw_reg, \
37 .pcw_shift = _pcw_shift, \
38 .pcw_chg_reg = _pcw_chg_reg, \
39 }
40
41 static const struct mtk_pll_data apmixed_plls[] = {
42 PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x00000001,
43 0, 22, 0x0310, 24, 0x0310, 0, 0),
44 PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0x00000001,
45 HAVE_RST_BAR, 22, 0x022C, 24, 0x022C, 0, 0),
46 PLL(CLK_APMIXED_UNIVPLL2, 0x0208, 0x0214, 0x00000001,
47 HAVE_RST_BAR, 22, 0x020C, 24, 0x020C, 0, 0),
48 PLL(CLK_APMIXED_MSDCPLL, 0x0350, 0x035C, 0x00000001,
49 0, 22, 0x0354, 24, 0x0354, 0, 0),
50 PLL(CLK_APMIXED_APLL1, 0x031C, 0x032C, 0x00000001,
51 0, 32, 0x0320, 24, 0x0324, 0, 0x0320),
52 PLL(CLK_APMIXED_APLL2, 0x0360, 0x0370, 0x00000001,
53 0, 32, 0x0364, 24, 0x0368, 0, 0x0364),
54 PLL(CLK_APMIXED_IPPLL, 0x0374, 0x0380, 0x00000001,
55 0, 22, 0x0378, 24, 0x0378, 0, 0),
56 PLL(CLK_APMIXED_DSPPLL, 0x0390, 0x039C, 0x00000001,
57 0, 22, 0x0394, 24, 0x0394, 0, 0),
58 PLL(CLK_APMIXED_TCONPLL, 0x03A0, 0x03AC, 0x00000001,
59 0, 22, 0x03A4, 24, 0x03A4, 0, 0),
60 };
61
62 /* topckgen */
63 #define FACTOR0(_id, _parent, _mult, _div) \
64 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
65
66 #define FACTOR1(_id, _parent, _mult, _div) \
67 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
68
69 #define FACTOR2(_id, _parent, _mult, _div) \
70 FACTOR(_id, _parent, _mult, _div, 0)
71
72 static const struct mtk_fixed_clk top_fixed_clks[] = {
73 FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000),
74 FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000),
75 };
76
77 static const struct mtk_fixed_factor top_fixed_divs[] = {
78 FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4),
79 FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8),
80 FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16),
81 FACTOR0(CLK_TOP_SYSPLL1_D16, CLK_APMIXED_MAINPLL, 1, 32),
82 FACTOR0(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
83 FACTOR0(CLK_TOP_SYSPLL2_D2, CLK_APMIXED_MAINPLL, 1, 6),
84 FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12),
85 FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24),
86 FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
87 FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20),
88 FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
89 FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14),
90 FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIVPLL2, 1, 2),
91 FACTOR1(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL, 1, 2),
92 FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4),
93 FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8),
94 FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16),
95 FACTOR1(CLK_TOP_UNIVPLL_D3, CLK_TOP_UNIVPLL, 1, 3),
96 FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6),
97 FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12),
98 FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24),
99 FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5),
100 FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10),
101 FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20),
102 FACTOR0(CLK_TOP_TCONPLL_D2, CLK_APMIXED_TCONPLL, 1, 2),
103 FACTOR0(CLK_TOP_TCONPLL_D4, CLK_APMIXED_TCONPLL, 1, 4),
104 FACTOR0(CLK_TOP_TCONPLL_D8, CLK_APMIXED_TCONPLL, 1, 8),
105 FACTOR0(CLK_TOP_TCONPLL_D16, CLK_APMIXED_TCONPLL, 1, 16),
106 FACTOR0(CLK_TOP_TCONPLL_D32, CLK_APMIXED_TCONPLL, 1, 32),
107 FACTOR0(CLK_TOP_TCONPLL_D64, CLK_APMIXED_TCONPLL, 1, 64),
108 FACTOR1(CLK_TOP_USB20_192M, CLK_TOP_UNIVPLL, 2, 13),
109 FACTOR1(CLK_TOP_USB20_192M_D2, CLK_TOP_USB20_192M, 1, 2),
110 FACTOR1(CLK_TOP_USB20_192M_D4_T, CLK_TOP_USB20_192M, 1, 4),
111 FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1),
112 FACTOR0(CLK_TOP_APLL1_D2, CLK_APMIXED_APLL1, 1, 2),
113 FACTOR0(CLK_TOP_APLL1_D3, CLK_APMIXED_APLL1, 1, 3),
114 FACTOR0(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4),
115 FACTOR0(CLK_TOP_APLL1_D8, CLK_APMIXED_APLL1, 1, 8),
116 FACTOR0(CLK_TOP_APLL1_D16, CLK_APMIXED_APLL1, 1, 16),
117 FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1),
118 FACTOR0(CLK_TOP_APLL2_D2, CLK_APMIXED_APLL2, 1, 2),
119 FACTOR0(CLK_TOP_APLL2_D3, CLK_APMIXED_APLL2, 1, 3),
120 FACTOR0(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4),
121 FACTOR0(CLK_TOP_APLL2_D8, CLK_APMIXED_APLL2, 1, 8),
122 FACTOR0(CLK_TOP_APLL2_D16, CLK_APMIXED_APLL2, 1, 16),
123 FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1),
124 FACTOR2(CLK_TOP_SYS_26M_D2, CLK_XTAL, 1, 2),
125 FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1),
126 FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2),
127 FACTOR0(CLK_TOP_DSPPLL, CLK_APMIXED_DSPPLL, 1, 1),
128 FACTOR0(CLK_TOP_DSPPLL_D2, CLK_APMIXED_DSPPLL, 1, 2),
129 FACTOR0(CLK_TOP_DSPPLL_D4, CLK_APMIXED_DSPPLL, 1, 4),
130 FACTOR0(CLK_TOP_DSPPLL_D8, CLK_APMIXED_DSPPLL, 1, 8),
131 FACTOR0(CLK_TOP_IPPLL, CLK_APMIXED_IPPLL, 1, 1),
132 FACTOR0(CLK_TOP_IPPLL_D2, CLK_APMIXED_IPPLL, 1, 2),
133 FACTOR1(CLK_TOP_NFI2X_CK_D2, CLK_TOP_NFI2X_SEL, 1, 2),
134 };
135
136 static const int axi_parents[] = {
137 CLK_TOP_CLK26M,
138 CLK_TOP_SYSPLL1_D4,
139 CLK_TOP_UNIVPLL3_D2,
140 CLK_TOP_SYSPLL1_D8,
141 CLK_TOP_SYS_26M_D2,
142 CLK_TOP_CLK32K
143 };
144
145 static const int mem_parents[] = {
146 CLK_TOP_DSPPLL,
147 CLK_TOP_IPPLL,
148 CLK_TOP_CLK26M,
149 CLK_TOP_UNIVPLL_D3
150 };
151
152 static const int uart_parents[] = {
153 CLK_TOP_CLK26M,
154 CLK_TOP_UNIVPLL2_D8
155 };
156
157 static const int spi_parents[] = {
158 CLK_TOP_CLK26M,
159 CLK_TOP_UNIVPLL2_D2,
160 CLK_TOP_SYSPLL2_D2,
161 CLK_TOP_UNIVPLL1_D4,
162 CLK_TOP_SYSPLL1_D4,
163 CLK_TOP_UNIVPLL3_D2,
164 CLK_TOP_UNIVPLL2_D4,
165 CLK_TOP_SYSPLL4_D2
166 };
167
168 static const int spis_parents[] = {
169 CLK_TOP_CLK26M,
170 CLK_TOP_UNIVPLL_D3,
171 CLK_TOP_SYSPLL_D3,
172 CLK_TOP_UNIVPLL1_D2,
173 CLK_TOP_UNIVPLL2_D2,
174 CLK_TOP_UNIVPLL1_D4,
175 CLK_TOP_UNIVPLL2_D4,
176 CLK_TOP_SYSPLL4_D2
177 };
178
179 static const int msdc50_0_hc_parents[] = {
180 CLK_TOP_CLK26M,
181 CLK_TOP_SYSPLL1_D2,
182 CLK_TOP_UNIVPLL1_D4,
183 CLK_TOP_SYSPLL2_D2
184 };
185
186 static const int msdc50_0_parents[] = {
187 CLK_TOP_CLK26M,
188 CLK_TOP_MSDCPLL_D2,
189 CLK_TOP_UNIVPLL2_D2,
190 CLK_TOP_SYSPLL2_D2,
191 CLK_TOP_UNIVPLL1_D4,
192 CLK_TOP_SYSPLL1_D4,
193 CLK_TOP_SYSPLL2_D4,
194 CLK_TOP_UNIVPLL2_D8
195 };
196
197 static const int msdc50_2_parents[] = {
198 CLK_TOP_CLK26M,
199 CLK_TOP_MSDCPLL,
200 CLK_TOP_UNIVPLL_D3,
201 CLK_TOP_UNIVPLL1_D2,
202 CLK_TOP_SYSPLL1_D2,
203 CLK_TOP_UNIVPLL2_D2,
204 CLK_TOP_SYSPLL2_D2,
205 CLK_TOP_UNIVPLL1_D4
206 };
207
208 static const int audio_parents[] = {
209 CLK_TOP_CLK26M,
210 CLK_TOP_UNIVPLL2_D8,
211 CLK_TOP_APLL1_D4,
212 CLK_TOP_APLL2_D4
213 };
214
215 static const int aud_intbus_parents[] = {
216 CLK_TOP_CLK26M,
217 CLK_TOP_SYSPLL1_D4,
218 CLK_TOP_UNIVPLL3_D2,
219 CLK_TOP_APLL2_D8,
220 CLK_TOP_SYS_26M_D2,
221 CLK_TOP_APLL1_D8,
222 CLK_TOP_UNIVPLL3_D4
223 };
224
225 static const int hapll1_parents[] = {
226 CLK_TOP_CLK26M,
227 CLK_TOP_APLL1,
228 CLK_TOP_APLL1_D2,
229 CLK_TOP_APLL1_D3,
230 CLK_TOP_APLL1_D4,
231 CLK_TOP_APLL1_D8,
232 CLK_TOP_APLL1_D16,
233 CLK_TOP_SYS_26M_D2
234 };
235
236 static const int hapll2_parents[] = {
237 CLK_TOP_CLK26M,
238 CLK_TOP_APLL2,
239 CLK_TOP_APLL2_D2,
240 CLK_TOP_APLL2_D3,
241 CLK_TOP_APLL2_D4,
242 CLK_TOP_APLL2_D8,
243 CLK_TOP_APLL2_D16,
244 CLK_TOP_SYS_26M_D2
245 };
246
247 static const int asm_l_parents[] = {
248 CLK_TOP_CLK26M,
249 CLK_TOP_UNIVPLL2_D4,
250 CLK_TOP_UNIVPLL2_D2,
251 CLK_TOP_SYSPLL_D5
252 };
253
254 static const int aud_spdif_parents[] = {
255 CLK_TOP_CLK26M,
256 CLK_TOP_UNIVPLL_D2,
257 CLK_TOP_DSPPLL
258 };
259
260 static const int aud_1_parents[] = {
261 CLK_TOP_CLK26M,
262 CLK_TOP_APLL1
263 };
264
265 static const int aud_2_parents[] = {
266 CLK_TOP_CLK26M,
267 CLK_TOP_APLL2
268 };
269
270 static const int ssusb_sys_parents[] = {
271 CLK_TOP_CLK26M,
272 CLK_TOP_UNIVPLL3_D4,
273 CLK_TOP_UNIVPLL2_D4,
274 CLK_TOP_UNIVPLL3_D2
275 };
276
277 static const int spm_parents[] = {
278 CLK_TOP_CLK26M,
279 CLK_TOP_SYSPLL1_D8
280 };
281
282 static const int i2c_parents[] = {
283 CLK_TOP_CLK26M,
284 CLK_TOP_SYS_26M_D2,
285 CLK_TOP_UNIVPLL3_D4,
286 CLK_TOP_UNIVPLL3_D2,
287 CLK_TOP_SYSPLL1_D8,
288 CLK_TOP_SYSPLL2_D8,
289 CLK_TOP_CLK32K
290 };
291
292 static const int pwm_parents[] = {
293 CLK_TOP_CLK26M,
294 CLK_TOP_UNIVPLL3_D4,
295 CLK_TOP_SYSPLL1_D8,
296 CLK_TOP_UNIVPLL2_D4,
297 CLK_TOP_SYS_26M_D2,
298 CLK_TOP_CLK32K
299 };
300
301 static const int dsp_parents[] = {
302 CLK_TOP_CLK26M,
303 CLK_TOP_DSPPLL,
304 CLK_TOP_DSPPLL_D2,
305 CLK_TOP_DSPPLL_D4,
306 CLK_TOP_DSPPLL_D8,
307 CLK_TOP_APLL2_D4,
308 CLK_TOP_SYS_26M_D2,
309 CLK_TOP_CLK32K
310 };
311
312 static const int nfi2x_parents[] = {
313 CLK_TOP_CLK26M,
314 CLK_TOP_SYSPLL2_D2,
315 CLK_TOP_SYSPLL_D7,
316 CLK_TOP_SYSPLL_D3,
317 CLK_TOP_SYSPLL2_D4,
318 CLK_TOP_MSDCPLL_D2,
319 CLK_TOP_UNIVPLL1_D2,
320 CLK_TOP_UNIVPLL_D5
321 };
322
323 static const int spinfi_parents[] = {
324 CLK_TOP_CLK26M,
325 CLK_TOP_UNIVPLL2_D8,
326 CLK_TOP_UNIVPLL3_D4,
327 CLK_TOP_SYSPLL1_D8,
328 CLK_TOP_SYSPLL4_D2,
329 CLK_TOP_SYSPLL2_D4,
330 CLK_TOP_UNIVPLL2_D4,
331 CLK_TOP_UNIVPLL3_D2
332 };
333
334 static const int ecc_parents[] = {
335 CLK_TOP_CLK26M,
336 CLK_TOP_SYSPLL_D5,
337 CLK_TOP_SYSPLL_D3,
338 CLK_TOP_UNIVPLL_D3
339 };
340
341 static const int gcpu_parents[] = {
342 CLK_TOP_CLK26M,
343 CLK_TOP_UNIVPLL_D3,
344 CLK_TOP_SYSPLL_D3,
345 CLK_TOP_UNIVPLL1_D2,
346 CLK_TOP_SYSPLL1_D2,
347 CLK_TOP_UNIVPLL2_D2
348 };
349
350 static const int gcpu_cpm_parents[] = {
351 CLK_TOP_CLK26M,
352 CLK_TOP_UNIVPLL2_D2,
353 CLK_TOP_SYSPLL2_D2,
354 CLK_TOP_UNIVPLL1_D4
355 };
356
357 static const int mbist_diag_parents[] = {
358 CLK_TOP_CLK26M,
359 CLK_TOP_SYS_26M_D2
360 };
361
362 static const int ip0_nna_parents[] = {
363 CLK_TOP_CLK26M,
364 CLK_TOP_DSPPLL,
365 CLK_TOP_DSPPLL_D2,
366 CLK_TOP_DSPPLL_D4,
367 CLK_TOP_IPPLL,
368 CLK_TOP_SYS_26M_D2,
369 CLK_TOP_IPPLL_D2,
370 CLK_TOP_MSDCPLL_D2
371 };
372
373 static const int ip2_wfst_parents[] = {
374 CLK_TOP_CLK26M,
375 CLK_TOP_UNIVPLL_D3,
376 CLK_TOP_UNIVPLL1_D2,
377 CLK_TOP_UNIVPLL2_D2,
378 CLK_TOP_IPPLL,
379 CLK_TOP_IPPLL_D2,
380 CLK_TOP_SYS_26M_D2,
381 CLK_TOP_MSDCPLL
382 };
383
384 static const int sflash_parents[] = {
385 CLK_TOP_CLK26M,
386 CLK_TOP_SYSPLL1_D16,
387 CLK_TOP_SYSPLL2_D8,
388 CLK_TOP_SYSPLL3_D4,
389 CLK_TOP_UNIVPLL3_D4,
390 CLK_TOP_UNIVPLL1_D8,
391 CLK_TOP_USB20_192M_D2,
392 CLK_TOP_UNIVPLL2_D4
393 };
394
395 static const int sram_parents[] = {
396 CLK_TOP_CLK26M,
397 CLK_TOP_DSPPLL,
398 CLK_TOP_UNIVPLL_D3,
399 CLK_TOP_SYSPLL1_D2,
400 CLK_TOP_APLL1,
401 CLK_TOP_APLL2,
402 CLK_TOP_SYSPLL1_D4,
403 CLK_TOP_SYS_26M_D2
404 };
405
406 static const int mm_parents[] = {
407 CLK_TOP_CLK26M,
408 CLK_TOP_SYSPLL_D3,
409 CLK_TOP_SYSPLL1_D2,
410 CLK_TOP_SYSPLL_D5,
411 CLK_TOP_SYSPLL1_D4,
412 CLK_TOP_UNIVPLL_D5,
413 CLK_TOP_UNIVPLL1_D2,
414 CLK_TOP_UNIVPLL_D3
415 };
416
417 static const int dpi0_parents[] = {
418 CLK_TOP_CLK26M,
419 CLK_TOP_TCONPLL_D2,
420 CLK_TOP_TCONPLL_D4,
421 CLK_TOP_TCONPLL_D8,
422 CLK_TOP_TCONPLL_D16,
423 CLK_TOP_TCONPLL_D32,
424 CLK_TOP_TCONPLL_D64
425 };
426
427 static const int dbg_atclk_parents[] = {
428 CLK_TOP_CLK26M,
429 CLK_TOP_UNIVPLL1_D2,
430 CLK_TOP_UNIVPLL_D5
431 };
432
433 static const int occ_104m_parents[] = {
434 CLK_TOP_UNIVPLL2_D4,
435 CLK_TOP_UNIVPLL2_D8
436 };
437
438 static const int occ_68m_parents[] = {
439 CLK_TOP_SYSPLL1_D8,
440 CLK_TOP_UNIVPLL2_D8
441 };
442
443 static const int occ_182m_parents[] = {
444 CLK_TOP_SYSPLL2_D2,
445 CLK_TOP_UNIVPLL1_D4,
446 CLK_TOP_UNIVPLL2_D8
447 };
448
449 static const struct mtk_composite top_muxes[] = {
450 /* CLK_CFG_0 */
451 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, axi_parents,
452 0x040, 0x044, 0x048, 0, 3, 7,
453 0x4, 0, CLK_MUX_SETCLR_UPD),
454 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, mem_parents,
455 0x040, 0x044, 0x048, 8, 2, 15,
456 0x4, 1, CLK_MUX_SETCLR_UPD),
457 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_UART_SEL, uart_parents,
458 0x040, 0x044, 0x048, 16, 1, 23,
459 0x4, 2, CLK_MUX_SETCLR_UPD),
460 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPI_SEL, spi_parents,
461 0x040, 0x044, 0x048, 24, 3, 31,
462 0x4, 3, CLK_MUX_SETCLR_UPD),
463 /* CLK_CFG_1 */
464 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPIS_SEL, spis_parents,
465 0x050, 0x054, 0x058, 0, 3, 7,
466 0x4, 4, CLK_MUX_SETCLR_UPD),
467 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HC_SEL, msdc50_0_hc_parents,
468 0x050, 0x054, 0x058, 8, 2, 15,
469 0x4, 5, CLK_MUX_SETCLR_UPD),
470 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC2_2_HC_SEL, msdc50_0_hc_parents,
471 0x050, 0x054, 0x058, 16, 2, 23,
472 0x4, 6, CLK_MUX_SETCLR_UPD),
473 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents,
474 0x050, 0x054, 0x058, 24, 3, 31,
475 0x4, 7, CLK_MUX_SETCLR_UPD),
476 /* CLK_CFG_2 */
477 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_2_SEL, msdc50_2_parents,
478 0x060, 0x064, 0x068, 0, 3, 7,
479 0x4, 8, CLK_MUX_SETCLR_UPD),
480 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, msdc50_0_parents,
481 0x060, 0x064, 0x068, 8, 3, 15,
482 0x4, 9, CLK_MUX_SETCLR_UPD),
483 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUDIO_SEL, audio_parents,
484 0x060, 0x064, 0x068, 16, 2, 23,
485 0x4, 10, CLK_MUX_SETCLR_UPD),
486 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents,
487 0x060, 0x064, 0x068, 24, 3, 31,
488 0x4, 11, CLK_MUX_SETCLR_UPD),
489 /* CLK_CFG_3 */
490 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_HAPLL1_SEL, hapll1_parents,
491 0x070, 0x074, 0x078, 0, 3, 7,
492 0x4, 12, CLK_MUX_SETCLR_UPD),
493 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_HAPLL2_SEL, hapll2_parents,
494 0x070, 0x074, 0x078, 8, 3, 15,
495 0x4, 13, CLK_MUX_SETCLR_UPD),
496 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_A2SYS_SEL, hapll1_parents,
497 0x070, 0x074, 0x078, 16, 3, 23,
498 0x4, 14, CLK_MUX_SETCLR_UPD),
499 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_A1SYS_SEL, hapll2_parents,
500 0x070, 0x074, 0x078, 24, 3, 31,
501 0x4, 15, CLK_MUX_SETCLR_UPD),
502 /* CLK_CFG_4 */
503 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_L_SEL, asm_l_parents,
504 0x080, 0x084, 0x088, 0, 2, 7,
505 0x4, 16, CLK_MUX_SETCLR_UPD),
506 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_M_SEL, asm_l_parents,
507 0x080, 0x084, 0x088, 8, 2, 15,
508 0x4, 17, CLK_MUX_SETCLR_UPD),
509 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_H_SEL, asm_l_parents,
510 0x080, 0x084, 0x088, 16, 2, 23,
511 0x4, 18, CLK_MUX_SETCLR_UPD),
512 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_SPDIF_SEL, aud_spdif_parents,
513 0x080, 0x084, 0x088, 24, 2, 31,
514 0x4, 19, CLK_MUX_SETCLR_UPD),
515 /* CLK_CFG_5 */
516 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_1_SEL, aud_1_parents,
517 0x090, 0x094, 0x098, 0, 1, 7,
518 0x4, 20, CLK_MUX_SETCLR_UPD),
519 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_2_SEL, aud_2_parents,
520 0x090, 0x094, 0x098, 8, 1, 15,
521 0x4, 21, CLK_MUX_SETCLR_UPD),
522 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SSUSB_SYS_SEL, ssusb_sys_parents,
523 0x090, 0x094, 0x098, 16, 2, 23,
524 0x4, 22, CLK_MUX_SETCLR_UPD),
525 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SSUSB_XHCI_SEL, ssusb_sys_parents,
526 0x090, 0x094, 0x098, 24, 2, 31,
527 0x4, 23, CLK_MUX_SETCLR_UPD),
528 /* CLK_CFG_6 */
529 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, spm_parents,
530 0x0a0, 0x0a4, 0x0a8, 0, 1, 7,
531 0x4, 24, CLK_MUX_SETCLR_UPD),
532 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_I2C_SEL, i2c_parents,
533 0x0a0, 0x0a4, 0x0a8, 8, 3, 15,
534 0x4, 25, CLK_MUX_SETCLR_UPD),
535 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_PWM_SEL, pwm_parents,
536 0x0a0, 0x0a4, 0x0a8, 16, 3, 23,
537 0x4, 26, CLK_MUX_SETCLR_UPD),
538 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DSP_SEL, dsp_parents,
539 0x0a0, 0x0a4, 0x0a8, 24, 3, 31,
540 0x4, 27, CLK_MUX_SETCLR_UPD),
541 /* CLK_CFG_7 */
542 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_NFI2X_SEL, nfi2x_parents,
543 0x0b0, 0x0b4, 0x0b8, 0, 3, 7,
544 0x4, 28, CLK_MUX_SETCLR_UPD),
545 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPINFI_SEL, spinfi_parents,
546 0x0b0, 0x0b4, 0x0b8, 8, 3, 15,
547 0x4, 29, CLK_MUX_SETCLR_UPD),
548 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ECC_SEL, ecc_parents,
549 0x0b0, 0x0b4, 0x0b8, 16, 2, 23,
550 0x4, 30, CLK_MUX_SETCLR_UPD),
551 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_GCPU_SEL, gcpu_parents,
552 0x0b0, 0x0b4, 0x0b8, 24, 3, 31,
553 0x4, 31, CLK_MUX_SETCLR_UPD),
554 /* CLK_CFG_8 */
555 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_GCPU_CPM_SEL, gcpu_cpm_parents,
556 0x0c0, 0x0c4, 0x0c8, 0, 2, 7,
557 0x8, 0, CLK_MUX_SETCLR_UPD),
558 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MBIST_DIAG_SEL, mbist_diag_parents,
559 0x0c0, 0x0c4, 0x0c8, 8, 1, 15,
560 0x8, 1, CLK_MUX_SETCLR_UPD),
561 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP0_NNA_SEL, ip0_nna_parents,
562 0x0c0, 0x0c4, 0x0c8, 16, 3, 23,
563 0x8, 2, CLK_MUX_SETCLR_UPD),
564 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP1_NNA_SEL, ip0_nna_parents,
565 0x0c0, 0x0c4, 0x0c8, 24, 3, 31,
566 0x8, 3, CLK_MUX_SETCLR_UPD),
567 /* CLK_CFG_9 */
568 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP2_WFST_SEL, ip2_wfst_parents,
569 0x0d0, 0x0d4, 0x0d8, 0, 3, 7,
570 0x8, 4, CLK_MUX_SETCLR_UPD),
571 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SFLASH_SEL, sflash_parents,
572 0x0d0, 0x0d4, 0x0d8, 8, 3, 15,
573 0x8, 5, CLK_MUX_SETCLR_UPD),
574 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SRAM_SEL, sram_parents,
575 0x0d0, 0x0d4, 0x0d8, 16, 3, 23,
576 0x8, 6, CLK_MUX_SETCLR_UPD),
577 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MM_SEL, mm_parents,
578 0x0d0, 0x0d4, 0x0d8, 24, 3, 31,
579 0x8, 7, CLK_MUX_SETCLR_UPD),
580 /* CLK_CFG_10 */
581 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DPI0_SEL, dpi0_parents,
582 0x0e0, 0x0e4, 0x0e8, 0, 3, 7,
583 0x8, 8, CLK_MUX_SETCLR_UPD),
584 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents,
585 0x0e0, 0x0e4, 0x0e8, 8, 2, 15,
586 0x8, 9, CLK_MUX_SETCLR_UPD),
587 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_104M_SEL, occ_104m_parents,
588 0x0e0, 0x0e4, 0x0e8, 16, 1, 23,
589 0x8, 10, CLK_MUX_SETCLR_UPD),
590 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_68M_SEL, occ_68m_parents,
591 0x0e0, 0x0e4, 0x0e8, 24, 1, 31,
592 0x8, 11, CLK_MUX_SETCLR_UPD),
593 /* CLK_CFG_11 */
594 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_182M_SEL, occ_182m_parents,
595 0x0ec, 0x0f0, 0x0f4, 0, 2, 7,
596 0x8, 12, CLK_MUX_SETCLR_UPD),
597 };
598
599 static const struct mtk_gate_regs top0_cg_regs = {
600 .set_ofs = 0x0,
601 .clr_ofs = 0x0,
602 .sta_ofs = 0x0,
603 };
604
605 static const struct mtk_gate_regs top1_cg_regs = {
606 .set_ofs = 0x104,
607 .clr_ofs = 0x104,
608 .sta_ofs = 0x104,
609 };
610
611 #define GATE_TOP0(_id, _parent, _shift) { \
612 .id = _id, \
613 .parent = _parent, \
614 .regs = &top0_cg_regs, \
615 .shift = _shift, \
616 .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \
617 }
618
619 #define GATE_TOP1(_id, _parent, _shift) { \
620 .id = _id, \
621 .parent = _parent, \
622 .regs = &top1_cg_regs, \
623 .shift = _shift, \
624 .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
625 }
626
627 static const struct mtk_gate top_clks[] = {
628 /* TOP0 */
629 GATE_TOP0(CLK_TOP_CONN_32K, CLK_TOP_CLK32K, 10),
630 GATE_TOP0(CLK_TOP_CONN_26M, CLK_TOP_CLK26M, 11),
631 GATE_TOP0(CLK_TOP_DSP_32K, CLK_TOP_CLK32K, 16),
632 GATE_TOP0(CLK_TOP_DSP_26M, CLK_TOP_CLK26M, 17),
633 /* TOP1 */
634 GATE_TOP1(CLK_TOP_USB20_48M_EN, CLK_TOP_USB20_192M_D4_T, 8),
635 GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, CLK_TOP_USB20_192M_D4_T, 9),
636 GATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, CLK_TOP_CLK_NULL, 22),
637 GATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, CLK_TOP_CLK_NULL, 23),
638 };
639
640 static const struct mtk_gate_regs infra0_cg_regs = {
641 .set_ofs = 0x294,
642 .clr_ofs = 0x294,
643 .sta_ofs = 0x294,
644 };
645
646 static const struct mtk_gate_regs infra1_cg_regs = {
647 .set_ofs = 0x80,
648 .clr_ofs = 0x84,
649 .sta_ofs = 0x90,
650 };
651
652 static const struct mtk_gate_regs infra2_cg_regs = {
653 .set_ofs = 0x88,
654 .clr_ofs = 0x8c,
655 .sta_ofs = 0x94,
656 };
657
658 static const struct mtk_gate_regs infra3_cg_regs = {
659 .set_ofs = 0xa4,
660 .clr_ofs = 0xa8,
661 .sta_ofs = 0xac,
662 };
663
664 static const struct mtk_gate_regs infra4_cg_regs = {
665 .set_ofs = 0xc0,
666 .clr_ofs = 0xc4,
667 .sta_ofs = 0xc8,
668 };
669
670 static const struct mtk_gate_regs infra5_cg_regs = {
671 .set_ofs = 0xd0,
672 .clr_ofs = 0xd4,
673 .sta_ofs = 0xd8,
674 };
675
676 #define GATE_INFRA0(_id, _parent, _shift) { \
677 .id = _id, \
678 .parent = _parent, \
679 .regs = &infra0_cg_regs, \
680 .shift = _shift, \
681 .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
682 }
683
684 #define GATE_INFRA1(_id, _parent, _shift) { \
685 .id = _id, \
686 .parent = _parent, \
687 .regs = &infra1_cg_regs, \
688 .shift = _shift, \
689 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
690 }
691
692 #define GATE_INFRA2(_id, _parent, _shift) { \
693 .id = _id, \
694 .parent = _parent, \
695 .regs = &infra2_cg_regs, \
696 .shift = _shift, \
697 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
698 }
699
700 #define GATE_INFRA3(_id, _parent, _shift) { \
701 .id = _id, \
702 .parent = _parent, \
703 .regs = &infra3_cg_regs, \
704 .shift = _shift, \
705 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
706 }
707
708 #define GATE_INFRA4(_id, _parent, _shift) { \
709 .id = _id, \
710 .parent = _parent, \
711 .regs = &infra4_cg_regs, \
712 .shift = _shift, \
713 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
714 }
715
716 #define GATE_INFRA5(_id, _parent, _shift) { \
717 .id = _id, \
718 .parent = _parent, \
719 .regs = &infra5_cg_regs, \
720 .shift = _shift, \
721 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
722 }
723
724 static const struct mtk_gate infra_clks[] = {
725 /* INFRA0 */
726 GATE_INFRA0(CLK_INFRA_DSP_AXI, CLK_TOP_AXI_SEL, 8),
727 /* INFRA1 */
728 GATE_INFRA1(CLK_INFRA_APXGPT, CLK_TOP_AXI_SEL, 6),
729 GATE_INFRA1(CLK_INFRA_ICUSB, CLK_TOP_AXI_SEL, 8),
730 GATE_INFRA1(CLK_INFRA_GCE, CLK_TOP_AXI_SEL, 9),
731 GATE_INFRA1(CLK_INFRA_THERM, CLK_TOP_AXI_SEL, 10),
732 GATE_INFRA1(CLK_INFRA_PWM_HCLK, CLK_TOP_AXI_SEL, 15),
733 GATE_INFRA1(CLK_INFRA_PWM1, CLK_TOP_PWM_SEL, 16),
734 GATE_INFRA1(CLK_INFRA_PWM2, CLK_TOP_PWM_SEL, 17),
735 GATE_INFRA1(CLK_INFRA_PWM3, CLK_TOP_PWM_SEL, 18),
736 GATE_INFRA1(CLK_INFRA_PWM4, CLK_TOP_PWM_SEL, 19),
737 GATE_INFRA1(CLK_INFRA_PWM5, CLK_TOP_PWM_SEL, 20),
738 GATE_INFRA1(CLK_INFRA_PWM, CLK_TOP_PWM_SEL, 21),
739 GATE_INFRA1(CLK_INFRA_UART0, CLK_TOP_UART_SEL, 22),
740 GATE_INFRA1(CLK_INFRA_UART1, CLK_TOP_UART_SEL, 23),
741 GATE_INFRA1(CLK_INFRA_UART2, CLK_TOP_UART_SEL, 24),
742 GATE_INFRA1(CLK_INFRA_DSP_UART, CLK_TOP_UART_SEL, 26),
743 GATE_INFRA1(CLK_INFRA_GCE_26M, CLK_TOP_CLK26M, 27),
744 GATE_INFRA1(CLK_INFRA_CQDMA_FPC, CLK_TOP_AXI_SEL, 28),
745 GATE_INFRA1(CLK_INFRA_BTIF, CLK_TOP_AXI_SEL, 31),
746 /* INFRA2 */
747 GATE_INFRA2(CLK_INFRA_SPI, CLK_TOP_SPI_SEL, 1),
748 GATE_INFRA2(CLK_INFRA_MSDC0, CLK_TOP_MSDC50_0_HC_SEL, 2),
749 GATE_INFRA2(CLK_INFRA_MSDC1, CLK_TOP_AXI_SEL, 4),
750 GATE_INFRA2(CLK_INFRA_DVFSRC, CLK_TOP_CLK26M, 7),
751 GATE_INFRA2(CLK_INFRA_GCPU, CLK_TOP_AXI_SEL, 8),
752 GATE_INFRA2(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 9),
753 GATE_INFRA2(CLK_INFRA_AUXADC, CLK_TOP_CLK26M, 10),
754 GATE_INFRA2(CLK_INFRA_AUXADC_MD, CLK_TOP_CLK26M, 14),
755 GATE_INFRA2(CLK_INFRA_AP_DMA, CLK_TOP_AXI_SEL, 18),
756 GATE_INFRA2(CLK_INFRA_DEBUGSYS, CLK_TOP_AXI_SEL, 24),
757 GATE_INFRA2(CLK_INFRA_AUDIO, CLK_TOP_AXI_SEL, 25),
758 GATE_INFRA2(CLK_INFRA_FLASHIF, CLK_TOP_SFLASH_SEL, 29),
759 /* INFRA3 */
760 GATE_INFRA3(CLK_INFRA_PWM_FB6, CLK_TOP_PWM_SEL, 0),
761 GATE_INFRA3(CLK_INFRA_PWM_FB7, CLK_TOP_PWM_SEL, 1),
762 GATE_INFRA3(CLK_INFRA_AUD_ASRC, CLK_TOP_AXI_SEL, 3),
763 GATE_INFRA3(CLK_INFRA_AUD_26M, CLK_TOP_CLK26M, 4),
764 GATE_INFRA3(CLK_INFRA_SPIS, CLK_TOP_AXI_SEL, 6),
765 GATE_INFRA3(CLK_INFRA_CQ_DMA, CLK_TOP_AXI_SEL, 27),
766 /* INFRA4 */
767 GATE_INFRA4(CLK_INFRA_AP_MSDC0, CLK_TOP_MSDC50_0_SEL, 7),
768 GATE_INFRA4(CLK_INFRA_MD_MSDC0, CLK_TOP_MSDC50_0_SEL, 8),
769 GATE_INFRA4(CLK_INFRA_MSDC0_SRC, CLK_TOP_MSDC50_0_SEL, 9),
770 GATE_INFRA4(CLK_INFRA_MSDC1_SRC, CLK_TOP_MSDC30_1_SEL, 10),
771 GATE_INFRA4(CLK_INFRA_IRRX_26M, CLK_TOP_AXI_SEL, 22),
772 GATE_INFRA4(CLK_INFRA_IRRX_32K, CLK_TOP_CLK32K, 23),
773 GATE_INFRA4(CLK_INFRA_I2C0_AXI, CLK_TOP_I2C_SEL, 24),
774 GATE_INFRA4(CLK_INFRA_I2C1_AXI, CLK_TOP_I2C_SEL, 25),
775 GATE_INFRA4(CLK_INFRA_I2C2_AXI, CLK_TOP_I2C_SEL, 26),
776 /* INFRA5 */
777 GATE_INFRA5(CLK_INFRA_NFI, CLK_TOP_NFI2X_CK_D2, 1),
778 GATE_INFRA5(CLK_INFRA_NFIECC, CLK_TOP_NFI2X_CK_D2, 2),
779 GATE_INFRA5(CLK_INFRA_NFI_HCLK, CLK_TOP_AXI_SEL, 3),
780 GATE_INFRA5(CLK_INFRA_SUSB_133, CLK_TOP_AXI_SEL, 7),
781 GATE_INFRA5(CLK_INFRA_USB_SYS, CLK_TOP_SSUSB_SYS_SEL, 9),
782 GATE_INFRA5(CLK_INFRA_USB_XHCI, CLK_TOP_SSUSB_XHCI_SEL, 11),
783 };
784
785 static const struct mtk_clk_tree mt8512_clk_tree = {
786 .xtal_rate = 26 * MHZ,
787 .xtal2_rate = 26 * MHZ,
788 .fdivs_offs = CLK_TOP_SYSPLL1_D2,
789 .muxes_offs = CLK_TOP_AXI_SEL,
790 .plls = apmixed_plls,
791 .fclks = top_fixed_clks,
792 .fdivs = top_fixed_divs,
793 .muxes = top_muxes,
794 };
795
mt8512_apmixedsys_probe(struct udevice * dev)796 static int mt8512_apmixedsys_probe(struct udevice *dev)
797 {
798 return mtk_common_clk_init(dev, &mt8512_clk_tree);
799 }
800
mt8512_topckgen_probe(struct udevice * dev)801 static int mt8512_topckgen_probe(struct udevice *dev)
802 {
803 return mtk_common_clk_init(dev, &mt8512_clk_tree);
804 }
805
mt8512_topckgen_cg_probe(struct udevice * dev)806 static int mt8512_topckgen_cg_probe(struct udevice *dev)
807 {
808 return mtk_common_clk_gate_init(dev, &mt8512_clk_tree, top_clks);
809 }
810
mt8512_infracfg_probe(struct udevice * dev)811 static int mt8512_infracfg_probe(struct udevice *dev)
812 {
813 return mtk_common_clk_gate_init(dev, &mt8512_clk_tree, infra_clks);
814 }
815
816 static const struct udevice_id mt8512_apmixed_compat[] = {
817 { .compatible = "mediatek,mt8512-apmixedsys", },
818 { }
819 };
820
821 static const struct udevice_id mt8512_topckgen_compat[] = {
822 { .compatible = "mediatek,mt8512-topckgen", },
823 { }
824 };
825
826 static const struct udevice_id mt8512_topckgen_cg_compat[] = {
827 { .compatible = "mediatek,mt8512-topckgen-cg", },
828 { }
829 };
830
831 static const struct udevice_id mt8512_infracfg_compat[] = {
832 { .compatible = "mediatek,mt8512-infracfg", },
833 { }
834 };
835
836 U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
837 .name = "mt8512-apmixedsys",
838 .id = UCLASS_CLK,
839 .of_match = mt8512_apmixed_compat,
840 .probe = mt8512_apmixedsys_probe,
841 .priv_auto = sizeof(struct mtk_clk_priv),
842 .ops = &mtk_clk_apmixedsys_ops,
843 .flags = DM_FLAG_PRE_RELOC,
844 };
845
846 U_BOOT_DRIVER(mtk_clk_topckgen) = {
847 .name = "mt8512-topckgen",
848 .id = UCLASS_CLK,
849 .of_match = mt8512_topckgen_compat,
850 .probe = mt8512_topckgen_probe,
851 .priv_auto = sizeof(struct mtk_clk_priv),
852 .ops = &mtk_clk_topckgen_ops,
853 .flags = DM_FLAG_PRE_RELOC,
854 };
855
856 U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
857 .name = "mt8512-topckgen-cg",
858 .id = UCLASS_CLK,
859 .of_match = mt8512_topckgen_cg_compat,
860 .probe = mt8512_topckgen_cg_probe,
861 .priv_auto = sizeof(struct mtk_cg_priv),
862 .ops = &mtk_clk_gate_ops,
863 .flags = DM_FLAG_PRE_RELOC,
864 };
865
866 U_BOOT_DRIVER(mtk_clk_infracfg) = {
867 .name = "mt8512-infracfg",
868 .id = UCLASS_CLK,
869 .of_match = mt8512_infracfg_compat,
870 .probe = mt8512_infracfg_probe,
871 .priv_auto = sizeof(struct mtk_cg_priv),
872 .ops = &mtk_clk_gate_ops,
873 .flags = DM_FLAG_PRE_RELOC,
874 };
875