1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com 4 * 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 */ 11 12 #ifndef K3_NAVSS_UDMA_HWDEF_H_ 13 #define K3_NAVSS_UDMA_HWDEF_H_ 14 15 #include <linux/bitops.h> 16 #define UDMA_PSIL_DST_THREAD_ID_OFFSET 0x8000 17 18 /* Global registers */ 19 #define UDMA_REV_REG 0x0 20 #define UDMA_PERF_CTL_REG 0x4 21 #define UDMA_EMU_CTL_REG 0x8 22 #define UDMA_PSIL_TO_REG 0x10 23 #define UDMA_UTC_CTL_REG 0x1c 24 #define UDMA_CAP_REG(i) (0x20 + (i * 4)) 25 #define UDMA_RX_FLOW_ID_FW_OES_REG 0x80 26 #define UDMA_RX_FLOW_ID_FW_STATUS_REG 0x88 27 28 /* RX Flow regs */ 29 #define UDMA_RFLOW_RFA_REG 0x0 30 #define UDMA_RFLOW_RFB_REG 0x4 31 #define UDMA_RFLOW_RFC_REG 0x8 32 #define UDMA_RFLOW_RFD_REG 0xc 33 #define UDMA_RFLOW_RFE_REG 0x10 34 #define UDMA_RFLOW_RFF_REG 0x14 35 #define UDMA_RFLOW_RFG_REG 0x18 36 #define UDMA_RFLOW_RFH_REG 0x1c 37 38 #define UDMA_RFLOW_REG(x) (UDMA_RFLOW_RF##x##_REG) 39 40 /* TX chan regs */ 41 #define UDMA_TCHAN_TCFG_REG 0x0 42 #define UDMA_TCHAN_TCREDIT_REG 0x4 43 #define UDMA_TCHAN_TCQ_REG 0x14 44 #define UDMA_TCHAN_TOES_REG(i) (0x20 + (i) * 4) 45 #define UDMA_TCHAN_TEOES_REG 0x60 46 #define UDMA_TCHAN_TPRI_CTRL_REG 0x64 47 #define UDMA_TCHAN_THREAD_ID_REG 0x68 48 #define UDMA_TCHAN_TFIFO_DEPTH_REG 0x70 49 #define UDMA_TCHAN_TST_SCHED_REG 0x80 50 51 /* RX chan regs */ 52 #define UDMA_RCHAN_RCFG_REG 0x0 53 #define UDMA_RCHAN_RCQ_REG 0x14 54 #define UDMA_RCHAN_ROES_REG(i) (0x20 + (i) * 4) 55 #define UDMA_RCHAN_REOES_REG 0x60 56 #define UDMA_RCHAN_RPRI_CTRL_REG 0x64 57 #define UDMA_RCHAN_THREAD_ID_REG 0x68 58 #define UDMA_RCHAN_RST_SCHED_REG 0x80 59 #define UDMA_RCHAN_RFLOW_RNG_REG 0xf0 60 61 /* TX chan RT regs */ 62 #define UDMA_TCHAN_RT_CTL_REG 0x0 63 #define UDMA_TCHAN_RT_SWTRIG_REG 0x8 64 #define UDMA_TCHAN_RT_STDATA_REG 0x80 65 66 #define UDMA_TCHAN_RT_PEERn_REG(i) (0x200 + (i * 0x4)) 67 #define UDMA_TCHAN_RT_PEER_STATIC_TR_XY_REG \ 68 UDMA_TCHAN_RT_PEERn_REG(0) /* PSI-L: 0x400 */ 69 #define UDMA_TCHAN_RT_PEER_STATIC_TR_Z_REG \ 70 UDMA_TCHAN_RT_PEERn_REG(1) /* PSI-L: 0x401 */ 71 #define UDMA_TCHAN_RT_PEER_BCNT_REG \ 72 UDMA_TCHAN_RT_PEERn_REG(4) /* PSI-L: 0x404 */ 73 #define UDMA_TCHAN_RT_PEER_RT_EN_REG \ 74 UDMA_TCHAN_RT_PEERn_REG(8) /* PSI-L: 0x408 */ 75 76 #define UDMA_TCHAN_RT_PCNT_REG 0x400 77 #define UDMA_TCHAN_RT_BCNT_REG 0x408 78 #define UDMA_TCHAN_RT_SBCNT_REG 0x410 79 80 /* RX chan RT regs */ 81 #define UDMA_RCHAN_RT_CTL_REG 0x0 82 #define UDMA_RCHAN_RT_SWTRIG_REG 0x8 83 #define UDMA_RCHAN_RT_STDATA_REG 0x80 84 85 #define UDMA_RCHAN_RT_PEERn_REG(i) (0x200 + (i * 0x4)) 86 #define UDMA_RCHAN_RT_PEER_STATIC_TR_XY_REG \ 87 UDMA_RCHAN_RT_PEERn_REG(0) /* PSI-L: 0x400 */ 88 #define UDMA_RCHAN_RT_PEER_STATIC_TR_Z_REG \ 89 UDMA_RCHAN_RT_PEERn_REG(1) /* PSI-L: 0x401 */ 90 #define UDMA_RCHAN_RT_PEER_BCNT_REG \ 91 UDMA_RCHAN_RT_PEERn_REG(4) /* PSI-L: 0x404 */ 92 #define UDMA_RCHAN_RT_PEER_RT_EN_REG \ 93 UDMA_RCHAN_RT_PEERn_REG(8) /* PSI-L: 0x408 */ 94 95 #define UDMA_RCHAN_RT_PCNT_REG 0x400 96 #define UDMA_RCHAN_RT_BCNT_REG 0x408 97 #define UDMA_RCHAN_RT_SBCNT_REG 0x410 98 99 /* UDMA_TCHAN_TCFG_REG/UDMA_RCHAN_RCFG_REG */ 100 #define UDMA_CHAN_CFG_PAUSE_ON_ERR BIT(31) 101 #define UDMA_TCHAN_CFG_FILT_EINFO BIT(30) 102 #define UDMA_TCHAN_CFG_FILT_PSWORDS BIT(29) 103 #define UDMA_CHAN_CFG_ATYPE_MASK GENMASK(25, 24) 104 #define UDMA_CHAN_CFG_ATYPE_SHIFT 24 105 #define UDMA_CHAN_CFG_CHAN_TYPE_MASK GENMASK(19, 16) 106 #define UDMA_CHAN_CFG_CHAN_TYPE_SHIFT 16 107 /* 108 * PBVR - using pass by value rings 109 * PBRR - using pass by reference rings 110 * 3RDP - Third Party DMA 111 * BC - Block Copy 112 * SB - single buffer packet mode enabled 113 */ 114 #define UDMA_CHAN_CFG_CHAN_TYPE_PACKET_PBRR \ 115 (2 << UDMA_CHAN_CFG_CHAN_TYPE_SHIFT) 116 #define UDMA_CHAN_CFG_CHAN_TYPE_PACKET_SB_PBRR \ 117 (3 << UDMA_CHAN_CFG_CHAN_TYPE_SHIFT) 118 #define UDMA_CHAN_CFG_CHAN_TYPE_3RDP_PBRR \ 119 (10 << UDMA_CHAN_CFG_CHAN_TYPE_SHIFT) 120 #define UDMA_CHAN_CFG_CHAN_TYPE_3RDP_PBVR \ 121 (11 << UDMA_CHAN_CFG_CHAN_TYPE_SHIFT) 122 #define UDMA_CHAN_CFG_CHAN_TYPE_3RDP_BC_PBRR \ 123 (12 << UDMA_CHAN_CFG_CHAN_TYPE_SHIFT) 124 #define UDMA_RCHAN_CFG_IGNORE_SHORT BIT(15) 125 #define UDMA_RCHAN_CFG_IGNORE_LONG BIT(14) 126 #define UDMA_TCHAN_CFG_SUPR_TDPKT BIT(8) 127 #define UDMA_CHAN_CFG_FETCH_SIZE_MASK GENMASK(6, 0) 128 #define UDMA_CHAN_CFG_FETCH_SIZE_SHIFT 0 129 130 /* UDMA_TCHAN_RT_CTL_REG/UDMA_RCHAN_RT_CTL_REG */ 131 #define UDMA_CHAN_RT_CTL_EN BIT(31) 132 #define UDMA_CHAN_RT_CTL_TDOWN BIT(30) 133 #define UDMA_CHAN_RT_CTL_PAUSE BIT(29) 134 #define UDMA_CHAN_RT_CTL_FTDOWN BIT(28) 135 #define UDMA_CHAN_RT_CTL_ERROR BIT(0) 136 137 /* UDMA_TCHAN_RT_PEER_RT_EN_REG/UDMA_RCHAN_RT_PEER_RT_EN_REG (PSI-L: 0x408) */ 138 #define UDMA_PEER_RT_EN_ENABLE BIT(31) 139 #define UDMA_PEER_RT_EN_TEARDOWN BIT(30) 140 #define UDMA_PEER_RT_EN_PAUSE BIT(29) 141 #define UDMA_PEER_RT_EN_FLUSH BIT(28) 142 #define UDMA_PEER_RT_EN_IDLE BIT(1) 143 144 /* RX Flow reg RFA */ 145 #define UDMA_RFLOW_RFA_EINFO BIT(30) 146 #define UDMA_RFLOW_RFA_PSINFO BIT(29) 147 #define UDMA_RFLOW_RFA_ERR_HANDLING BIT(28) 148 #define UDMA_RFLOW_RFA_DESC_TYPE_MASK GENMASK(27, 26) 149 #define UDMA_RFLOW_RFA_DESC_TYPE_SHIFT 26 150 #define UDMA_RFLOW_RFA_PS_LOC BIT(25) 151 #define UDMA_RFLOW_RFA_SOP_OFF_MASK GENMASK(24, 16) 152 #define UDMA_RFLOW_RFA_SOP_OFF_SHIFT 16 153 #define UDMA_RFLOW_RFA_DEST_QNUM_MASK GENMASK(15, 0) 154 #define UDMA_RFLOW_RFA_DEST_QNUM_SHIFT 0 155 156 /* RX Flow reg RFC */ 157 #define UDMA_RFLOW_RFC_SRC_TAG_HI_SEL_SHIFT 28 158 #define UDMA_RFLOW_RFC_SRC_TAG_LO_SEL_SHIFT 24 159 #define UDMA_RFLOW_RFC_DST_TAG_HI_SEL_SHIFT 20 160 #define UDMA_RFLOW_RFC_DST_TAG_LO_SE_SHIFT 16 161 162 /* 163 * UDMA_TCHAN_RT_PEER_STATIC_TR_XY_REG / 164 * UDMA_RCHAN_RT_PEER_STATIC_TR_XY_REG 165 */ 166 #define PDMA_STATIC_TR_X_MASK GENMASK(26, 24) 167 #define PDMA_STATIC_TR_X_SHIFT (24) 168 #define PDMA_STATIC_TR_Y_MASK GENMASK(11, 0) 169 #define PDMA_STATIC_TR_Y_SHIFT (0) 170 171 #define PDMA_STATIC_TR_Y(x) \ 172 (((x) << PDMA_STATIC_TR_Y_SHIFT) & PDMA_STATIC_TR_Y_MASK) 173 #define PDMA_STATIC_TR_X(x) \ 174 (((x) << PDMA_STATIC_TR_X_SHIFT) & PDMA_STATIC_TR_X_MASK) 175 176 /* 177 * UDMA_TCHAN_RT_PEER_STATIC_TR_Z_REG / 178 * UDMA_RCHAN_RT_PEER_STATIC_TR_Z_REG 179 */ 180 #define PDMA_STATIC_TR_Z_MASK GENMASK(11, 0) 181 #define PDMA_STATIC_TR_Z_SHIFT (0) 182 #define PDMA_STATIC_TR_Z(x) \ 183 (((x) << PDMA_STATIC_TR_Z_SHIFT) & PDMA_STATIC_TR_Z_MASK) 184 185 #endif /* K3_NAVSS_UDMA_HWDEF_H_ */ 186