1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * bcm2835 sdhost driver.
4 *
5 * The 2835 has two SD controllers: The Arasan sdhci controller
6 * (supported by the iproc driver) and a custom sdhost controller
7 * (supported by this driver).
8 *
9 * The sdhci controller supports both sdcard and sdio. The sdhost
10 * controller supports the sdcard only, but has better performance.
11 * Also note that the rpi3 has sdio wifi, so driving the sdcard with
12 * the sdhost controller allows to use the sdhci controller for wifi
13 * support.
14 *
15 * The configuration is done by devicetree via pin muxing. Both
16 * SD controller are available on the same pins (2 pin groups = pin 22
17 * to 27 + pin 48 to 53). So it's possible to use both SD controllers
18 * at the same time with different pin groups.
19 *
20 * This code was ported to U-Boot by
21 * Alexander Graf <agraf@suse.de>
22 * and is based on drivers/mmc/host/bcm2835.c in Linux which is written by
23 * Phil Elwell <phil@raspberrypi.org>
24 * Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd.
25 * which is based on
26 * mmc-bcm2835.c by Gellert Weisz
27 * which is, in turn, based on
28 * sdhci-bcm2708.c by Broadcom
29 * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko
30 * sdhci.c and sdhci-pci.c by Pierre Ossman
31 */
32 #include <clk.h>
33 #include <common.h>
34 #include <dm.h>
35 #include <mmc.h>
36 #include <asm/arch/msg.h>
37 #include <asm/arch/mbox.h>
38 #include <asm/unaligned.h>
39 #include <dm/device_compat.h>
40 #include <linux/bitops.h>
41 #include <linux/bug.h>
42 #include <linux/compat.h>
43 #include <linux/delay.h>
44 #include <linux/io.h>
45 #include <linux/iopoll.h>
46 #include <linux/sizes.h>
47 #include <mach/gpio.h>
48 #include <power/regulator.h>
49
50 #define msleep(a) udelay(a * 1000)
51
52 #define SDCMD 0x00 /* Command to SD card - 16 R/W */
53 #define SDARG 0x04 /* Argument to SD card - 32 R/W */
54 #define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */
55 #define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */
56 #define SDRSP0 0x10 /* SD card response (31:0) - 32 R */
57 #define SDRSP1 0x14 /* SD card response (63:32) - 32 R */
58 #define SDRSP2 0x18 /* SD card response (95:64) - 32 R */
59 #define SDRSP3 0x1c /* SD card response (127:96) - 32 R */
60 #define SDHSTS 0x20 /* SD host status - 11 R/W */
61 #define SDVDD 0x30 /* SD card power control - 1 R/W */
62 #define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */
63 #define SDHCFG 0x38 /* Host configuration - 2 R/W */
64 #define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */
65 #define SDDATA 0x40 /* Data to/from SD card - 32 R/W */
66 #define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */
67
68 #define SDCMD_NEW_FLAG 0x8000
69 #define SDCMD_FAIL_FLAG 0x4000
70 #define SDCMD_BUSYWAIT 0x800
71 #define SDCMD_NO_RESPONSE 0x400
72 #define SDCMD_LONG_RESPONSE 0x200
73 #define SDCMD_WRITE_CMD 0x80
74 #define SDCMD_READ_CMD 0x40
75 #define SDCMD_CMD_MASK 0x3f
76
77 #define SDCDIV_MAX_CDIV 0x7ff
78
79 #define SDHSTS_BUSY_IRPT 0x400
80 #define SDHSTS_BLOCK_IRPT 0x200
81 #define SDHSTS_SDIO_IRPT 0x100
82 #define SDHSTS_REW_TIME_OUT 0x80
83 #define SDHSTS_CMD_TIME_OUT 0x40
84 #define SDHSTS_CRC16_ERROR 0x20
85 #define SDHSTS_CRC7_ERROR 0x10
86 #define SDHSTS_FIFO_ERROR 0x08
87 #define SDHSTS_DATA_FLAG 0x01
88
89 #define SDHSTS_CLEAR_MASK (SDHSTS_BUSY_IRPT | \
90 SDHSTS_BLOCK_IRPT | \
91 SDHSTS_SDIO_IRPT | \
92 SDHSTS_REW_TIME_OUT | \
93 SDHSTS_CMD_TIME_OUT | \
94 SDHSTS_CRC16_ERROR | \
95 SDHSTS_CRC7_ERROR | \
96 SDHSTS_FIFO_ERROR)
97
98 #define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR | \
99 SDHSTS_CRC16_ERROR | \
100 SDHSTS_REW_TIME_OUT | \
101 SDHSTS_FIFO_ERROR)
102
103 #define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT | \
104 SDHSTS_TRANSFER_ERROR_MASK)
105
106 #define SDHCFG_BUSY_IRPT_EN BIT(10)
107 #define SDHCFG_BLOCK_IRPT_EN BIT(8)
108 #define SDHCFG_SDIO_IRPT_EN BIT(5)
109 #define SDHCFG_DATA_IRPT_EN BIT(4)
110 #define SDHCFG_SLOW_CARD BIT(3)
111 #define SDHCFG_WIDE_EXT_BUS BIT(2)
112 #define SDHCFG_WIDE_INT_BUS BIT(1)
113 #define SDHCFG_REL_CMD_LINE BIT(0)
114
115 #define SDVDD_POWER_OFF 0
116 #define SDVDD_POWER_ON 1
117
118 #define SDEDM_FORCE_DATA_MODE BIT(19)
119 #define SDEDM_CLOCK_PULSE BIT(20)
120 #define SDEDM_BYPASS BIT(21)
121
122 #define SDEDM_FIFO_FILL_SHIFT 4
123 #define SDEDM_FIFO_FILL_MASK 0x1f
edm_fifo_fill(u32 edm)124 static u32 edm_fifo_fill(u32 edm)
125 {
126 return (edm >> SDEDM_FIFO_FILL_SHIFT) & SDEDM_FIFO_FILL_MASK;
127 }
128
129 #define SDEDM_WRITE_THRESHOLD_SHIFT 9
130 #define SDEDM_READ_THRESHOLD_SHIFT 14
131 #define SDEDM_THRESHOLD_MASK 0x1f
132
133 #define SDEDM_FSM_MASK 0xf
134 #define SDEDM_FSM_IDENTMODE 0x0
135 #define SDEDM_FSM_DATAMODE 0x1
136 #define SDEDM_FSM_READDATA 0x2
137 #define SDEDM_FSM_WRITEDATA 0x3
138 #define SDEDM_FSM_READWAIT 0x4
139 #define SDEDM_FSM_READCRC 0x5
140 #define SDEDM_FSM_WRITECRC 0x6
141 #define SDEDM_FSM_WRITEWAIT1 0x7
142 #define SDEDM_FSM_POWERDOWN 0x8
143 #define SDEDM_FSM_POWERUP 0x9
144 #define SDEDM_FSM_WRITESTART1 0xa
145 #define SDEDM_FSM_WRITESTART2 0xb
146 #define SDEDM_FSM_GENPULSES 0xc
147 #define SDEDM_FSM_WRITEWAIT2 0xd
148 #define SDEDM_FSM_STARTPOWDOWN 0xf
149
150 #define SDDATA_FIFO_WORDS 16
151
152 #define FIFO_READ_THRESHOLD 4
153 #define FIFO_WRITE_THRESHOLD 4
154 #define SDDATA_FIFO_PIO_BURST 8
155
156 #define SDHST_TIMEOUT_MAX_USEC 100000
157
158 struct bcm2835_plat {
159 struct mmc_config cfg;
160 struct mmc mmc;
161 };
162
163 struct bcm2835_host {
164 void __iomem *ioaddr;
165 u32 phys_addr;
166
167 int clock; /* Current clock speed */
168 unsigned int max_clk; /* Max possible freq */
169 unsigned int blocks; /* remaining PIO blocks */
170
171 u32 ns_per_fifo_word;
172
173 /* cached registers */
174 u32 hcfg;
175 u32 cdiv;
176
177 struct mmc_cmd *cmd; /* Current command */
178 struct mmc_data *data; /* Current data request */
179 bool use_busy:1; /* Wait for busy interrupt */
180
181 struct udevice *dev;
182 struct mmc *mmc;
183 struct bcm2835_plat *plat;
184 };
185
bcm2835_dumpregs(struct bcm2835_host * host)186 static void bcm2835_dumpregs(struct bcm2835_host *host)
187 {
188 dev_dbg(host->dev, "=========== REGISTER DUMP ===========\n");
189 dev_dbg(host->dev, "SDCMD 0x%08x\n", readl(host->ioaddr + SDCMD));
190 dev_dbg(host->dev, "SDARG 0x%08x\n", readl(host->ioaddr + SDARG));
191 dev_dbg(host->dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT));
192 dev_dbg(host->dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV));
193 dev_dbg(host->dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0));
194 dev_dbg(host->dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1));
195 dev_dbg(host->dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2));
196 dev_dbg(host->dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3));
197 dev_dbg(host->dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS));
198 dev_dbg(host->dev, "SDVDD 0x%08x\n", readl(host->ioaddr + SDVDD));
199 dev_dbg(host->dev, "SDEDM 0x%08x\n", readl(host->ioaddr + SDEDM));
200 dev_dbg(host->dev, "SDHCFG 0x%08x\n", readl(host->ioaddr + SDHCFG));
201 dev_dbg(host->dev, "SDHBCT 0x%08x\n", readl(host->ioaddr + SDHBCT));
202 dev_dbg(host->dev, "SDHBLC 0x%08x\n", readl(host->ioaddr + SDHBLC));
203 dev_dbg(host->dev, "===========================================\n");
204 }
205
bcm2835_reset_internal(struct bcm2835_host * host)206 static void bcm2835_reset_internal(struct bcm2835_host *host)
207 {
208 u32 temp;
209
210 writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD);
211 writel(0, host->ioaddr + SDCMD);
212 writel(0, host->ioaddr + SDARG);
213 /* Set timeout to a big enough value so we don't hit it */
214 writel(0xf00000, host->ioaddr + SDTOUT);
215 writel(0, host->ioaddr + SDCDIV);
216 /* Clear status register */
217 writel(SDHSTS_CLEAR_MASK, host->ioaddr + SDHSTS);
218 writel(0, host->ioaddr + SDHCFG);
219 writel(0, host->ioaddr + SDHBCT);
220 writel(0, host->ioaddr + SDHBLC);
221
222 /* Limit fifo usage due to silicon bug */
223 temp = readl(host->ioaddr + SDEDM);
224 temp &= ~((SDEDM_THRESHOLD_MASK << SDEDM_READ_THRESHOLD_SHIFT) |
225 (SDEDM_THRESHOLD_MASK << SDEDM_WRITE_THRESHOLD_SHIFT));
226 temp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) |
227 (FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT);
228 writel(temp, host->ioaddr + SDEDM);
229 /* Wait for FIFO threshold to populate */
230 msleep(20);
231 writel(SDVDD_POWER_ON, host->ioaddr + SDVDD);
232 /* Wait for all components to go through power on cycle */
233 msleep(20);
234 host->clock = 0;
235 writel(host->hcfg, host->ioaddr + SDHCFG);
236 writel(host->cdiv, host->ioaddr + SDCDIV);
237 }
238
bcm2835_wait_transfer_complete(struct bcm2835_host * host)239 static int bcm2835_wait_transfer_complete(struct bcm2835_host *host)
240 {
241 ulong tstart_ms = get_timer(0);
242
243 while (1) {
244 u32 edm, fsm;
245
246 edm = readl(host->ioaddr + SDEDM);
247 fsm = edm & SDEDM_FSM_MASK;
248
249 if ((fsm == SDEDM_FSM_IDENTMODE) ||
250 (fsm == SDEDM_FSM_DATAMODE))
251 break;
252
253 if ((fsm == SDEDM_FSM_READWAIT) ||
254 (fsm == SDEDM_FSM_WRITESTART1) ||
255 (fsm == SDEDM_FSM_READDATA)) {
256 writel(edm | SDEDM_FORCE_DATA_MODE,
257 host->ioaddr + SDEDM);
258 break;
259 }
260
261 /* Error out after ~1s */
262 ulong tlapse_ms = get_timer(tstart_ms);
263 if ( tlapse_ms > 1000 /* ms */ ) {
264
265 dev_err(host->dev,
266 "wait_transfer_complete - still waiting after %lu ms\n",
267 tlapse_ms);
268 bcm2835_dumpregs(host);
269 return -ETIMEDOUT;
270 }
271 }
272
273 return 0;
274 }
275
bcm2835_transfer_block_pio(struct bcm2835_host * host,bool is_read)276 static int bcm2835_transfer_block_pio(struct bcm2835_host *host, bool is_read)
277 {
278 struct mmc_data *data = host->data;
279 size_t blksize = data->blocksize;
280 int copy_words;
281 u32 hsts = 0;
282 u32 *buf;
283
284 if (blksize % sizeof(u32))
285 return -EINVAL;
286
287 buf = is_read ? (u32 *)data->dest : (u32 *)data->src;
288
289 if (is_read)
290 data->dest += blksize;
291 else
292 data->src += blksize;
293
294 copy_words = blksize / sizeof(u32);
295
296 /*
297 * Copy all contents from/to the FIFO as far as it reaches,
298 * then wait for it to fill/empty again and rewind.
299 */
300 while (copy_words) {
301 int burst_words, words;
302 u32 edm;
303
304 burst_words = min(SDDATA_FIFO_PIO_BURST, copy_words);
305 edm = readl(host->ioaddr + SDEDM);
306 if (is_read)
307 words = edm_fifo_fill(edm);
308 else
309 words = SDDATA_FIFO_WORDS - edm_fifo_fill(edm);
310
311 if (words < burst_words) {
312 int fsm_state = (edm & SDEDM_FSM_MASK);
313
314 if ((is_read &&
315 (fsm_state != SDEDM_FSM_READDATA &&
316 fsm_state != SDEDM_FSM_READWAIT &&
317 fsm_state != SDEDM_FSM_READCRC)) ||
318 (!is_read &&
319 (fsm_state != SDEDM_FSM_WRITEDATA &&
320 fsm_state != SDEDM_FSM_WRITEWAIT1 &&
321 fsm_state != SDEDM_FSM_WRITEWAIT2 &&
322 fsm_state != SDEDM_FSM_WRITECRC &&
323 fsm_state != SDEDM_FSM_WRITESTART1 &&
324 fsm_state != SDEDM_FSM_WRITESTART2))) {
325 hsts = readl(host->ioaddr + SDHSTS);
326 printf("fsm %x, hsts %08x\n", fsm_state, hsts);
327 if (hsts & SDHSTS_ERROR_MASK)
328 break;
329 }
330
331 continue;
332 } else if (words > copy_words) {
333 words = copy_words;
334 }
335
336 copy_words -= words;
337
338 /* Copy current chunk to/from the FIFO */
339 while (words) {
340 if (is_read)
341 *(buf++) = readl(host->ioaddr + SDDATA);
342 else
343 writel(*(buf++), host->ioaddr + SDDATA);
344 words--;
345 }
346 }
347
348 return 0;
349 }
350
bcm2835_transfer_pio(struct bcm2835_host * host)351 static int bcm2835_transfer_pio(struct bcm2835_host *host)
352 {
353 u32 sdhsts;
354 bool is_read;
355 int ret = 0;
356
357 is_read = (host->data->flags & MMC_DATA_READ) != 0;
358 ret = bcm2835_transfer_block_pio(host, is_read);
359 if (ret)
360 return ret;
361
362 sdhsts = readl(host->ioaddr + SDHSTS);
363 if (sdhsts & (SDHSTS_CRC16_ERROR |
364 SDHSTS_CRC7_ERROR |
365 SDHSTS_FIFO_ERROR)) {
366 printf("%s transfer error - HSTS %08x\n",
367 is_read ? "read" : "write", sdhsts);
368 ret = -EILSEQ;
369 } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT |
370 SDHSTS_REW_TIME_OUT))) {
371 printf("%s timeout error - HSTS %08x\n",
372 is_read ? "read" : "write", sdhsts);
373 ret = -ETIMEDOUT;
374 }
375
376 return ret;
377 }
378
bcm2835_prepare_data(struct bcm2835_host * host,struct mmc_cmd * cmd,struct mmc_data * data)379 static void bcm2835_prepare_data(struct bcm2835_host *host, struct mmc_cmd *cmd,
380 struct mmc_data *data)
381 {
382 WARN_ON(host->data);
383
384 host->data = data;
385 if (!data)
386 return;
387
388 /* Use PIO */
389 host->blocks = data->blocks;
390
391 writel(data->blocksize, host->ioaddr + SDHBCT);
392 writel(data->blocks, host->ioaddr + SDHBLC);
393 }
394
bcm2835_read_wait_sdcmd(struct bcm2835_host * host)395 static u32 bcm2835_read_wait_sdcmd(struct bcm2835_host *host)
396 {
397 u32 value;
398 int ret;
399 int timeout_us = SDHST_TIMEOUT_MAX_USEC;
400
401 ret = readl_poll_timeout(host->ioaddr + SDCMD, value,
402 !(value & SDCMD_NEW_FLAG), timeout_us);
403 if (ret == -ETIMEDOUT)
404 printf("%s: timeout (%d us)\n", __func__, timeout_us);
405
406 return value;
407 }
408
bcm2835_send_command(struct bcm2835_host * host,struct mmc_cmd * cmd,struct mmc_data * data)409 static int bcm2835_send_command(struct bcm2835_host *host, struct mmc_cmd *cmd,
410 struct mmc_data *data)
411 {
412 u32 sdcmd, sdhsts;
413
414 WARN_ON(host->cmd);
415
416 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) {
417 printf("unsupported response type!\n");
418 return -EINVAL;
419 }
420
421 sdcmd = bcm2835_read_wait_sdcmd(host);
422 if (sdcmd & SDCMD_NEW_FLAG) {
423 printf("previous command never completed.\n");
424 bcm2835_dumpregs(host);
425 return -EBUSY;
426 }
427
428 host->cmd = cmd;
429
430 /* Clear any error flags */
431 sdhsts = readl(host->ioaddr + SDHSTS);
432 if (sdhsts & SDHSTS_ERROR_MASK)
433 writel(sdhsts, host->ioaddr + SDHSTS);
434
435 bcm2835_prepare_data(host, cmd, data);
436
437 writel(cmd->cmdarg, host->ioaddr + SDARG);
438
439 sdcmd = cmd->cmdidx & SDCMD_CMD_MASK;
440
441 host->use_busy = false;
442 if (!(cmd->resp_type & MMC_RSP_PRESENT)) {
443 sdcmd |= SDCMD_NO_RESPONSE;
444 } else {
445 if (cmd->resp_type & MMC_RSP_136)
446 sdcmd |= SDCMD_LONG_RESPONSE;
447 if (cmd->resp_type & MMC_RSP_BUSY) {
448 sdcmd |= SDCMD_BUSYWAIT;
449 host->use_busy = true;
450 }
451 }
452
453 if (data) {
454 if (data->flags & MMC_DATA_WRITE)
455 sdcmd |= SDCMD_WRITE_CMD;
456 if (data->flags & MMC_DATA_READ)
457 sdcmd |= SDCMD_READ_CMD;
458 }
459
460 writel(sdcmd | SDCMD_NEW_FLAG, host->ioaddr + SDCMD);
461
462 return 0;
463 }
464
bcm2835_finish_command(struct bcm2835_host * host)465 static int bcm2835_finish_command(struct bcm2835_host *host)
466 {
467 struct mmc_cmd *cmd = host->cmd;
468 u32 sdcmd;
469 int ret = 0;
470
471 sdcmd = bcm2835_read_wait_sdcmd(host);
472
473 /* Check for errors */
474 if (sdcmd & SDCMD_NEW_FLAG) {
475 printf("command never completed.\n");
476 bcm2835_dumpregs(host);
477 return -EIO;
478 } else if (sdcmd & SDCMD_FAIL_FLAG) {
479 u32 sdhsts = readl(host->ioaddr + SDHSTS);
480
481 /* Clear the errors */
482 writel(SDHSTS_ERROR_MASK, host->ioaddr + SDHSTS);
483
484 if (!(sdhsts & SDHSTS_CRC7_ERROR) ||
485 (host->cmd->cmdidx != MMC_CMD_SEND_OP_COND)) {
486 if (sdhsts & SDHSTS_CMD_TIME_OUT) {
487 ret = -ETIMEDOUT;
488 } else {
489 printf("unexpected command %d error\n",
490 host->cmd->cmdidx);
491 bcm2835_dumpregs(host);
492 ret = -EILSEQ;
493 }
494
495 return ret;
496 }
497 }
498
499 if (cmd->resp_type & MMC_RSP_PRESENT) {
500 if (cmd->resp_type & MMC_RSP_136) {
501 int i;
502
503 for (i = 0; i < 4; i++) {
504 cmd->response[3 - i] =
505 readl(host->ioaddr + SDRSP0 + i * 4);
506 }
507 } else {
508 cmd->response[0] = readl(host->ioaddr + SDRSP0);
509 }
510 }
511
512 /* Processed actual command. */
513 host->cmd = NULL;
514
515 return ret;
516 }
517
bcm2835_check_cmd_error(struct bcm2835_host * host,u32 intmask)518 static int bcm2835_check_cmd_error(struct bcm2835_host *host, u32 intmask)
519 {
520 int ret = -EINVAL;
521
522 if (!(intmask & SDHSTS_ERROR_MASK))
523 return 0;
524
525 if (!host->cmd)
526 return -EINVAL;
527
528 printf("sdhost_busy_irq: intmask %08x\n", intmask);
529 if (intmask & SDHSTS_CRC7_ERROR) {
530 ret = -EILSEQ;
531 } else if (intmask & (SDHSTS_CRC16_ERROR |
532 SDHSTS_FIFO_ERROR)) {
533 ret = -EILSEQ;
534 } else if (intmask & (SDHSTS_REW_TIME_OUT | SDHSTS_CMD_TIME_OUT)) {
535 ret = -ETIMEDOUT;
536 }
537 bcm2835_dumpregs(host);
538 return ret;
539 }
540
bcm2835_check_data_error(struct bcm2835_host * host,u32 intmask)541 static int bcm2835_check_data_error(struct bcm2835_host *host, u32 intmask)
542 {
543 int ret = 0;
544
545 if (!host->data)
546 return 0;
547 if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_FIFO_ERROR))
548 ret = -EILSEQ;
549 if (intmask & SDHSTS_REW_TIME_OUT)
550 ret = -ETIMEDOUT;
551
552 if (ret)
553 printf("%s:%d %d\n", __func__, __LINE__, ret);
554
555 return ret;
556 }
557
bcm2835_transmit(struct bcm2835_host * host)558 static int bcm2835_transmit(struct bcm2835_host *host)
559 {
560 u32 intmask = readl(host->ioaddr + SDHSTS);
561 int ret;
562
563 /* Check for errors */
564 ret = bcm2835_check_data_error(host, intmask);
565 if (ret)
566 return ret;
567
568 ret = bcm2835_check_cmd_error(host, intmask);
569 if (ret)
570 return ret;
571
572 /* Handle wait for busy end */
573 if (host->use_busy && (intmask & SDHSTS_BUSY_IRPT)) {
574 writel(SDHSTS_BUSY_IRPT, host->ioaddr + SDHSTS);
575 host->use_busy = false;
576 bcm2835_finish_command(host);
577 }
578
579 /* Handle PIO data transfer */
580 if (host->data) {
581 ret = bcm2835_transfer_pio(host);
582 if (ret)
583 return ret;
584 host->blocks--;
585 if (host->blocks == 0) {
586 /* Wait for command to complete for real */
587 ret = bcm2835_wait_transfer_complete(host);
588 if (ret)
589 return ret;
590 /* Transfer complete */
591 host->data = NULL;
592 }
593 }
594
595 return 0;
596 }
597
bcm2835_set_clock(struct bcm2835_host * host,unsigned int clock)598 static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock)
599 {
600 int div;
601
602 /* The SDCDIV register has 11 bits, and holds (div - 2). But
603 * in data mode the max is 50MHz wihout a minimum, and only
604 * the bottom 3 bits are used. Since the switch over is
605 * automatic (unless we have marked the card as slow...),
606 * chosen values have to make sense in both modes. Ident mode
607 * must be 100-400KHz, so can range check the requested
608 * clock. CMD15 must be used to return to data mode, so this
609 * can be monitored.
610 *
611 * clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz
612 * 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz
613 *
614 * 623->400KHz/27.8MHz
615 * reset value (507)->491159/50MHz
616 *
617 * BUT, the 3-bit clock divisor in data mode is too small if
618 * the core clock is higher than 250MHz, so instead use the
619 * SLOW_CARD configuration bit to force the use of the ident
620 * clock divisor at all times.
621 */
622
623 if (clock < 100000) {
624 /* Can't stop the clock, but make it as slow as possible
625 * to show willing
626 */
627 host->cdiv = SDCDIV_MAX_CDIV;
628 writel(host->cdiv, host->ioaddr + SDCDIV);
629 return;
630 }
631
632 div = host->max_clk / clock;
633 if (div < 2)
634 div = 2;
635 if ((host->max_clk / div) > clock)
636 div++;
637 div -= 2;
638
639 if (div > SDCDIV_MAX_CDIV)
640 div = SDCDIV_MAX_CDIV;
641
642 clock = host->max_clk / (div + 2);
643 host->mmc->clock = clock;
644
645 /* Calibrate some delays */
646
647 host->ns_per_fifo_word = (1000000000 / clock) *
648 ((host->mmc->card_caps & MMC_MODE_4BIT) ? 8 : 32);
649
650 host->cdiv = div;
651 writel(host->cdiv, host->ioaddr + SDCDIV);
652
653 /* Set the timeout to 500ms */
654 writel(host->mmc->clock / 2, host->ioaddr + SDTOUT);
655 }
656
is_power_of_2(u64 x)657 static inline int is_power_of_2(u64 x)
658 {
659 return !(x & (x - 1));
660 }
661
bcm2835_send_cmd(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data)662 static int bcm2835_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
663 struct mmc_data *data)
664 {
665 struct bcm2835_host *host = dev_get_priv(dev);
666 u32 edm, fsm;
667 int ret = 0;
668
669 if (data && !is_power_of_2(data->blocksize)) {
670 printf("unsupported block size (%d bytes)\n", data->blocksize);
671
672 if (cmd)
673 return -EINVAL;
674 }
675
676 edm = readl(host->ioaddr + SDEDM);
677 fsm = edm & SDEDM_FSM_MASK;
678
679 if ((fsm != SDEDM_FSM_IDENTMODE) &&
680 (fsm != SDEDM_FSM_DATAMODE) &&
681 (cmd && cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) {
682 printf("previous command (%d) not complete (EDM %08x)\n",
683 readl(host->ioaddr + SDCMD) & SDCMD_CMD_MASK, edm);
684 bcm2835_dumpregs(host);
685
686 if (cmd)
687 return -EILSEQ;
688
689 return 0;
690 }
691
692 if (cmd) {
693 ret = bcm2835_send_command(host, cmd, data);
694 if (!ret && !host->use_busy)
695 ret = bcm2835_finish_command(host);
696 }
697
698 /* Wait for completion of busy signal or data transfer */
699 while (host->use_busy || host->data) {
700 ret = bcm2835_transmit(host);
701 if (ret)
702 break;
703 }
704
705 return ret;
706 }
707
bcm2835_set_ios(struct udevice * dev)708 static int bcm2835_set_ios(struct udevice *dev)
709 {
710 struct bcm2835_host *host = dev_get_priv(dev);
711 struct mmc *mmc = mmc_get_mmc_dev(dev);
712
713 if (!mmc->clock || mmc->clock != host->clock) {
714 bcm2835_set_clock(host, mmc->clock);
715 host->clock = mmc->clock;
716 }
717
718 /* set bus width */
719 host->hcfg &= ~SDHCFG_WIDE_EXT_BUS;
720 if (mmc->bus_width == 4)
721 host->hcfg |= SDHCFG_WIDE_EXT_BUS;
722
723 host->hcfg |= SDHCFG_WIDE_INT_BUS;
724
725 /* Disable clever clock switching, to cope with fast core clocks */
726 host->hcfg |= SDHCFG_SLOW_CARD;
727
728 writel(host->hcfg, host->ioaddr + SDHCFG);
729
730 return 0;
731 }
732
bcm2835_add_host(struct bcm2835_host * host)733 static void bcm2835_add_host(struct bcm2835_host *host)
734 {
735 struct mmc_config *cfg = &host->plat->cfg;
736
737 cfg->f_max = host->max_clk;
738 cfg->f_min = host->max_clk / SDCDIV_MAX_CDIV;
739 cfg->b_max = 65535;
740
741 dev_dbg(host->dev, "f_max %d, f_min %d\n",
742 cfg->f_max, cfg->f_min);
743
744 /* host controller capabilities */
745 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz;
746
747 /* report supported voltage ranges */
748 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
749
750 /* Set interrupt enables */
751 host->hcfg = SDHCFG_BUSY_IRPT_EN;
752
753 bcm2835_reset_internal(host);
754 }
755
bcm2835_probe(struct udevice * dev)756 static int bcm2835_probe(struct udevice *dev)
757 {
758 struct bcm2835_plat *plat = dev_get_plat(dev);
759 struct bcm2835_host *host = dev_get_priv(dev);
760 struct mmc *mmc = mmc_get_mmc_dev(dev);
761 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
762
763 host->dev = dev;
764 host->mmc = mmc;
765 host->plat = plat;
766 upriv->mmc = &plat->mmc;
767 plat->cfg.name = dev->name;
768
769 host->phys_addr = dev_read_addr(dev);
770 if (host->phys_addr == FDT_ADDR_T_NONE)
771 return -EINVAL;
772
773 host->ioaddr = devm_ioremap(dev, host->phys_addr, SZ_256);
774 if (!host->ioaddr)
775 return -ENOMEM;
776
777 host->max_clk = bcm2835_get_mmc_clock(BCM2835_MBOX_CLOCK_ID_CORE);
778
779 bcm2835_add_host(host);
780
781 dev_dbg(dev, "%s -> OK\n", __func__);
782
783 return 0;
784 }
785
786 static const struct udevice_id bcm2835_match[] = {
787 { .compatible = "brcm,bcm2835-sdhost" },
788 { }
789 };
790
791 static const struct dm_mmc_ops bcm2835_ops = {
792 .send_cmd = bcm2835_send_cmd,
793 .set_ios = bcm2835_set_ios,
794 };
795
bcm2835_bind(struct udevice * dev)796 static int bcm2835_bind(struct udevice *dev)
797 {
798 struct bcm2835_plat *plat = dev_get_plat(dev);
799
800 return mmc_bind(dev, &plat->mmc, &plat->cfg);
801 }
802
803 U_BOOT_DRIVER(bcm2835_sdhost) = {
804 .name = "bcm2835-sdhost",
805 .id = UCLASS_MMC,
806 .of_match = bcm2835_match,
807 .bind = bcm2835_bind,
808 .probe = bcm2835_probe,
809 .priv_auto = sizeof(struct bcm2835_host),
810 .plat_auto = sizeof(struct bcm2835_plat),
811 .ops = &bcm2835_ops,
812 };
813