1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * 4 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. 5 * Copyright (C) 2016 Jagan Teki <jagan@openedev.com> 6 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ 7 */ 8 9 #include <common.h> 10 #include <spi.h> 11 #include <spi_flash.h> 12 13 #include "sf_internal.h" 14 15 /* Exclude chip names for SPL to save space */ 16 #if !CONFIG_IS_ENABLED(SPI_FLASH_TINY) 17 #define INFO_NAME(_name) .name = _name, 18 #else 19 #define INFO_NAME(_name) 20 #endif 21 22 /* Used when the "_ext_id" is two bytes at most */ 23 #define INFO(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 24 INFO_NAME(_name) \ 25 .id = { \ 26 ((_jedec_id) >> 16) & 0xff, \ 27 ((_jedec_id) >> 8) & 0xff, \ 28 (_jedec_id) & 0xff, \ 29 ((_ext_id) >> 8) & 0xff, \ 30 (_ext_id) & 0xff, \ 31 }, \ 32 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \ 33 .sector_size = (_sector_size), \ 34 .n_sectors = (_n_sectors), \ 35 .page_size = 256, \ 36 .flags = (_flags), 37 38 #define INFO6(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 39 INFO_NAME(_name) \ 40 .id = { \ 41 ((_jedec_id) >> 16) & 0xff, \ 42 ((_jedec_id) >> 8) & 0xff, \ 43 (_jedec_id) & 0xff, \ 44 ((_ext_id) >> 16) & 0xff, \ 45 ((_ext_id) >> 8) & 0xff, \ 46 (_ext_id) & 0xff, \ 47 }, \ 48 .id_len = 6, \ 49 .sector_size = (_sector_size), \ 50 .n_sectors = (_n_sectors), \ 51 .page_size = 256, \ 52 .flags = (_flags), 53 54 /* NOTE: double check command sets and memory organization when you add 55 * more nor chips. This current list focusses on newer chips, which 56 * have been converging on command sets which including JEDEC ID. 57 * 58 * All newly added entries should describe *hardware* and should use SECT_4K 59 * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage 60 * scenarios excluding small sectors there is config option that can be 61 * disabled: CONFIG_SPI_FLASH_USE_4K_SECTORS. 62 * For historical (and compatibility) reasons (before we got above config) some 63 * old entries may be missing 4K flag. 64 */ 65 const struct flash_info spi_nor_ids[] = { 66 #ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */ 67 /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 68 { INFO("at26df321", 0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, 69 { INFO("at25df321a", 0x1f4701, 0, 64 * 1024, 64, SECT_4K) }, 70 71 { INFO("at45db011d", 0x1f2200, 0, 64 * 1024, 4, SECT_4K) }, 72 { INFO("at45db021d", 0x1f2300, 0, 64 * 1024, 8, SECT_4K) }, 73 { INFO("at45db041d", 0x1f2400, 0, 64 * 1024, 8, SECT_4K) }, 74 { INFO("at45db081d", 0x1f2500, 0, 64 * 1024, 16, SECT_4K) }, 75 { INFO("at45db161d", 0x1f2600, 0, 64 * 1024, 32, SECT_4K) }, 76 { INFO("at45db321d", 0x1f2700, 0, 64 * 1024, 64, SECT_4K) }, 77 { INFO("at45db641d", 0x1f2800, 0, 64 * 1024, 128, SECT_4K) }, 78 { INFO("at25sl321", 0x1f4216, 0, 64 * 1024, 64, SECT_4K) }, 79 { INFO("at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, 80 #endif 81 #ifdef CONFIG_SPI_FLASH_EON /* EON */ 82 /* EON -- en25xxx */ 83 { INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) }, 84 { INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, 85 { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) }, 86 { INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, 87 #endif 88 #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ 89 /* GigaDevice */ 90 { 91 INFO("gd25q16", 0xc84015, 0, 64 * 1024, 32, 92 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 93 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 94 }, 95 { 96 INFO("gd25q32", 0xc84016, 0, 64 * 1024, 64, 97 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 98 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 99 }, 100 { 101 INFO("gd25lq32", 0xc86016, 0, 64 * 1024, 64, 102 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 103 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 104 }, 105 { 106 INFO("gd25q64", 0xc84017, 0, 64 * 1024, 128, 107 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 108 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 109 }, 110 { 111 INFO("gd25lq64c", 0xc86017, 0, 64 * 1024, 128, 112 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 113 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 114 }, 115 { 116 INFO("gd25q128", 0xc84018, 0, 64 * 1024, 256, 117 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 118 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 119 }, 120 { 121 INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256, 122 SECT_4K | SPI_NOR_DUAL_READ | 123 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 124 }, 125 #endif 126 #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ 127 /* ISSI */ 128 { INFO("is25lq040b", 0x9d4013, 0, 64 * 1024, 8, 129 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 130 { INFO("is25lp032", 0x9d6016, 0, 64 * 1024, 64, 0) }, 131 { INFO("is25lp064", 0x9d6017, 0, 64 * 1024, 128, 0) }, 132 { INFO("is25lp128", 0x9d6018, 0, 64 * 1024, 256, 133 SECT_4K | SPI_NOR_DUAL_READ) }, 134 { INFO("is25lp256", 0x9d6019, 0, 64 * 1024, 512, 135 SECT_4K | SPI_NOR_DUAL_READ) }, 136 { INFO("is25wp032", 0x9d7016, 0, 64 * 1024, 64, 137 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 138 { INFO("is25wp064", 0x9d7017, 0, 64 * 1024, 128, 139 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 140 { INFO("is25wp128", 0x9d7018, 0, 64 * 1024, 256, 141 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 142 { INFO("is25wp256", 0x9d7019, 0, 64 * 1024, 512, 143 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 144 SPI_NOR_4B_OPCODES) }, 145 #endif 146 #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ 147 /* Macronix */ 148 { INFO("mx25l2005a", 0xc22012, 0, 64 * 1024, 4, SECT_4K) }, 149 { INFO("mx25l4005a", 0xc22013, 0, 64 * 1024, 8, SECT_4K) }, 150 { INFO("mx25l8005", 0xc22014, 0, 64 * 1024, 16, 0) }, 151 { INFO("mx25l1606e", 0xc22015, 0, 64 * 1024, 32, SECT_4K) }, 152 { INFO("mx25l3205d", 0xc22016, 0, 64 * 1024, 64, SECT_4K) }, 153 { INFO("mx25l6405d", 0xc22017, 0, 64 * 1024, 128, SECT_4K) }, 154 { INFO("mx25u2033e", 0xc22532, 0, 64 * 1024, 4, SECT_4K) }, 155 { INFO("mx25u1635e", 0xc22535, 0, 64 * 1024, 32, SECT_4K) }, 156 { INFO("mx25u3235f", 0xc22536, 0, 4 * 1024, 1024, SECT_4K) }, 157 { INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) }, 158 { INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, SECT_4K) }, 159 { INFO("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K) }, 160 { INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) }, 161 { INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 162 { INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) }, 163 { INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) }, 164 { INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 165 { INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 166 { INFO("mx66u2g45g", 0xc2253c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 167 { INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 168 { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) }, 169 { INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) }, 170 #endif 171 172 #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ 173 /* Micron */ 174 { INFO("n25q016a", 0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) }, 175 { INFO("n25q032", 0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, 176 { INFO("n25q032a", 0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, 177 { INFO("n25q064", 0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, 178 { INFO("n25q064a", 0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, 179 { INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, 180 { INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, 181 { INFO6("mt25ql256a", 0x20ba19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) }, 182 { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_FSR) }, 183 { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) }, 184 { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR) }, 185 { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024, 186 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | 187 USE_FSR) }, 188 { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, 189 { INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 190 { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, 191 { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 192 { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 193 { INFO("mt25ql01g", 0x21ba20, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 194 { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 195 { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, 196 { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, 197 #endif 198 #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ 199 /* Spansion/Cypress -- single (large) sector size only, at least 200 * for the chips listed here (without boot sectors). 201 */ 202 { INFO("s25sl032p", 0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 203 { INFO("s25sl064p", 0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 204 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 205 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 206 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 207 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 208 { INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 209 { INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 210 { INFO("s25fl512s_512k", 0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 211 { INFO("s25sl12800", 0x012018, 0x0300, 256 * 1024, 64, 0) }, 212 { INFO("s25sl12801", 0x012018, 0x0301, 64 * 1024, 256, 0) }, 213 { INFO6("s25fl128s", 0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 214 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 215 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 216 { INFO("s25sl008a", 0x010213, 0, 64 * 1024, 16, 0) }, 217 { INFO("s25sl016a", 0x010214, 0, 64 * 1024, 32, 0) }, 218 { INFO("s25sl032a", 0x010215, 0, 64 * 1024, 64, 0) }, 219 { INFO("s25sl064a", 0x010216, 0, 64 * 1024, 128, 0) }, 220 { INFO("s25fl116k", 0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 221 { INFO("s25fl164k", 0x014017, 0, 64 * 1024, 128, SECT_4K) }, 222 { INFO("s25fl208k", 0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) }, 223 { INFO("s25fl064l", 0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 224 { INFO("s25fl128l", 0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 225 #endif 226 #ifdef CONFIG_SPI_FLASH_SST /* SST */ 227 /* SST -- large erase sizes are "overlays", "sectors" are 4K */ 228 { INFO("sst25vf040b", 0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, 229 { INFO("sst25vf080b", 0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, 230 { INFO("sst25vf016b", 0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) }, 231 { INFO("sst25vf032b", 0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) }, 232 { INFO("sst25vf064c", 0xbf254b, 0, 64 * 1024, 128, SECT_4K) }, 233 { INFO("sst25wf512", 0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) }, 234 { INFO("sst25wf010", 0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) }, 235 { INFO("sst25wf020", 0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) }, 236 { INFO("sst25wf020a", 0x621612, 0, 64 * 1024, 4, SECT_4K) }, 237 { INFO("sst25wf040b", 0x621613, 0, 64 * 1024, 8, SECT_4K) }, 238 { INFO("sst25wf040", 0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, 239 { INFO("sst25wf080", 0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, 240 { INFO("sst26vf064b", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 241 { INFO("sst26wf016", 0xbf2651, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, 242 { INFO("sst26wf032", 0xbf2622, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, 243 { INFO("sst26wf064", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, 244 #endif 245 #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ 246 /* ST Microelectronics -- newer production may have feature updates */ 247 { INFO("m25p10", 0x202011, 0, 32 * 1024, 4, 0) }, 248 { INFO("m25p20", 0x202012, 0, 64 * 1024, 4, 0) }, 249 { INFO("m25p40", 0x202013, 0, 64 * 1024, 8, 0) }, 250 { INFO("m25p80", 0x202014, 0, 64 * 1024, 16, 0) }, 251 { INFO("m25p16", 0x202015, 0, 64 * 1024, 32, 0) }, 252 { INFO("m25p32", 0x202016, 0, 64 * 1024, 64, 0) }, 253 { INFO("m25p64", 0x202017, 0, 64 * 1024, 128, 0) }, 254 { INFO("m25p128", 0x202018, 0, 256 * 1024, 64, 0) }, 255 { INFO("m25pe16", 0x208015, 0, 64 * 1024, 32, SECT_4K) }, 256 { INFO("m25px16", 0x207115, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 257 { INFO("m25px64", 0x207117, 0, 64 * 1024, 128, 0) }, 258 #endif 259 #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */ 260 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ 261 { INFO("w25p80", 0xef2014, 0x0, 64 * 1024, 16, 0) }, 262 { INFO("w25p16", 0xef2015, 0x0, 64 * 1024, 32, 0) }, 263 { INFO("w25p32", 0xef2016, 0x0, 64 * 1024, 64, 0) }, 264 { INFO("w25x05", 0xef3010, 0, 64 * 1024, 1, SECT_4K) }, 265 { INFO("w25x40", 0xef3013, 0, 64 * 1024, 8, SECT_4K) }, 266 { INFO("w25x16", 0xef3015, 0, 64 * 1024, 32, SECT_4K) }, 267 { 268 INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32, 269 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 270 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 271 }, 272 { INFO("w25x32", 0xef3016, 0, 64 * 1024, 64, SECT_4K) }, 273 { INFO("w25q20cl", 0xef4012, 0, 64 * 1024, 4, SECT_4K) }, 274 { INFO("w25q20bw", 0xef5012, 0, 64 * 1024, 4, SECT_4K) }, 275 { INFO("w25q20ew", 0xef6012, 0, 64 * 1024, 4, SECT_4K) }, 276 { INFO("w25q32", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 277 { 278 INFO("w25q32dw", 0xef6016, 0, 64 * 1024, 64, 279 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 280 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 281 }, 282 { 283 INFO("w25q32jv", 0xef7016, 0, 64 * 1024, 64, 284 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 285 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 286 }, 287 { 288 INFO("w25q32jwm", 0xef8016, 0, 64 * 1024, 64, 289 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 290 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 291 }, 292 { INFO("w25x64", 0xef3017, 0, 64 * 1024, 128, SECT_4K) }, 293 { 294 INFO("w25q64dw", 0xef6017, 0, 64 * 1024, 128, 295 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 296 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 297 }, 298 { 299 INFO("w25q64jv", 0xef7017, 0, 64 * 1024, 128, 300 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 301 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 302 }, 303 { 304 INFO("w25q128fw", 0xef6018, 0, 64 * 1024, 256, 305 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 306 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 307 }, 308 { 309 INFO("w25q128jv", 0xef7018, 0, 64 * 1024, 256, 310 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 311 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 312 }, 313 { 314 INFO("w25q256fw", 0xef6019, 0, 64 * 1024, 512, 315 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 316 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 317 }, 318 { 319 INFO("w25q256jw", 0xef7019, 0, 64 * 1024, 512, 320 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 321 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 322 }, 323 { INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) }, 324 { INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 325 { INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 326 { INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 327 { INFO("w25q128", 0xef4018, 0, 64 * 1024, 256, 328 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 329 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 330 }, 331 { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 332 { INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 333 { INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 334 #endif 335 #ifdef CONFIG_SPI_FLASH_XMC 336 /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */ 337 { INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 338 { INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 339 #endif 340 { }, 341 }; 342