1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Cadence DDR Driver
4 *
5 * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
6 * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
7 */
8
9 #include <errno.h>
10
11 #include "cps_drv_lpddr4.h"
12 #include "lpddr4_ctl_regs.h"
13 #include "lpddr4_if.h"
14 #include "lpddr4.h"
15 #include "lpddr4_structs_if.h"
16
17 static u32 ctlintmap[51][3] = {
18 { 0, 0, 7 },
19 { 1, 0, 8 },
20 { 2, 0, 9 },
21 { 3, 0, 14 },
22 { 4, 0, 15 },
23 { 5, 0, 16 },
24 { 6, 0, 17 },
25 { 7, 0, 19 },
26 { 8, 1, 0 },
27 { 9, 2, 0 },
28 { 10, 2, 3 },
29 { 11, 3, 0 },
30 { 12, 4, 0 },
31 { 13, 5, 11 },
32 { 14, 5, 12 },
33 { 15, 5, 13 },
34 { 16, 5, 14 },
35 { 17, 5, 15 },
36 { 18, 6, 0 },
37 { 19, 6, 1 },
38 { 20, 6, 2 },
39 { 21, 6, 6 },
40 { 22, 6, 7 },
41 { 23, 7, 3 },
42 { 24, 7, 4 },
43 { 25, 7, 5 },
44 { 26, 7, 6 },
45 { 27, 7, 7 },
46 { 28, 8, 0 },
47 { 29, 9, 0 },
48 { 30, 10, 0 },
49 { 31, 10, 1 },
50 { 32, 10, 2 },
51 { 33, 10, 3 },
52 { 34, 10, 4 },
53 { 35, 10, 5 },
54 { 36, 11, 0 },
55 { 37, 12, 0 },
56 { 38, 12, 1 },
57 { 39, 12, 2 },
58 { 40, 12, 3 },
59 { 41, 12, 4 },
60 { 42, 12, 5 },
61 { 43, 13, 0 },
62 { 44, 13, 1 },
63 { 45, 13, 3 },
64 { 46, 14, 0 },
65 { 47, 14, 2 },
66 { 48, 14, 3 },
67 { 49, 15, 2 },
68 { 50, 16, 0 },
69 };
70
71 static void lpddr4_checkctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, u32 *ctlgrpirqstatus, u32 *ctlmasterintflag);
72 static void lpddr4_checkctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, u32 *ctlgrpirqstatus, u32 *ctlmasterintflag);
73 static void lpddr4_checkctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, u32 *ctlgrpirqstatus, u32 *ctlmasterintflag);
74 static void lpddr4_ackctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr);
75 static void lpddr4_ackctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr);
76 static void lpddr4_ackctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr);
77
lpddr4_enablepiinitiator(const lpddr4_privatedata * pd)78 u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd)
79 {
80 u32 result = 0U;
81 u32 regval = 0U;
82
83 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
84
85 regval = CPS_FLD_SET(LPDDR4__PI_NORMAL_LVL_SEQ__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_NORMAL_LVL_SEQ__REG)));
86 CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_NORMAL_LVL_SEQ__REG)), regval);
87 regval = CPS_FLD_SET(LPDDR4__PI_INIT_LVL_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)));
88 CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)), regval);
89 return result;
90 }
91
lpddr4_getctlinterruptmask(const lpddr4_privatedata * pd,u64 * mask)92 u32 lpddr4_getctlinterruptmask(const lpddr4_privatedata *pd, u64 *mask)
93 {
94 u32 result = 0U;
95
96 result = lpddr4_getctlinterruptmasksf(pd, mask);
97 if (result == (u32)0) {
98 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
99 *mask = (u64)(CPS_FLD_READ(LPDDR4__INT_MASK_MASTER__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_MASTER__REG))));
100 }
101 return result;
102 }
103
lpddr4_setctlinterruptmask(const lpddr4_privatedata * pd,const u64 * mask)104 u32 lpddr4_setctlinterruptmask(const lpddr4_privatedata *pd, const u64 *mask)
105 {
106 u32 result;
107 u32 regval = 0;
108 const u64 ui64one = 1ULL;
109 const u32 ui32irqcount = (u32)32U;
110
111 result = lpddr4_setctlinterruptmasksf(pd, mask);
112 if ((result == (u32)0) && (ui32irqcount < 64U)) {
113 if (*mask >= (ui64one << ui32irqcount))
114 result = (u32)EINVAL;
115 }
116
117 if (result == (u32)0) {
118 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
119 regval = CPS_FLD_WRITE(LPDDR4__INT_MASK_MASTER__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_MASTER__REG)), *mask);
120 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_MASTER__REG), regval);
121 }
122 return result;
123 }
124
lpddr4_checkctlinterrupt_4(lpddr4_ctlregs * ctlregbase,lpddr4_intr_ctlinterrupt intr,u32 * ctlgrpirqstatus,u32 * ctlmasterintflag)125 static void lpddr4_checkctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr,
126 u32 *ctlgrpirqstatus, u32 *ctlmasterintflag)
127 {
128 if ((intr >= LPDDR4_INTR_INIT_MEM_RESET_DONE) && (intr <= LPDDR4_INTR_INIT_POWER_ON_STATE))
129 *ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_INIT__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_INIT__REG)));
130 else if ((intr >= LPDDR4_INTR_MRR_ERROR) && (intr <= LPDDR4_INTR_MR_WRITE_DONE))
131 *ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_MODE__REG));
132 else if (intr == LPDDR4_INTR_BIST_DONE)
133 *ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_BIST__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_BIST__REG)));
134 else if (intr == LPDDR4_INTR_PARITY_ERROR)
135 *ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_PARITY__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_PARITY__REG)));
136 else
137 *ctlmasterintflag = (u32)1U;
138 }
139
lpddr4_checkctlinterrupt_3(lpddr4_ctlregs * ctlregbase,lpddr4_intr_ctlinterrupt intr,u32 * ctlgrpirqstatus,u32 * ctlmasterintflag)140 static void lpddr4_checkctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr,
141 u32 *ctlgrpirqstatus, u32 *ctlmasterintflag)
142 {
143 if ((intr >= LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE) && (intr <= LPDDR4_INTR_FREQ_DFS_SW_DONE))
144 *ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_FREQ__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_FREQ__REG)));
145 else if ((intr >= LPDDR4_INTR_LP_DONE) && (intr <= LPDDR4_INTR_LP_TIMEOUT))
146 *ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_LOWPOWER__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_LOWPOWER__REG)));
147 else
148 lpddr4_checkctlinterrupt_4(ctlregbase, intr, ctlgrpirqstatus, ctlmasterintflag);
149 }
150
lpddr4_checkctlinterrupt_2(lpddr4_ctlregs * ctlregbase,lpddr4_intr_ctlinterrupt intr,u32 * ctlgrpirqstatus,u32 * ctlmasterintflag)151 static void lpddr4_checkctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr,
152 u32 *ctlgrpirqstatus, u32 *ctlmasterintflag)
153 {
154 if (intr <= LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX)
155 *ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_TIMEOUT__REG));
156 else if ((intr >= LPDDR4_INTR_TRAINING_ZQ_STATUS) && (intr <= LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT))
157 *ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_TRAINING__REG));
158 else if ((intr >= LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS) && (intr <= LPDDR4_INTR_USERIF_INVAL_SETTING))
159 *ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_USERIF__REG));
160 else if ((intr >= LPDDR4_INTR_MISC_MRR_TRAFFIC) && (intr <= LPDDR4_INTR_MISC_REFRESH_STATUS))
161 *ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_MISC__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_MISC__REG)));
162 else if ((intr >= LPDDR4_INTR_DFI_UPDATE_ERROR) && (intr <= LPDDR4_INTR_DFI_TIMEOUT))
163 *ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_DFI__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_DFI__REG)));
164 else
165 lpddr4_checkctlinterrupt_3(ctlregbase, intr, ctlgrpirqstatus, ctlmasterintflag);
166 }
167
lpddr4_checkctlinterrupt(const lpddr4_privatedata * pd,lpddr4_intr_ctlinterrupt intr,bool * irqstatus)168 u32 lpddr4_checkctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus)
169 {
170 u32 result;
171 u32 ctlmasterirqstatus = 0U;
172 u32 ctlgrpirqstatus = 0U;
173 u32 ctlmasterintflag = 0U;
174
175 result = LPDDR4_INTR_CheckCtlIntSF(pd, intr, irqstatus);
176 if (result == (u32)0) {
177 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
178 ctlmasterirqstatus = (CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_MASTER__REG)) & (~((u32)1 << 31)));
179
180 lpddr4_checkctlinterrupt_2(ctlregbase, intr, &ctlgrpirqstatus, &ctlmasterintflag);
181
182 if ((ctlintmap[intr][INT_SHIFT] < WORD_SHIFT) && (ctlintmap[intr][GRP_SHIFT] < WORD_SHIFT)) {
183 if ((((ctlmasterirqstatus >> ctlintmap[intr][GRP_SHIFT]) & LPDDR4_BIT_MASK) > 0U) &&
184 (((ctlgrpirqstatus >> ctlintmap[intr][INT_SHIFT]) & LPDDR4_BIT_MASK) > 0U) &&
185 (ctlmasterintflag == (u32)0))
186 *irqstatus = true;
187 else if ((((ctlmasterirqstatus >> ctlintmap[intr][GRP_SHIFT]) & LPDDR4_BIT_MASK) > 0U) &&
188 (ctlmasterintflag == (u32)1U))
189 *irqstatus = true;
190 else
191 *irqstatus = false;
192 }
193 }
194 return result;
195 }
196
lpddr4_ackctlinterrupt_4(lpddr4_ctlregs * ctlregbase,lpddr4_intr_ctlinterrupt intr)197 static void lpddr4_ackctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr)
198 {
199 u32 regval = 0;
200
201 if ((intr >= LPDDR4_INTR_MRR_ERROR) && (intr <= LPDDR4_INTR_MR_WRITE_DONE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
202 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_MODE__REG), (u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]);
203 } else if ((intr == LPDDR4_INTR_BIST_DONE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
204 regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_BIST__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_BIST__REG)),
205 (u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]);
206 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_BIST__REG), regval);
207 } else if ((intr == LPDDR4_INTR_PARITY_ERROR) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
208 regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_PARITY__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_PARITY__REG)),
209 (u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]);
210 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_PARITY__REG), regval);
211 } else {
212 }
213 }
214
lpddr4_ackctlinterrupt_3(lpddr4_ctlregs * ctlregbase,lpddr4_intr_ctlinterrupt intr)215 static void lpddr4_ackctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr)
216 {
217 u32 regval = 0;
218
219 if ((intr >= LPDDR4_INTR_LP_DONE) && (intr <= LPDDR4_INTR_LP_TIMEOUT) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
220 regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_LOWPOWER__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_LOWPOWER__REG)),
221 (u32)((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
222 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_LOWPOWER__REG), regval);
223 } else if ((intr >= LPDDR4_INTR_INIT_MEM_RESET_DONE) && (intr <= LPDDR4_INTR_INIT_POWER_ON_STATE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
224 regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_INIT__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_INIT__REG)),
225 (u32)((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
226 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_INIT__REG), regval);
227 } else {
228 lpddr4_ackctlinterrupt_4(ctlregbase, intr);
229 }
230 }
231
lpddr4_ackctlinterrupt_2(lpddr4_ctlregs * ctlregbase,lpddr4_intr_ctlinterrupt intr)232 static void lpddr4_ackctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr)
233 {
234 u32 regval = 0;
235
236 if ((intr >= LPDDR4_INTR_DFI_UPDATE_ERROR) && (intr <= LPDDR4_INTR_DFI_TIMEOUT) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
237 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_DFI__REG), (u32)((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
238 } else if ((intr >= LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE) && (intr <= LPDDR4_INTR_FREQ_DFS_SW_DONE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
239 regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_FREQ__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_FREQ__REG)),
240 (u32)((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
241 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_FREQ__REG), regval);
242 } else {
243 lpddr4_ackctlinterrupt_3(ctlregbase, intr);
244 }
245 }
246
lpddr4_ackctlinterrupt(const lpddr4_privatedata * pd,lpddr4_intr_ctlinterrupt intr)247 u32 lpddr4_ackctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr)
248 {
249 u32 result;
250
251 result = LPDDR4_INTR_AckCtlIntSF(pd, intr);
252 if ((result == (u32)0) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
253 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
254 if (intr <= LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX)
255 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_TIMEOUT__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
256 else if ((intr >= LPDDR4_INTR_TRAINING_ZQ_STATUS) && (intr <= LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT))
257 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_TRAINING__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
258 else if ((intr >= LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS) && (intr <= LPDDR4_INTR_USERIF_INVAL_SETTING))
259 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_USERIF__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
260 else if ((intr >= LPDDR4_INTR_MISC_MRR_TRAFFIC) && (intr <= LPDDR4_INTR_MISC_REFRESH_STATUS))
261 CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_MISC__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
262 else
263 lpddr4_ackctlinterrupt_2(ctlregbase, intr);
264 }
265
266 return result;
267 }
268
lpddr4_checkwrlvlerror(lpddr4_ctlregs * ctlregbase,lpddr4_debuginfo * debuginfo,bool * errfoundptr)269 void lpddr4_checkwrlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
270 {
271 u32 regval;
272 u32 errbitmask = 0U;
273 u32 snum;
274 volatile u32 *regaddress;
275
276 regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_WRLVL_STATUS_OBS_0__REG));
277 errbitmask = ((u32)LPDDR4_BIT_MASK << (u32)12U);
278 for (snum = 0U; snum < DSLICE_NUM; snum++) {
279 regval = CPS_REG_READ(regaddress);
280 if ((regval & errbitmask) != 0U) {
281 debuginfo->wrlvlerror = CDN_TRUE;
282 *errfoundptr = true;
283 }
284 regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
285 }
286 }
287
lpddr4_getdebuginitinfo(const lpddr4_privatedata * pd,lpddr4_debuginfo * debuginfo)288 u32 lpddr4_getdebuginitinfo(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo)
289 {
290 u32 result = 0U;
291 bool errorfound = false;
292
293 result = lpddr4_getdebuginitinfosf(pd, debuginfo);
294 if (result == (u32)0) {
295 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
296 lpddr4_seterrors(ctlregbase, debuginfo, (u8 *)&errorfound);
297 lpddr4_setsettings(ctlregbase, errorfound);
298 errorfound = (bool)lpddr4_checklvlerrors(pd, debuginfo, errorfound);
299 }
300
301 if (errorfound == (bool)true)
302 result = (u32)EPROTO;
303
304 return result;
305 }
306
lpddr4_getreducmode(const lpddr4_privatedata * pd,lpddr4_reducmode * mode)307 u32 lpddr4_getreducmode(const lpddr4_privatedata *pd, lpddr4_reducmode *mode)
308 {
309 u32 result = 0U;
310
311 result = lpddr4_getreducmodesf(pd, mode);
312 if (result == (u32)0) {
313 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
314 if (CPS_FLD_READ(LPDDR4__MEM_DP_REDUCTION__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MEM_DP_REDUCTION__REG))) == 0U)
315 *mode = LPDDR4_REDUC_ON;
316 else
317 *mode = LPDDR4_REDUC_OFF;
318 }
319 return result;
320 }
321
lpddr4_setreducmode(const lpddr4_privatedata * pd,const lpddr4_reducmode * mode)322 u32 lpddr4_setreducmode(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode)
323 {
324 u32 result = 0U;
325 u32 regval = 0U;
326
327 result = lpddr4_setreducmodesf(pd, mode);
328 if (result == (u32)0) {
329 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
330 regval = (u32)CPS_FLD_WRITE(LPDDR4__MEM_DP_REDUCTION__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MEM_DP_REDUCTION__REG)), *mode);
331 CPS_REG_WRITE(&(ctlregbase->LPDDR4__MEM_DP_REDUCTION__REG), regval);
332 }
333 return result;
334 }
335
lpddr4_checkmmrreaderror(const lpddr4_privatedata * pd,u64 * mmrvalue,u8 * mrrstatus)336 u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mrrstatus)
337 {
338 u32 lowerdata;
339 lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
340 u32 result = (u32)0;
341
342 if (lpddr4_pollctlirq(pd, LPDDR4_INTR_MRR_ERROR, 100) == 0U) {
343 *mrrstatus = (u8)CPS_FLD_READ(LPDDR4__MRR_ERROR_STATUS__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MRR_ERROR_STATUS__REG)));
344 *mmrvalue = (u64)0;
345 result = (u32)EIO;
346 } else {
347 *mrrstatus = (u8)0;
348 lowerdata = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA__REG));
349 *mmrvalue = (u64)((*mmrvalue << WORD_SHIFT) | lowerdata);
350 result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MR_READ_DONE);
351 }
352 return result;
353 }
354
355 #ifdef REG_WRITE_VERIF
356
lpddr4_getdslicemask(u32 dslicenum,u32 arrayoffset)357 u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset)
358 {
359 u32 rwmask = 0U;
360
361 switch (dslicenum) {
362 case 0:
363 if (arrayoffset < DSLICE0_REG_COUNT)
364 rwmask = g_lpddr4_data_slice_0_rw_mask[arrayoffset];
365 break;
366 default:
367 if (arrayoffset < DSLICE1_REG_COUNT)
368 rwmask = g_lpddr4_data_slice_1_rw_mask[arrayoffset];
369 break;
370 }
371 return rwmask;
372 }
373 #endif
374
lpddr4_geteccenable(const lpddr4_privatedata * pd,lpddr4_eccenable * eccparam)375 u32 lpddr4_geteccenable(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam)
376 {
377 u32 result = 0U;
378
379 result = lpddr4_geteccenablesf(pd, eccparam);
380 if (result == (u32)0) {
381 *eccparam = LPDDR4_ECC_DISABLED;
382 result = (u32)EOPNOTSUPP;
383 }
384
385 return result;
386 }
lpddr4_seteccenable(const lpddr4_privatedata * pd,const lpddr4_eccenable * eccparam)387 u32 lpddr4_seteccenable(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam)
388 {
389 u32 result = 0U;
390
391 result = lpddr4_seteccenablesf(pd, eccparam);
392 if (result == (u32)0)
393 result = (u32)EOPNOTSUPP;
394
395 return result;
396 }
397