1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Cadence DDR Driver 4 * 5 * Copyright (C) 2012-2021 Cadence Design Systems, Inc. 6 * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ 7 */ 8 9 #ifndef LPDDR4_16BIT_H 10 #define LPDDR4_16BIT_H 11 12 #define DSLICE_NUM (2U) 13 #define ASLICE_NUM (3U) 14 15 #ifdef __cplusplus 16 extern "C" { 17 #endif 18 19 #define DSLICE0_REG_COUNT (126U) 20 #define DSLICE1_REG_COUNT (126U) 21 #define ASLICE0_REG_COUNT (42U) 22 #define ASLICE1_REG_COUNT (42U) 23 #define ASLICE2_REG_COUNT (42U) 24 #define PHY_CORE_REG_COUNT (126U) 25 26 #define GRP_SHIFT 1 27 #define INT_SHIFT 2 28 29 #ifdef __cplusplus 30 } 31 #endif 32 33 #endif /* LPDDR4_16BIT_H */ 34