1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2010
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * Contributor: Mahavir Jain <mjain@marvell.com>
7 */
8
9 #include <common.h>
10 #include <cpu_func.h>
11 #include <init.h>
12 #include <time.h>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/armada100.h>
15 #include <asm/global_data.h>
16 #include <linux/delay.h>
17
18 /*
19 * Timer registers
20 * Refer Section A.6 in Datasheet
21 */
22 struct armd1tmr_registers {
23 u32 clk_ctrl; /* Timer clk control reg */
24 u32 match[9]; /* Timer match registers */
25 u32 count[3]; /* Timer count registers */
26 u32 status[3];
27 u32 ie[3];
28 u32 preload[3]; /* Timer preload value */
29 u32 preload_ctrl[3];
30 u32 wdt_match_en;
31 u32 wdt_match_r;
32 u32 wdt_val;
33 u32 wdt_sts;
34 u32 icr[3];
35 u32 wdt_icr;
36 u32 cer; /* Timer count enable reg */
37 u32 cmr;
38 u32 ilr[3];
39 u32 wcr;
40 u32 wfar;
41 u32 wsar;
42 u32 cvwr;
43 };
44
45 #define TIMER 0 /* Use TIMER 0 */
46 /* Each timer has 3 match registers */
47 #define MATCH_CMP(x) ((3 * TIMER) + x)
48 #define TIMER_LOAD_VAL 0xffffffff
49 #define COUNT_RD_REQ 0x1
50
51 DECLARE_GLOBAL_DATA_PTR;
52 /* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
53
54 /* For preventing risk of instability in reading counter value,
55 * first set read request to register cvwr and then read same
56 * register after it captures counter value.
57 */
read_timer(void)58 ulong read_timer(void)
59 {
60 struct armd1tmr_registers *armd1timers =
61 (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
62 volatile int loop=100;
63
64 writel(COUNT_RD_REQ, &armd1timers->cvwr);
65 while (loop--);
66 return(readl(&armd1timers->cvwr));
67 }
68
get_timer_masked(void)69 static ulong get_timer_masked(void)
70 {
71 ulong now = read_timer();
72
73 if (now >= gd->arch.tbl) {
74 /* normal mode */
75 gd->arch.tbu += now - gd->arch.tbl;
76 } else {
77 /* we have an overflow ... */
78 gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
79 }
80 gd->arch.tbl = now;
81
82 return gd->arch.tbu;
83 }
84
get_timer(ulong base)85 ulong get_timer(ulong base)
86 {
87 return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
88 base);
89 }
90
__udelay(unsigned long usec)91 void __udelay(unsigned long usec)
92 {
93 ulong delayticks;
94 ulong endtime;
95
96 delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
97 endtime = get_timer_masked() + delayticks;
98
99 while (get_timer_masked() < endtime);
100 }
101
102 /*
103 * init the Timer
104 */
timer_init(void)105 int timer_init(void)
106 {
107 struct armd1apb1_registers *apb1clkres =
108 (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
109 struct armd1tmr_registers *armd1timers =
110 (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
111
112 /* Enable Timer clock at 3.25 MHZ */
113 writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
114
115 /* load value into timer */
116 writel(0x0, &armd1timers->clk_ctrl);
117 /* Use Timer 0 Match Resiger 0 */
118 writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
119 /* Preload value is 0 */
120 writel(0x0, &armd1timers->preload[TIMER]);
121 /* Enable match comparator 0 for Timer 0 */
122 writel(0x1, &armd1timers->preload_ctrl[TIMER]);
123
124 /* Enable timer 0 */
125 writel(0x1, &armd1timers->cer);
126 /* init the gd->arch.tbu and gd->arch.tbl value */
127 gd->arch.tbl = read_timer();
128 gd->arch.tbu = 0;
129
130 return 0;
131 }
132
133 #define MPMU_APRR_WDTR (1<<4)
134 #define TMR_WFAR 0xbaba /* WDT Register First key */
135 #define TMP_WSAR 0xeb10 /* WDT Register Second key */
136
137 /*
138 * This function uses internal Watchdog Timer
139 * based reset mechanism.
140 * Steps to write watchdog registers (protected access)
141 * 1. Write key value to TMR_WFAR reg.
142 * 2. Write key value to TMP_WSAR reg.
143 * 3. Perform write operation.
144 */
reset_cpu(void)145 void reset_cpu(void)
146 {
147 struct armd1mpmu_registers *mpmu =
148 (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
149 struct armd1tmr_registers *armd1timers =
150 (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
151 u32 val;
152
153 /* negate hardware reset to the WDT after system reset */
154 val = readl(&mpmu->aprr);
155 val = val | MPMU_APRR_WDTR;
156 writel(val, &mpmu->aprr);
157
158 /* reset/enable WDT clock */
159 writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
160 readl(&mpmu->wdtpcr);
161 writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
162 readl(&mpmu->wdtpcr);
163
164 /* clear previous WDT status */
165 writel(TMR_WFAR, &armd1timers->wfar);
166 writel(TMP_WSAR, &armd1timers->wsar);
167 writel(0, &armd1timers->wdt_sts);
168
169 /* set match counter */
170 writel(TMR_WFAR, &armd1timers->wfar);
171 writel(TMP_WSAR, &armd1timers->wsar);
172 writel(0xf, &armd1timers->wdt_match_r);
173
174 /* enable WDT reset */
175 writel(TMR_WFAR, &armd1timers->wfar);
176 writel(TMP_WSAR, &armd1timers->wsar);
177 writel(0x3, &armd1timers->wdt_match_en);
178
179 while(1);
180 }
181
182 /*
183 * This function is derived from PowerPC code (read timebase as long long).
184 * On ARM it just returns the timer value.
185 */
get_ticks(void)186 unsigned long long get_ticks(void)
187 {
188 return get_timer(0);
189 }
190
191 /*
192 * This function is derived from PowerPC code (timebase clock frequency).
193 * On ARM it returns the number of timer ticks per second.
194 */
get_tbclk(void)195 ulong get_tbclk(void)
196 {
197 return (ulong)CONFIG_SYS_HZ;
198 }
199