1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com)
7 *
8 * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
9 */
10
11 #include <common.h>
12 #include <init.h>
13 #include <asm/global_data.h>
14 #include <asm/immap.h>
15 #include <asm/io.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 #define PERIOD 13 /* system bus period in ns */
20 #define SDRAM_TREFI 7800 /* in ns */
21
checkboard(void)22 int checkboard(void)
23 {
24 puts("Board: ");
25 puts("Freescale MCF5275 EVB\n");
26 return 0;
27 };
28
dram_init(void)29 int dram_init(void)
30 {
31 sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
32 gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
33
34 /* Enable SDRAM */
35 out_be16(&gpio_reg->par_sdram, 0x3FF);
36
37 /* Set up chip select */
38 out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE);
39 out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V);
40
41 /* Set up timing */
42 out_be32(&sdp->sdcfg1, 0x83711630);
43 out_be32(&sdp->sdcfg2, 0x46770000);
44
45 /* Enable clock */
46 out_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE);
47
48 /* Set precharge */
49 setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
50
51 /* Dummy write to start SDRAM */
52 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
53
54 /* Send LEMR */
55 setbits_be32(&sdp->sdmr,
56 MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) |
57 MCF_SDRAMC_SDMR_CMD);
58 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
59
60 /* Send LMR */
61 out_be32(&sdp->sdmr, 0x058d0000);
62 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
63
64 /* Stop sending commands */
65 clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
66
67 /* Set precharge */
68 setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
69 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
70
71 /* Stop manual precharge, send 2 IREF */
72 clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
73 setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF);
74 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
75 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
76
77
78 out_be32(&sdp->sdmr, 0x018d0000);
79 *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
80
81 /* Stop sending commands */
82 clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
83 clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN);
84
85 /* Turn on auto refresh, lock SDMR */
86 out_be32(&sdp->sdcr,
87 MCF_SDRAMC_SDCR_CKE
88 | MCF_SDRAMC_SDCR_REF
89 | MCF_SDRAMC_SDCR_MUX(1)
90 /* 1 added to round up */
91 | MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
92 | MCF_SDRAMC_SDCR_DQS_OE(0x3));
93
94 gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
95
96 return 0;
97 };
98
testdram(void)99 int testdram(void)
100 {
101 /* TODO: XXX XXX XXX */
102 printf("DRAM test not implemented!\n");
103
104 return (0);
105 }
106