1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2015 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __LS1043AQDS_H__ 7 #define __LS1043AQDS_H__ 8 9 #include "ls1043a_common.h" 10 11 #ifndef __ASSEMBLY__ 12 unsigned long get_board_sys_clk(void); 13 unsigned long get_board_ddr_clk(void); 14 #endif 15 16 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 17 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 18 19 #define CONFIG_SKIP_LOWLEVEL_INIT 20 21 #define CONFIG_LAYERSCAPE_NS_ACCESS 22 23 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 24 /* Physical Memory Map */ 25 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 26 27 #define CONFIG_DDR_SPD 28 #define SPD_EEPROM_ADDRESS 0x51 29 #define CONFIG_SYS_SPD_BUS_NUM 0 30 31 #define CONFIG_DDR_ECC 32 #ifdef CONFIG_DDR_ECC 33 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 34 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 35 #endif 36 37 #ifdef CONFIG_SYS_DPAA_FMAN 38 #define RGMII_PHY1_ADDR 0x1 39 #define RGMII_PHY2_ADDR 0x2 40 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 41 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 42 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 43 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 44 /* PHY address on QSGMII riser card on slot 1 */ 45 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4 46 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5 47 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6 48 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7 49 /* PHY address on QSGMII riser card on slot 2 */ 50 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 51 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 52 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA 53 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB 54 #endif 55 56 #ifdef CONFIG_RAMBOOT_PBL 57 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg 58 #endif 59 60 #ifdef CONFIG_NAND_BOOT 61 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg 62 #endif 63 64 #ifdef CONFIG_SD_BOOT 65 #ifdef CONFIG_SD_BOOT_QSPI 66 #define CONFIG_SYS_FSL_PBL_RCW \ 67 board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg 68 #else 69 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg 70 #endif 71 #endif 72 73 /* LPUART */ 74 #ifdef CONFIG_LPUART 75 #define CONFIG_LPUART_32B_REG 76 #endif 77 78 /* SATA */ 79 #define CONFIG_SCSI_AHCI_PLAT 80 81 /* EEPROM */ 82 #define CONFIG_ID_EEPROM 83 #define CONFIG_SYS_I2C_EEPROM_NXID 84 #define CONFIG_SYS_EEPROM_BUS_NUM 0 85 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 86 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 87 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 88 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 89 90 #define CONFIG_SYS_SATA AHCI_BASE_ADDR 91 92 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 93 #define CONFIG_SYS_SCSI_MAX_LUN 1 94 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 95 CONFIG_SYS_SCSI_MAX_LUN) 96 97 /* 98 * IFC Definitions 99 */ 100 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 101 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 102 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 103 CSPR_PORT_SIZE_16 | \ 104 CSPR_MSEL_NOR | \ 105 CSPR_V) 106 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 107 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 108 + 0x8000000) | \ 109 CSPR_PORT_SIZE_16 | \ 110 CSPR_MSEL_NOR | \ 111 CSPR_V) 112 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 113 114 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 115 CSOR_NOR_TRHZ_80) 116 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 117 FTIM0_NOR_TEADC(0x5) | \ 118 FTIM0_NOR_TEAHC(0x5)) 119 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 120 FTIM1_NOR_TRAD_NOR(0x1a) | \ 121 FTIM1_NOR_TSEQRAD_NOR(0x13)) 122 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 123 FTIM2_NOR_TCH(0x4) | \ 124 FTIM2_NOR_TWPH(0xe) | \ 125 FTIM2_NOR_TWP(0x1c)) 126 #define CONFIG_SYS_NOR_FTIM3 0 127 128 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 129 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 130 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 131 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 132 133 #define CONFIG_SYS_FLASH_EMPTY_INFO 134 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 135 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 136 137 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 138 #define CONFIG_SYS_WRITE_SWAPPED_DATA 139 140 /* 141 * NAND Flash Definitions 142 */ 143 #define CONFIG_NAND_FSL_IFC 144 145 #define CONFIG_SYS_NAND_BASE 0x7e800000 146 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 147 148 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 149 150 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 151 | CSPR_PORT_SIZE_8 \ 152 | CSPR_MSEL_NAND \ 153 | CSPR_V) 154 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 155 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 156 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 157 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 158 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 159 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 160 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 161 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 162 163 #define CONFIG_SYS_NAND_ONFI_DETECTION 164 165 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 166 FTIM0_NAND_TWP(0x18) | \ 167 FTIM0_NAND_TWCHT(0x7) | \ 168 FTIM0_NAND_TWH(0xa)) 169 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 170 FTIM1_NAND_TWBE(0x39) | \ 171 FTIM1_NAND_TRR(0xe) | \ 172 FTIM1_NAND_TRP(0x18)) 173 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 174 FTIM2_NAND_TREH(0xa) | \ 175 FTIM2_NAND_TWHRE(0x1e)) 176 #define CONFIG_SYS_NAND_FTIM3 0x0 177 178 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 179 #define CONFIG_SYS_MAX_NAND_DEVICE 1 180 #define CONFIG_MTD_NAND_VERIFY_WRITE 181 182 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 183 #endif 184 185 #ifdef CONFIG_NAND_BOOT 186 #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ 187 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 188 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) 189 #endif 190 191 #if defined(CONFIG_TFABOOT) || \ 192 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 193 #define CONFIG_QIXIS_I2C_ACCESS 194 #define CONFIG_SYS_I2C_EARLY_INIT 195 #endif 196 197 /* 198 * QIXIS Definitions 199 */ 200 #define CONFIG_FSL_QIXIS 201 202 #ifdef CONFIG_FSL_QIXIS 203 #define QIXIS_BASE 0x7fb00000 204 #define QIXIS_BASE_PHYS QIXIS_BASE 205 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 206 #define QIXIS_LBMAP_SWITCH 6 207 #define QIXIS_LBMAP_MASK 0x0f 208 #define QIXIS_LBMAP_SHIFT 0 209 #define QIXIS_LBMAP_DFLTBANK 0x00 210 #define QIXIS_LBMAP_ALTBANK 0x04 211 #define QIXIS_LBMAP_NAND 0x09 212 #define QIXIS_LBMAP_SD 0x00 213 #define QIXIS_LBMAP_SD_QSPI 0xff 214 #define QIXIS_LBMAP_QSPI 0xff 215 #define QIXIS_RCW_SRC_NAND 0x106 216 #define QIXIS_RCW_SRC_SD 0x040 217 #define QIXIS_RCW_SRC_QSPI 0x045 218 #define QIXIS_RST_CTL_RESET 0x41 219 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 220 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 221 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 222 223 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 224 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 225 CSPR_PORT_SIZE_8 | \ 226 CSPR_MSEL_GPCM | \ 227 CSPR_V) 228 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 229 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 230 CSOR_NOR_NOR_MODE_AVD_NOR | \ 231 CSOR_NOR_TRHZ_80) 232 233 /* 234 * QIXIS Timing parameters for IFC GPCM 235 */ 236 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ 237 FTIM0_GPCM_TEADC(0x20) | \ 238 FTIM0_GPCM_TEAHC(0x10)) 239 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ 240 FTIM1_GPCM_TRAD(0x1f)) 241 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ 242 FTIM2_GPCM_TCH(0x8) | \ 243 FTIM2_GPCM_TWP(0xf0)) 244 #define CONFIG_SYS_FPGA_FTIM3 0x0 245 #endif 246 247 #ifdef CONFIG_TFABOOT 248 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 249 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 250 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 251 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 252 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 253 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 254 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 255 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 256 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 257 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 258 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 259 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 260 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 261 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 262 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 263 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 264 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 265 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 266 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 267 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 268 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 269 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 270 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 271 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 272 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 273 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 274 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 275 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 276 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 277 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 278 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 279 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 280 #else 281 #ifdef CONFIG_NAND_BOOT 282 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 283 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 284 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 285 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 286 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 287 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 288 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 289 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 290 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 291 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 292 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 293 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 294 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 295 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 296 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 297 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 298 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 299 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 300 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 301 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 302 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 303 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 304 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 305 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 306 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 307 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 308 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 309 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 310 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 311 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 312 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 313 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 314 #else 315 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 316 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 317 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 318 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 319 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 320 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 321 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 322 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 323 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 324 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 325 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 326 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 327 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 328 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 329 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 330 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 331 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 332 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 333 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 334 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 335 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 336 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 337 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 338 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 339 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 340 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 341 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 342 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 343 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 344 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 345 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 346 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 347 #endif 348 #endif 349 350 /* 351 * I2C bus multiplexer 352 */ 353 #define I2C_MUX_PCA_ADDR_PRI 0x77 354 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 355 #define I2C_RETIMER_ADDR 0x18 356 #define I2C_MUX_CH_DEFAULT 0x8 357 #define I2C_MUX_CH_CH7301 0xC 358 #define I2C_MUX_CH5 0xD 359 #define I2C_MUX_CH7 0xF 360 361 #define I2C_MUX_CH_VOL_MONITOR 0xa 362 363 /* Voltage monitor on channel 2*/ 364 #define I2C_VOL_MONITOR_ADDR 0x40 365 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 366 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 367 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 368 369 #define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv" 370 #ifndef CONFIG_SPL_BUILD 371 #define CONFIG_VID 372 #endif 373 #define CONFIG_VOL_MONITOR_IR36021_SET 374 #define CONFIG_VOL_MONITOR_INA220 375 /* The lowest and highest voltage allowed for LS1043AQDS */ 376 #define VDD_MV_MIN 819 377 #define VDD_MV_MAX 1212 378 379 /* 380 * Miscellaneous configurable options 381 */ 382 383 #define CONFIG_SYS_HZ 1000 384 385 #define CONFIG_SYS_INIT_SP_OFFSET \ 386 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 387 388 #ifdef CONFIG_SPL_BUILD 389 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 390 #else 391 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 392 #endif 393 394 /* 395 * Environment 396 */ 397 398 #define CONFIG_CMDLINE_TAG 399 400 #include <asm/fsl_secure_boot.h> 401 402 #endif /* __LS1043AQDS_H__ */ 403