1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * From coreboot src/soc/intel/broadwell/include/soc/pm.h
4  *
5  * Copyright (C) 2016 Google, Inc.
6  */
7 
8 #ifndef __ASM_ARCH_PM_H
9 #define __ASM_ARCH_PM_H
10 
11 #define PM1_STS			0x00
12 #define  WAK_STS		(1 << 15)
13 #define  PCIEXPWAK_STS		(1 << 14)
14 #define  PRBTNOR_STS		(1 << 11)
15 #define  RTC_STS		(1 << 10)
16 #define  PWRBTN_STS		(1 << 8)
17 #define  GBL_STS		(1 << 5)
18 #define  BM_STS			(1 << 4)
19 #define  TMROF_STS		(1 << 0)
20 #define PM1_EN			0x02
21 #define  PCIEXPWAK_DIS		(1 << 14)
22 #define  RTC_EN			(1 << 10)
23 #define  PWRBTN_EN		(1 << 8)
24 #define  GBL_EN			(1 << 5)
25 #define  TMROF_EN		(1 << 0)
26 #define PM1_CNT			0x04
27 #define  SLP_EN			(1 << 13)
28 #define  SLP_TYP		(7 << 10)
29 #define   SLP_TYP_SHIFT         10
30 #define   SLP_TYP_S0		0
31 #define   SLP_TYP_S1		1
32 #define   SLP_TYP_S3		5
33 #define   SLP_TYP_S4		6
34 #define   SLP_TYP_S5		7
35 #define  GBL_RLS		(1 << 2)
36 #define  BM_RLD			(1 << 1)
37 #define  SCI_EN			(1 << 0)
38 #define PM1_TMR			0x08
39 #define SMI_EN			0x30
40 #define  XHCI_SMI_EN		(1 << 31)
41 #define  ME_SMI_EN		(1 << 30)
42 #define  GPIO_UNLOCK_SMI_EN	(1 << 27)
43 #define  INTEL_USB2_EN		(1 << 18)
44 #define  LEGACY_USB2_EN		(1 << 17)
45 #define  PERIODIC_EN		(1 << 14)
46 #define  TCO_EN			(1 << 13)
47 #define  MCSMI_EN		(1 << 11)
48 #define  BIOS_RLS		(1 <<  7)
49 #define  SWSMI_TMR_EN		(1 <<  6)
50 #define  APMC_EN		(1 <<  5)
51 #define  SLP_SMI_EN		(1 <<  4)
52 #define  LEGACY_USB_EN		(1 <<  3)
53 #define  BIOS_EN		(1 <<  2)
54 #define  EOS			(1 <<  1)
55 #define  GBL_SMI_EN		(1 <<  0)
56 #define SMI_STS			0x34
57 #define UPWRC			0x3c
58 #define  UPWRC_WS		(1 << 8)
59 #define  UPWRC_WE		(1 << 1)
60 #define  UPWRC_SMI		(1 << 0)
61 #define GPE_CNTL		0x42
62 #define  SWGPE_CTRL		(1 << 1)
63 #define DEVACT_STS		0x44
64 #define PM2_CNT			0x50
65 #define TCO1_CNT		0x60
66 #define  TCO_TMR_HLT		(1 << 11)
67 #define TCO1_STS		0x64
68 #define  DMISCI_STS		(1 << 9)
69 #define TCO2_STS		0x66
70 #define  TCO2_STS_SECOND_TO	(1 << 1)
71 
72 #define GPE0_REG_MAX		4
73 #define GPE0_REG_SIZE		32
74 #define GPE0_STS(x)		(0x80 + (x * 4))
75 #define  GPE_31_0		0	/* 0x80/0x90 = GPE[31:0] */
76 #define  GPE_63_32		1	/* 0x84/0x94 = GPE[63:32] */
77 #define  GPE_94_64		2	/* 0x88/0x98 = GPE[94:64] */
78 #define  GPE_STD		3	/* 0x8c/0x9c = Standard GPE */
79 #define   WADT_STS		(1 << 18)
80 #define   GP27_STS		(1 << 16)
81 #define   PME_B0_STS		(1 << 13)
82 #define   ME_SCI_STS		(1 << 12)
83 #define   PME_STS		(1 << 11)
84 #define   BATLOW_STS		(1 << 10)
85 #define   PCI_EXP_STS		(1 << 9)
86 #define   SMB_WAK_STS		(1 << 7)
87 #define   TCOSCI_STS		(1 << 6)
88 #define   SWGPE_STS		(1 << 2)
89 #define   HOT_PLUG_STS		(1 << 1)
90 #define GPE0_EN(x)		(0x90 + (x * 4))
91 #define   WADT_en		(1 << 18)
92 #define   GP27_EN		(1 << 16)
93 #define   PME_B0_EN		(1 << 13)
94 #define   ME_SCI_EN		(1 << 12)
95 #define   PME_EN		(1 << 11)
96 #define   BATLOW_EN		(1 << 10)
97 #define   PCI_EXP_EN		(1 << 9)
98 #define   TCOSCI_EN		(1 << 6)
99 #define   SWGPE_EN		(1 << 2)
100 #define   HOT_PLUG_EN		(1 << 1)
101 
102 #define MAINBOARD_POWER_OFF	0
103 #define MAINBOARD_POWER_ON	1
104 #define MAINBOARD_POWER_KEEP	2
105 
106 #define SLEEP_STATE_S0		0
107 #define SLEEP_STATE_S3		3
108 #define SLEEP_STATE_S5		5
109 
110 struct chipset_power_state {
111 	uint16_t pm1_sts;
112 	uint16_t pm1_en;
113 	uint32_t pm1_cnt;
114 	uint16_t tco1_sts;
115 	uint16_t tco2_sts;
116 	uint32_t gpe0_sts[4];
117 	uint32_t gpe0_en[4];
118 	uint16_t gen_pmcon1;
119 	uint16_t gen_pmcon2;
120 	uint16_t gen_pmcon3;
121 	int prev_sleep_state;
122 	uint16_t hsio_version;
123 	uint16_t hsio_checksum;
124 };
125 
126 void power_state_get(struct udevice *pch_dev, struct chipset_power_state *ps);
127 
128 #endif
129