1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2017 NXP 4 * 5 * Peng Fan <peng.fan at nxp.com> 6 */ 7 8 #include <linux/bitops.h> 9 10 #ifdef CONFIG_IMX8MQ 11 #include <asm/arch/clock_imx8mq.h> 12 #elif defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) || \ 13 defined(CONFIG_IMX8MP) 14 #include <asm/arch/clock_imx8mm.h> 15 #else 16 #error "Error no clock.h" 17 #endif 18 19 #define MHZ(X) ((X) * 1000000UL) 20 21 /* Mainly for compatible to imx common code. */ 22 enum mxc_clock { 23 MXC_ARM_CLK = 0, 24 MXC_IPG_CLK, 25 MXC_CSPI_CLK, 26 MXC_ESDHC_CLK, 27 MXC_ESDHC2_CLK, 28 MXC_ESDHC3_CLK, 29 MXC_I2C_CLK, 30 MXC_UART_CLK, 31 MXC_QSPI_CLK, 32 }; 33 34 enum clk_slice_type { 35 CORE_CLOCK_SLICE, 36 BUS_CLOCK_SLICE, 37 IP_CLOCK_SLICE, 38 AHB_CLOCK_SLICE, 39 IPG_CLOCK_SLICE, 40 CORE_SEL_CLOCK_SLICE, 41 DRAM_SEL_CLOCK_SLICE, 42 }; 43 44 enum root_pre_div { 45 CLK_ROOT_PRE_DIV1 = 0, 46 CLK_ROOT_PRE_DIV2, 47 CLK_ROOT_PRE_DIV3, 48 CLK_ROOT_PRE_DIV4, 49 CLK_ROOT_PRE_DIV5, 50 CLK_ROOT_PRE_DIV6, 51 CLK_ROOT_PRE_DIV7, 52 CLK_ROOT_PRE_DIV8, 53 }; 54 55 enum root_post_div { 56 CLK_ROOT_POST_DIV1 = 0, 57 CLK_ROOT_POST_DIV2, 58 CLK_ROOT_POST_DIV3, 59 CLK_ROOT_POST_DIV4, 60 CLK_ROOT_POST_DIV5, 61 CLK_ROOT_POST_DIV6, 62 CLK_ROOT_POST_DIV7, 63 CLK_ROOT_POST_DIV8, 64 CLK_ROOT_POST_DIV9, 65 CLK_ROOT_POST_DIV10, 66 CLK_ROOT_POST_DIV11, 67 CLK_ROOT_POST_DIV12, 68 CLK_ROOT_POST_DIV13, 69 CLK_ROOT_POST_DIV14, 70 CLK_ROOT_POST_DIV15, 71 CLK_ROOT_POST_DIV16, 72 CLK_ROOT_POST_DIV17, 73 CLK_ROOT_POST_DIV18, 74 CLK_ROOT_POST_DIV19, 75 CLK_ROOT_POST_DIV20, 76 CLK_ROOT_POST_DIV21, 77 CLK_ROOT_POST_DIV22, 78 CLK_ROOT_POST_DIV23, 79 CLK_ROOT_POST_DIV24, 80 CLK_ROOT_POST_DIV25, 81 CLK_ROOT_POST_DIV26, 82 CLK_ROOT_POST_DIV27, 83 CLK_ROOT_POST_DIV28, 84 CLK_ROOT_POST_DIV29, 85 CLK_ROOT_POST_DIV30, 86 CLK_ROOT_POST_DIV31, 87 CLK_ROOT_POST_DIV32, 88 CLK_ROOT_POST_DIV33, 89 CLK_ROOT_POST_DIV34, 90 CLK_ROOT_POST_DIV35, 91 CLK_ROOT_POST_DIV36, 92 CLK_ROOT_POST_DIV37, 93 CLK_ROOT_POST_DIV38, 94 CLK_ROOT_POST_DIV39, 95 CLK_ROOT_POST_DIV40, 96 CLK_ROOT_POST_DIV41, 97 CLK_ROOT_POST_DIV42, 98 CLK_ROOT_POST_DIV43, 99 CLK_ROOT_POST_DIV44, 100 CLK_ROOT_POST_DIV45, 101 CLK_ROOT_POST_DIV46, 102 CLK_ROOT_POST_DIV47, 103 CLK_ROOT_POST_DIV48, 104 CLK_ROOT_POST_DIV49, 105 CLK_ROOT_POST_DIV50, 106 CLK_ROOT_POST_DIV51, 107 CLK_ROOT_POST_DIV52, 108 CLK_ROOT_POST_DIV53, 109 CLK_ROOT_POST_DIV54, 110 CLK_ROOT_POST_DIV55, 111 CLK_ROOT_POST_DIV56, 112 CLK_ROOT_POST_DIV57, 113 CLK_ROOT_POST_DIV58, 114 CLK_ROOT_POST_DIV59, 115 CLK_ROOT_POST_DIV60, 116 CLK_ROOT_POST_DIV61, 117 CLK_ROOT_POST_DIV62, 118 CLK_ROOT_POST_DIV63, 119 CLK_ROOT_POST_DIV64, 120 }; 121 122 struct clk_root_map { 123 enum clk_root_index entry; 124 enum clk_slice_type slice_type; 125 u32 slice_index; 126 u8 src_mux[8]; 127 }; 128 129 struct ccm_ccgr { 130 u32 ccgr; 131 u32 ccgr_set; 132 u32 ccgr_clr; 133 u32 ccgr_tog; 134 }; 135 136 struct ccm_root { 137 u32 target_root; 138 u32 target_root_set; 139 u32 target_root_clr; 140 u32 target_root_tog; 141 u32 misc; 142 u32 misc_set; 143 u32 misc_clr; 144 u32 misc_tog; 145 u32 nm_post; 146 u32 nm_post_root_set; 147 u32 nm_post_root_clr; 148 u32 nm_post_root_tog; 149 u32 nm_pre; 150 u32 nm_pre_root_set; 151 u32 nm_pre_root_clr; 152 u32 nm_pre_root_tog; 153 u32 db_post; 154 u32 db_post_root_set; 155 u32 db_post_root_clr; 156 u32 db_post_root_tog; 157 u32 db_pre; 158 u32 db_pre_root_set; 159 u32 db_pre_root_clr; 160 u32 db_pre_root_tog; 161 u32 reserved[4]; 162 u32 access_ctrl; 163 u32 access_ctrl_root_set; 164 u32 access_ctrl_root_clr; 165 u32 access_ctrl_root_tog; 166 }; 167 168 struct ccm_reg { 169 u32 reserved_0[4096]; 170 struct ccm_ccgr ccgr_array[192]; 171 u32 reserved_1[3328]; 172 struct ccm_root core_root[5]; 173 u32 reserved_2[352]; 174 struct ccm_root bus_root[12]; 175 u32 reserved_3[128]; 176 struct ccm_root ahb_ipg_root[4]; 177 u32 reserved_4[384]; 178 struct ccm_root dram_sel; 179 struct ccm_root core_sel; 180 u32 reserved_5[448]; 181 struct ccm_root ip_root[78]; 182 }; 183 184 enum enet_freq { 185 ENET_25MHZ = 0, 186 ENET_50MHZ, 187 ENET_125MHZ, 188 }; 189 190 #define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k) \ 191 { \ 192 .clk = (_rate), \ 193 .alt_root_sel = (_m), \ 194 .alt_pre_div = (_p), \ 195 .apb_root_sel = (_s), \ 196 .apb_pre_div = (_k), \ 197 } 198 199 struct dram_bypass_clk_setting { 200 ulong clk; 201 int alt_root_sel; 202 enum root_pre_div alt_pre_div; 203 int apb_root_sel; 204 enum root_pre_div apb_pre_div; 205 }; 206 207 #define CCGR_CLK_ON_MASK 0x03 208 #define CLK_SRC_ON_MASK 0x03 209 210 #define CLK_ROOT_ON BIT(28) 211 #define CLK_ROOT_OFF (0 << 28) 212 #define CLK_ROOT_ENABLE_MASK BIT(28) 213 #define CLK_ROOT_ENABLE_SHIFT 28 214 #define CLK_ROOT_SOURCE_SEL(n) (((n) & 0x7) << 24) 215 216 /* For SEL, only use 1 bit */ 217 #define CLK_ROOT_SRC_MUX_MASK 0x07000000 218 #define CLK_ROOT_SRC_MUX_SHIFT 24 219 #define CLK_ROOT_SRC_0 0x00000000 220 #define CLK_ROOT_SRC_1 0x01000000 221 #define CLK_ROOT_SRC_2 0x02000000 222 #define CLK_ROOT_SRC_3 0x03000000 223 #define CLK_ROOT_SRC_4 0x04000000 224 #define CLK_ROOT_SRC_5 0x05000000 225 #define CLK_ROOT_SRC_6 0x06000000 226 #define CLK_ROOT_SRC_7 0x07000000 227 228 #define CLK_ROOT_PRE_DIV_MASK (0x00070000) 229 #define CLK_ROOT_PRE_DIV_SHIFT 16 230 #define CLK_ROOT_PRE_DIV(n) (((n) << 16) & 0x00070000) 231 232 #define CLK_ROOT_AUDO_SLOW_EN 0x1000 233 234 #define CLK_ROOT_AUDO_DIV_MASK 0x700 235 #define CLK_ROOT_AUDO_DIV_SHIFT 0x8 236 #define CLK_ROOT_AUDO_DIV(n) (((n) << 8) & 0x700) 237 238 /* For CORE: mask is 0x7; For IPG: mask is 0x3 */ 239 #define CLK_ROOT_POST_DIV_MASK 0x3f 240 #define CLK_ROOT_CORE_POST_DIV_MASK 0x7 241 #define CLK_ROOT_IPG_POST_DIV_MASK 0x3 242 #define CLK_ROOT_POST_DIV_SHIFT 0 243 #define CLK_ROOT_POST_DIV(n) ((n) & 0x3f) 244 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000 245 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 246 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000 247 #define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x07000000 248 #define ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M 0x01000000 249 #define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 250 #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000 251 252 void dram_pll_init(ulong pll_val); 253 void dram_enable_bypass(ulong clk_val); 254 void dram_disable_bypass(void); 255 u32 imx_get_fecclk(void); 256 u32 imx_get_uartclk(void); 257 int clock_init(void); 258 void init_clk_usdhc(u32 index); 259 void init_uart_clk(u32 index); 260 void init_wdog_clk(void); 261 unsigned int mxc_get_clock(enum mxc_clock clk); 262 int clock_enable(enum clk_ccgr_index index, bool enable); 263 int clock_root_enabled(enum clk_root_index clock_id); 264 int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div, 265 enum root_post_div post_div, enum clk_root_src clock_src); 266 int clock_set_target_val(enum clk_root_index clock_id, u32 val); 267 int clock_get_target_val(enum clk_root_index clock_id, u32 *val); 268 int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div); 269 int clock_get_postdiv(enum clk_root_index clock_id, 270 enum root_post_div *post_div); 271 int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src); 272 void mxs_set_lcdclk(u32 base_addr, u32 freq); 273 int set_clk_qspi(void); 274 void enable_ocotp_clk(unsigned char enable); 275 int enable_i2c_clk(unsigned char enable, unsigned int i2c_num); 276 int set_clk_enet(enum enet_freq type); 277 int set_clk_eqos(enum enet_freq type); 278 void hab_caam_clock_enable(unsigned char enable); 279