1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2003 4 * Josef Baumgartner <josef.baumgartner@telex.de> 5 * 6 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. 7 * Hayden Fraser (Hayden.Fraser@freescale.com) 8 */ 9 10 #include <common.h> 11 #include <clock_legacy.h> 12 #include <asm/global_data.h> 13 #include <asm/processor.h> 14 #include <asm/immap.h> 15 #include <asm/io.h> 16 #include <linux/delay.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */ get_clocks(void)21int get_clocks(void) 22 { 23 #if defined(CONFIG_M5208) 24 pll_t *pll = (pll_t *) MMAP_PLL; 25 26 out_8(&pll->odr, CONFIG_SYS_PLL_ODR); 27 out_8(&pll->fdr, CONFIG_SYS_PLL_FDR); 28 #endif 29 30 #if defined(CONFIG_M5249) || defined(CONFIG_M5253) 31 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); 32 unsigned long pllcr; 33 34 #ifndef CONFIG_SYS_PLL_BYPASS 35 36 #ifdef CONFIG_M5249 37 /* Setup the PLL to run at the specified speed */ 38 #ifdef CONFIG_SYS_FAST_CLK 39 pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ 40 #else 41 pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ 42 #endif 43 #endif /* CONFIG_M5249 */ 44 45 #ifdef CONFIG_M5253 46 pllcr = CONFIG_SYS_PLLCR; 47 #endif /* CONFIG_M5253 */ 48 49 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ 50 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ 51 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ 52 pllcr ^= 0x00000001; /* Set pll bypass to 1 */ 53 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ 54 udelay(0x20); /* Wait for a lock ... */ 55 #endif /* #ifndef CONFIG_SYS_PLL_BYPASS */ 56 57 #endif /* CONFIG_M5249 || CONFIG_M5253 */ 58 59 #if defined(CONFIG_M5275) 60 pll_t *pll = (pll_t *)(MMAP_PLL); 61 62 /* Setup PLL */ 63 out_be32(&pll->syncr, 0x01080000); 64 while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK)) 65 ; 66 out_be32(&pll->syncr, 0x01000000); 67 while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK)) 68 ; 69 #endif 70 71 gd->cpu_clk = CONFIG_SYS_CLK; 72 #if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \ 73 defined(CONFIG_M5271) || defined(CONFIG_M5275) 74 gd->bus_clk = gd->cpu_clk / 2; 75 #else 76 gd->bus_clk = gd->cpu_clk; 77 #endif 78 79 #ifdef CONFIG_SYS_I2C_FSL 80 gd->arch.i2c1_clk = gd->bus_clk; 81 #ifdef CONFIG_SYS_I2C2_FSL_OFFSET 82 gd->arch.i2c2_clk = gd->bus_clk; 83 #endif 84 #endif 85 86 return (0); 87 } 88