1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * 4 * Common functions for OMAP4/5 based boards 5 * 6 * (C) Copyright 2010 7 * Texas Instruments, <www.ti.com> 8 * 9 * Author : 10 * Aneesh V <aneesh@ti.com> 11 * Steve Sakoman <steve@sakoman.com> 12 */ 13 14 #include <common.h> 15 #include <cpu_func.h> 16 #include <log.h> 17 #include <asm/cache.h> 18 #include <asm/global_data.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 /* 23 * Without LPAE short descriptors are used 24 * Set C - Cache Bit3 25 * Set B - Buffer Bit2 26 * The last 2 bits set to 0b10 27 * Do Not set XN bit4 28 * So value is 0xe 29 * 30 * With LPAE cache configuration happens via MAIR0 register 31 * AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF. 32 * 0xFF maps to Cache writeback with Read and Write Allocate set 33 * The bits[1:0] should have the value 0b01 for the first level 34 * descriptor. 35 * So the value is 0xd 36 */ 37 38 #ifdef CONFIG_ARMV7_LPAE 39 #define ARMV7_DCACHE_POLICY DCACHE_WRITEALLOC 40 #else 41 #define ARMV7_DCACHE_POLICY DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK 42 #endif 43 enable_caches(void)44void enable_caches(void) 45 { 46 47 /* Enable I cache if not enabled */ 48 if (!icache_status()) 49 icache_enable(); 50 51 dcache_enable(); 52 } 53 dram_bank_mmu_setup(int bank)54void dram_bank_mmu_setup(int bank) 55 { 56 struct bd_info *bd = gd->bd; 57 int i; 58 59 u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; 60 u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT; 61 u32 end = start + size; 62 63 debug("%s: bank: %d\n", __func__, bank); 64 for (i = start; i < end; i++) 65 set_section_dcache(i, ARMV7_DCACHE_POLICY); 66 } 67