1// SPDX-License-Identifier: GPL-2.0 2// 3// Copyright 2014 Freescale Semiconductor, Inc. 4 5#include <dt-bindings/clock/imx6sx-clock.h> 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/input/input.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include "imx6sx-pinfunc.h" 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 /* 15 * The decompressor and also some bootloaders rely on a 16 * pre-existing /chosen node to be available to insert the 17 * command line and merge other ATAGS info. 18 */ 19 chosen {}; 20 21 aliases { 22 can0 = &flexcan1; 23 can1 = &flexcan2; 24 ethernet0 = &fec1; 25 ethernet1 = &fec2; 26 gpio0 = &gpio1; 27 gpio1 = &gpio2; 28 gpio2 = &gpio3; 29 gpio3 = &gpio4; 30 gpio4 = &gpio5; 31 gpio5 = &gpio6; 32 gpio6 = &gpio7; 33 i2c0 = &i2c1; 34 i2c1 = &i2c2; 35 i2c2 = &i2c3; 36 i2c3 = &i2c4; 37 mmc0 = &usdhc1; 38 mmc1 = &usdhc2; 39 mmc2 = &usdhc3; 40 mmc3 = &usdhc4; 41 serial0 = &uart1; 42 serial1 = &uart2; 43 serial2 = &uart3; 44 serial3 = &uart4; 45 serial4 = &uart5; 46 serial5 = &uart6; 47 spi0 = &ecspi1; 48 spi1 = &ecspi2; 49 spi2 = &ecspi3; 50 spi3 = &ecspi4; 51 spi4 = &ecspi5; 52 usbphy0 = &usbphy1; 53 usbphy1 = &usbphy2; 54 }; 55 56 cpus { 57 #address-cells = <1>; 58 #size-cells = <0>; 59 60 cpu0: cpu@0 { 61 compatible = "arm,cortex-a9"; 62 device_type = "cpu"; 63 reg = <0>; 64 next-level-cache = <&L2>; 65 operating-points = < 66 /* kHz uV */ 67 996000 1250000 68 792000 1175000 69 396000 1075000 70 198000 975000 71 >; 72 fsl,soc-operating-points = < 73 /* ARM kHz SOC uV */ 74 996000 1175000 75 792000 1175000 76 396000 1175000 77 198000 1175000 78 >; 79 clock-latency = <61036>; /* two CLK32 periods */ 80 #cooling-cells = <2>; 81 clocks = <&clks IMX6SX_CLK_ARM>, 82 <&clks IMX6SX_CLK_PLL2_PFD2>, 83 <&clks IMX6SX_CLK_STEP>, 84 <&clks IMX6SX_CLK_PLL1_SW>, 85 <&clks IMX6SX_CLK_PLL1_SYS>; 86 clock-names = "arm", "pll2_pfd2_396m", "step", 87 "pll1_sw", "pll1_sys"; 88 arm-supply = <®_arm>; 89 soc-supply = <®_soc>; 90 }; 91 }; 92 93 ckil: clock-ckil { 94 compatible = "fixed-clock"; 95 #clock-cells = <0>; 96 clock-frequency = <32768>; 97 clock-output-names = "ckil"; 98 }; 99 100 osc: clock-osc { 101 compatible = "fixed-clock"; 102 #clock-cells = <0>; 103 clock-frequency = <24000000>; 104 clock-output-names = "osc"; 105 }; 106 107 ipp_di0: clock-ipp-di0 { 108 compatible = "fixed-clock"; 109 #clock-cells = <0>; 110 clock-frequency = <0>; 111 clock-output-names = "ipp_di0"; 112 }; 113 114 ipp_di1: clock-ipp-di1 { 115 compatible = "fixed-clock"; 116 #clock-cells = <0>; 117 clock-frequency = <0>; 118 clock-output-names = "ipp_di1"; 119 }; 120 121 anaclk1: clock-anaclk1 { 122 compatible = "fixed-clock"; 123 #clock-cells = <0>; 124 clock-frequency = <0>; 125 clock-output-names = "anaclk1"; 126 }; 127 128 anaclk2: clock-anaclk2 { 129 compatible = "fixed-clock"; 130 #clock-cells = <0>; 131 clock-frequency = <0>; 132 clock-output-names = "anaclk2"; 133 }; 134 135 tempmon: tempmon { 136 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; 137 interrupt-parent = <&gpc>; 138 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 139 fsl,tempmon = <&anatop>; 140 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; 141 nvmem-cell-names = "calib", "temp_grade"; 142 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; 143 }; 144 145 pmu { 146 compatible = "arm,cortex-a9-pmu"; 147 interrupt-parent = <&gpc>; 148 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 149 }; 150 151 usbphynop1: usbphynop1 { 152 compatible = "usb-nop-xceiv"; 153 #phy-cells = <0>; 154 }; 155 156 soc { 157 #address-cells = <1>; 158 #size-cells = <1>; 159 compatible = "simple-bus"; 160 interrupt-parent = <&gpc>; 161 ranges; 162 163 ocram_s: sram@8f8000 { 164 compatible = "mmio-sram"; 165 reg = <0x008f8000 0x4000>; 166 clocks = <&clks IMX6SX_CLK_OCRAM_S>; 167 }; 168 169 ocram: sram@900000 { 170 compatible = "mmio-sram"; 171 reg = <0x00900000 0x20000>; 172 clocks = <&clks IMX6SX_CLK_OCRAM>; 173 }; 174 175 intc: interrupt-controller@a01000 { 176 compatible = "arm,cortex-a9-gic"; 177 #interrupt-cells = <3>; 178 interrupt-controller; 179 reg = <0x00a01000 0x1000>, 180 <0x00a00100 0x100>; 181 interrupt-parent = <&intc>; 182 }; 183 184 L2: l2-cache@a02000 { 185 compatible = "arm,pl310-cache"; 186 reg = <0x00a02000 0x1000>; 187 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 188 cache-unified; 189 cache-level = <2>; 190 arm,tag-latency = <4 2 3>; 191 arm,data-latency = <4 2 3>; 192 }; 193 194 gpu: gpu@1800000 { 195 compatible = "vivante,gc"; 196 reg = <0x01800000 0x4000>; 197 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 198 clocks = <&clks IMX6SX_CLK_GPU>, 199 <&clks IMX6SX_CLK_GPU>, 200 <&clks IMX6SX_CLK_GPU>; 201 clock-names = "bus", "core", "shader"; 202 power-domains = <&pd_pu>; 203 }; 204 205 dma_apbh: dma-apbh@1804000 { 206 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh"; 207 reg = <0x01804000 0x2000>; 208 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 212 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 213 #dma-cells = <1>; 214 dma-channels = <4>; 215 clocks = <&clks IMX6SX_CLK_APBH_DMA>; 216 }; 217 218 gpmi: gpmi-nand@1806000{ 219 compatible = "fsl,imx6sx-gpmi-nand"; 220 #address-cells = <1>; 221 #size-cells = <1>; 222 reg = <0x01806000 0x2000>, <0x01808000 0x4000>; 223 reg-names = "gpmi-nand", "bch"; 224 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 225 interrupt-names = "bch"; 226 clocks = <&clks IMX6SX_CLK_GPMI_IO>, 227 <&clks IMX6SX_CLK_GPMI_APB>, 228 <&clks IMX6SX_CLK_GPMI_BCH>, 229 <&clks IMX6SX_CLK_GPMI_BCH_APB>, 230 <&clks IMX6SX_CLK_PER1_BCH>; 231 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", 232 "gpmi_bch_apb", "per1_bch"; 233 dmas = <&dma_apbh 0>; 234 dma-names = "rx-tx"; 235 status = "disabled"; 236 }; 237 238 aips1: aips-bus@2000000 { 239 compatible = "fsl,aips-bus", "simple-bus"; 240 #address-cells = <1>; 241 #size-cells = <1>; 242 reg = <0x02000000 0x100000>; 243 ranges; 244 245 spba-bus@2000000 { 246 compatible = "fsl,spba-bus", "simple-bus"; 247 #address-cells = <1>; 248 #size-cells = <1>; 249 reg = <0x02000000 0x40000>; 250 ranges; 251 252 spdif: spdif@2004000 { 253 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif"; 254 reg = <0x02004000 0x4000>; 255 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 256 dmas = <&sdma 14 18 0>, 257 <&sdma 15 18 0>; 258 dma-names = "rx", "tx"; 259 clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>, 260 <&clks IMX6SX_CLK_OSC>, 261 <&clks IMX6SX_CLK_SPDIF>, 262 <&clks 0>, <&clks 0>, <&clks 0>, 263 <&clks IMX6SX_CLK_IPG>, 264 <&clks 0>, <&clks 0>, 265 <&clks IMX6SX_CLK_SPBA>; 266 clock-names = "core", "rxtx0", 267 "rxtx1", "rxtx2", 268 "rxtx3", "rxtx4", 269 "rxtx5", "rxtx6", 270 "rxtx7", "spba"; 271 status = "disabled"; 272 }; 273 274 ecspi1: spi@2008000 { 275 #address-cells = <1>; 276 #size-cells = <0>; 277 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 278 reg = <0x02008000 0x4000>; 279 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 280 clocks = <&clks IMX6SX_CLK_ECSPI1>, 281 <&clks IMX6SX_CLK_ECSPI1>; 282 clock-names = "ipg", "per"; 283 status = "disabled"; 284 }; 285 286 ecspi2: spi@200c000 { 287 #address-cells = <1>; 288 #size-cells = <0>; 289 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 290 reg = <0x0200c000 0x4000>; 291 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 292 clocks = <&clks IMX6SX_CLK_ECSPI2>, 293 <&clks IMX6SX_CLK_ECSPI2>; 294 clock-names = "ipg", "per"; 295 status = "disabled"; 296 }; 297 298 ecspi3: spi@2010000 { 299 #address-cells = <1>; 300 #size-cells = <0>; 301 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 302 reg = <0x02010000 0x4000>; 303 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&clks IMX6SX_CLK_ECSPI3>, 305 <&clks IMX6SX_CLK_ECSPI3>; 306 clock-names = "ipg", "per"; 307 status = "disabled"; 308 }; 309 310 ecspi4: spi@2014000 { 311 #address-cells = <1>; 312 #size-cells = <0>; 313 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 314 reg = <0x02014000 0x4000>; 315 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 316 clocks = <&clks IMX6SX_CLK_ECSPI4>, 317 <&clks IMX6SX_CLK_ECSPI4>; 318 clock-names = "ipg", "per"; 319 status = "disabled"; 320 }; 321 322 uart1: serial@2020000 { 323 compatible = "fsl,imx6sx-uart", 324 "fsl,imx6q-uart", "fsl,imx21-uart"; 325 reg = <0x02020000 0x4000>; 326 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&clks IMX6SX_CLK_UART_IPG>, 328 <&clks IMX6SX_CLK_UART_SERIAL>; 329 clock-names = "ipg", "per"; 330 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; 331 dma-names = "rx", "tx"; 332 status = "disabled"; 333 }; 334 335 esai: esai@2024000 { 336 reg = <0x02024000 0x4000>; 337 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&clks IMX6SX_CLK_ESAI_IPG>, 339 <&clks IMX6SX_CLK_ESAI_MEM>, 340 <&clks IMX6SX_CLK_ESAI_EXTAL>, 341 <&clks IMX6SX_CLK_ESAI_IPG>, 342 <&clks IMX6SX_CLK_SPBA>; 343 clock-names = "core", "mem", "extal", 344 "fsys", "spba"; 345 status = "disabled"; 346 }; 347 348 ssi1: ssi@2028000 { 349 #sound-dai-cells = <0>; 350 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; 351 reg = <0x02028000 0x4000>; 352 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 353 clocks = <&clks IMX6SX_CLK_SSI1_IPG>, 354 <&clks IMX6SX_CLK_SSI1>; 355 clock-names = "ipg", "baud"; 356 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; 357 dma-names = "rx", "tx"; 358 fsl,fifo-depth = <15>; 359 status = "disabled"; 360 }; 361 362 ssi2: ssi@202c000 { 363 #sound-dai-cells = <0>; 364 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; 365 reg = <0x0202c000 0x4000>; 366 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&clks IMX6SX_CLK_SSI2_IPG>, 368 <&clks IMX6SX_CLK_SSI2>; 369 clock-names = "ipg", "baud"; 370 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; 371 dma-names = "rx", "tx"; 372 fsl,fifo-depth = <15>; 373 status = "disabled"; 374 }; 375 376 ssi3: ssi@2030000 { 377 #sound-dai-cells = <0>; 378 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; 379 reg = <0x02030000 0x4000>; 380 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&clks IMX6SX_CLK_SSI3_IPG>, 382 <&clks IMX6SX_CLK_SSI3>; 383 clock-names = "ipg", "baud"; 384 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; 385 dma-names = "rx", "tx"; 386 fsl,fifo-depth = <15>; 387 status = "disabled"; 388 }; 389 390 asrc: asrc@2034000 { 391 reg = <0x02034000 0x4000>; 392 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&clks IMX6SX_CLK_ASRC_MEM>, 394 <&clks IMX6SX_CLK_ASRC_IPG>, 395 <&clks IMX6SX_CLK_SPDIF>, 396 <&clks IMX6SX_CLK_SPBA>; 397 clock-names = "mem", "ipg", "asrck", "spba"; 398 dmas = <&sdma 17 20 1>, <&sdma 18 20 1>, 399 <&sdma 19 20 1>, <&sdma 20 20 1>, 400 <&sdma 21 20 1>, <&sdma 22 20 1>; 401 dma-names = "rxa", "rxb", "rxc", 402 "txa", "txb", "txc"; 403 status = "okay"; 404 }; 405 }; 406 407 pwm1: pwm@2080000 { 408 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 409 reg = <0x02080000 0x4000>; 410 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 411 clocks = <&clks IMX6SX_CLK_PWM1>, 412 <&clks IMX6SX_CLK_PWM1>; 413 clock-names = "ipg", "per"; 414 #pwm-cells = <2>; 415 }; 416 417 pwm2: pwm@2084000 { 418 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 419 reg = <0x02084000 0x4000>; 420 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&clks IMX6SX_CLK_PWM2>, 422 <&clks IMX6SX_CLK_PWM2>; 423 clock-names = "ipg", "per"; 424 #pwm-cells = <2>; 425 }; 426 427 pwm3: pwm@2088000 { 428 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 429 reg = <0x02088000 0x4000>; 430 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 431 clocks = <&clks IMX6SX_CLK_PWM3>, 432 <&clks IMX6SX_CLK_PWM3>; 433 clock-names = "ipg", "per"; 434 #pwm-cells = <2>; 435 }; 436 437 pwm4: pwm@208c000 { 438 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 439 reg = <0x0208c000 0x4000>; 440 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 441 clocks = <&clks IMX6SX_CLK_PWM4>, 442 <&clks IMX6SX_CLK_PWM4>; 443 clock-names = "ipg", "per"; 444 #pwm-cells = <2>; 445 }; 446 447 flexcan1: can@2090000 { 448 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; 449 reg = <0x02090000 0x4000>; 450 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&clks IMX6SX_CLK_CAN1_IPG>, 452 <&clks IMX6SX_CLK_CAN1_SERIAL>; 453 clock-names = "ipg", "per"; 454 fsl,stop-mode = <&gpr 0x10 1 0x10 17>; 455 status = "disabled"; 456 }; 457 458 flexcan2: can@2094000 { 459 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; 460 reg = <0x02094000 0x4000>; 461 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&clks IMX6SX_CLK_CAN2_IPG>, 463 <&clks IMX6SX_CLK_CAN2_SERIAL>; 464 clock-names = "ipg", "per"; 465 fsl,stop-mode = <&gpr 0x10 2 0x10 18>; 466 status = "disabled"; 467 }; 468 469 gpt: gpt@2098000 { 470 compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt"; 471 reg = <0x02098000 0x4000>; 472 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 473 clocks = <&clks IMX6SX_CLK_GPT_BUS>, 474 <&clks IMX6SX_CLK_GPT_3M>; 475 clock-names = "ipg", "per"; 476 }; 477 478 gpio1: gpio@209c000 { 479 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 480 reg = <0x0209c000 0x4000>; 481 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 483 gpio-controller; 484 #gpio-cells = <2>; 485 interrupt-controller; 486 #interrupt-cells = <2>; 487 gpio-ranges = <&iomuxc 0 5 26>; 488 }; 489 490 gpio2: gpio@20a0000 { 491 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 492 reg = <0x020a0000 0x4000>; 493 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 495 gpio-controller; 496 #gpio-cells = <2>; 497 interrupt-controller; 498 #interrupt-cells = <2>; 499 gpio-ranges = <&iomuxc 0 31 20>; 500 }; 501 502 gpio3: gpio@20a4000 { 503 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 504 reg = <0x020a4000 0x4000>; 505 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 507 gpio-controller; 508 #gpio-cells = <2>; 509 interrupt-controller; 510 #interrupt-cells = <2>; 511 gpio-ranges = <&iomuxc 0 51 29>; 512 }; 513 514 gpio4: gpio@20a8000 { 515 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 516 reg = <0x020a8000 0x4000>; 517 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 519 gpio-controller; 520 #gpio-cells = <2>; 521 interrupt-controller; 522 #interrupt-cells = <2>; 523 gpio-ranges = <&iomuxc 0 80 32>; 524 }; 525 526 gpio5: gpio@20ac000 { 527 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 528 reg = <0x020ac000 0x4000>; 529 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 531 gpio-controller; 532 #gpio-cells = <2>; 533 interrupt-controller; 534 #interrupt-cells = <2>; 535 gpio-ranges = <&iomuxc 0 112 24>; 536 }; 537 538 gpio6: gpio@20b0000 { 539 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 540 reg = <0x020b0000 0x4000>; 541 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 543 gpio-controller; 544 #gpio-cells = <2>; 545 interrupt-controller; 546 #interrupt-cells = <2>; 547 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>; 548 }; 549 550 gpio7: gpio@20b4000 { 551 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 552 reg = <0x020b4000 0x4000>; 553 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 555 gpio-controller; 556 #gpio-cells = <2>; 557 interrupt-controller; 558 #interrupt-cells = <2>; 559 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>; 560 }; 561 562 kpp: kpp@20b8000 { 563 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp"; 564 reg = <0x020b8000 0x4000>; 565 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 566 clocks = <&clks IMX6SX_CLK_IPG>; 567 status = "disabled"; 568 }; 569 570 wdog1: wdog@20bc000 { 571 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; 572 reg = <0x020bc000 0x4000>; 573 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&clks IMX6SX_CLK_IPG>; 575 }; 576 577 wdog2: wdog@20c0000 { 578 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; 579 reg = <0x020c0000 0x4000>; 580 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&clks IMX6SX_CLK_IPG>; 582 status = "disabled"; 583 }; 584 585 clks: ccm@20c4000 { 586 compatible = "fsl,imx6sx-ccm"; 587 reg = <0x020c4000 0x4000>; 588 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 590 #clock-cells = <1>; 591 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>; 592 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2"; 593 }; 594 595 anatop: anatop@20c8000 { 596 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop", 597 "syscon", "simple-bus"; 598 reg = <0x020c8000 0x1000>; 599 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 602 603 reg_vdd1p1: regulator-1p1 { 604 compatible = "fsl,anatop-regulator"; 605 regulator-name = "vdd1p1"; 606 regulator-min-microvolt = <1000000>; 607 regulator-max-microvolt = <1200000>; 608 regulator-always-on; 609 anatop-reg-offset = <0x110>; 610 anatop-vol-bit-shift = <8>; 611 anatop-vol-bit-width = <5>; 612 anatop-min-bit-val = <4>; 613 anatop-min-voltage = <800000>; 614 anatop-max-voltage = <1375000>; 615 anatop-enable-bit = <0>; 616 }; 617 618 reg_vdd3p0: regulator-3p0 { 619 compatible = "fsl,anatop-regulator"; 620 regulator-name = "vdd3p0"; 621 regulator-min-microvolt = <2800000>; 622 regulator-max-microvolt = <3150000>; 623 regulator-always-on; 624 anatop-reg-offset = <0x120>; 625 anatop-vol-bit-shift = <8>; 626 anatop-vol-bit-width = <5>; 627 anatop-min-bit-val = <0>; 628 anatop-min-voltage = <2625000>; 629 anatop-max-voltage = <3400000>; 630 anatop-enable-bit = <0>; 631 }; 632 633 reg_vdd2p5: regulator-2p5 { 634 compatible = "fsl,anatop-regulator"; 635 regulator-name = "vdd2p5"; 636 regulator-min-microvolt = <2250000>; 637 regulator-max-microvolt = <2750000>; 638 regulator-always-on; 639 anatop-reg-offset = <0x130>; 640 anatop-vol-bit-shift = <8>; 641 anatop-vol-bit-width = <5>; 642 anatop-min-bit-val = <0>; 643 anatop-min-voltage = <2100000>; 644 anatop-max-voltage = <2875000>; 645 anatop-enable-bit = <0>; 646 }; 647 648 reg_arm: regulator-vddcore { 649 compatible = "fsl,anatop-regulator"; 650 regulator-name = "vddarm"; 651 regulator-min-microvolt = <725000>; 652 regulator-max-microvolt = <1450000>; 653 regulator-always-on; 654 anatop-reg-offset = <0x140>; 655 anatop-vol-bit-shift = <0>; 656 anatop-vol-bit-width = <5>; 657 anatop-delay-reg-offset = <0x170>; 658 anatop-delay-bit-shift = <24>; 659 anatop-delay-bit-width = <2>; 660 anatop-min-bit-val = <1>; 661 anatop-min-voltage = <725000>; 662 anatop-max-voltage = <1450000>; 663 }; 664 665 reg_pcie: regulator-vddpcie { 666 compatible = "fsl,anatop-regulator"; 667 regulator-name = "vddpcie"; 668 regulator-min-microvolt = <725000>; 669 regulator-max-microvolt = <1450000>; 670 anatop-reg-offset = <0x140>; 671 anatop-vol-bit-shift = <9>; 672 anatop-vol-bit-width = <5>; 673 anatop-delay-reg-offset = <0x170>; 674 anatop-delay-bit-shift = <26>; 675 anatop-delay-bit-width = <2>; 676 anatop-min-bit-val = <1>; 677 anatop-min-voltage = <725000>; 678 anatop-max-voltage = <1450000>; 679 }; 680 681 reg_soc: regulator-vddsoc { 682 compatible = "fsl,anatop-regulator"; 683 regulator-name = "vddsoc"; 684 regulator-min-microvolt = <725000>; 685 regulator-max-microvolt = <1450000>; 686 regulator-always-on; 687 anatop-reg-offset = <0x140>; 688 anatop-vol-bit-shift = <18>; 689 anatop-vol-bit-width = <5>; 690 anatop-delay-reg-offset = <0x170>; 691 anatop-delay-bit-shift = <28>; 692 anatop-delay-bit-width = <2>; 693 anatop-min-bit-val = <1>; 694 anatop-min-voltage = <725000>; 695 anatop-max-voltage = <1450000>; 696 }; 697 }; 698 699 usbphy1: usbphy@20c9000 { 700 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; 701 reg = <0x020c9000 0x1000>; 702 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 703 clocks = <&clks IMX6SX_CLK_USBPHY1>; 704 fsl,anatop = <&anatop>; 705 }; 706 707 usbphy2: usbphy@20ca000 { 708 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; 709 reg = <0x020ca000 0x1000>; 710 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&clks IMX6SX_CLK_USBPHY2>; 712 fsl,anatop = <&anatop>; 713 }; 714 715 snvs: snvs@20cc000 { 716 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 717 reg = <0x020cc000 0x4000>; 718 719 snvs_rtc: snvs-rtc-lp { 720 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 721 regmap = <&snvs>; 722 offset = <0x34>; 723 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 724 }; 725 726 snvs_poweroff: snvs-poweroff { 727 compatible = "syscon-poweroff"; 728 regmap = <&snvs>; 729 offset = <0x38>; 730 value = <0x60>; 731 mask = <0x60>; 732 status = "disabled"; 733 }; 734 735 snvs_pwrkey: snvs-powerkey { 736 compatible = "fsl,sec-v4.0-pwrkey"; 737 regmap = <&snvs>; 738 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 739 linux,keycode = <KEY_POWER>; 740 wakeup-source; 741 status = "disabled"; 742 }; 743 }; 744 745 epit1: epit@20d0000 { 746 reg = <0x020d0000 0x4000>; 747 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 748 }; 749 750 epit2: epit@20d4000 { 751 reg = <0x020d4000 0x4000>; 752 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 753 }; 754 755 src: src@20d8000 { 756 compatible = "fsl,imx6sx-src", "fsl,imx51-src"; 757 reg = <0x020d8000 0x4000>; 758 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 760 #reset-cells = <1>; 761 }; 762 763 gpc: gpc@20dc000 { 764 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc"; 765 reg = <0x020dc000 0x4000>; 766 interrupt-controller; 767 #interrupt-cells = <3>; 768 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 769 interrupt-parent = <&intc>; 770 clocks = <&clks IMX6SX_CLK_IPG>; 771 clock-names = "ipg"; 772 773 pgc { 774 #address-cells = <1>; 775 #size-cells = <0>; 776 777 power-domain@0 { 778 reg = <0>; 779 #power-domain-cells = <0>; 780 }; 781 782 pd_pu: power-domain@1 { 783 reg = <1>; 784 #power-domain-cells = <0>; 785 power-supply = <®_soc>; 786 clocks = <&clks IMX6SX_CLK_GPU>; 787 }; 788 789 pd_disp: power-domain@2 { 790 reg = <2>; 791 #power-domain-cells = <0>; 792 clocks = <&clks IMX6SX_CLK_PXP_AXI>, 793 <&clks IMX6SX_CLK_DISPLAY_AXI>, 794 <&clks IMX6SX_CLK_LCDIF1_PIX>, 795 <&clks IMX6SX_CLK_LCDIF_APB>, 796 <&clks IMX6SX_CLK_LCDIF2_PIX>, 797 <&clks IMX6SX_CLK_CSI>, 798 <&clks IMX6SX_CLK_VADC>; 799 }; 800 801 pd_pci: power-domain@3 { 802 reg = <3>; 803 #power-domain-cells = <0>; 804 power-supply = <®_pcie>; 805 }; 806 }; 807 }; 808 809 iomuxc: iomuxc@20e0000 { 810 compatible = "fsl,imx6sx-iomuxc"; 811 reg = <0x020e0000 0x4000>; 812 }; 813 814 gpr: iomuxc-gpr@20e4000 { 815 compatible = "fsl,imx6sx-iomuxc-gpr", 816 "fsl,imx6q-iomuxc-gpr", "syscon"; 817 reg = <0x020e4000 0x4000>; 818 }; 819 820 sdma: sdma@20ec000 { 821 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; 822 reg = <0x020ec000 0x4000>; 823 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&clks IMX6SX_CLK_IPG>, 825 <&clks IMX6SX_CLK_SDMA>; 826 clock-names = "ipg", "ahb"; 827 #dma-cells = <3>; 828 /* imx6sx reuses imx6q sdma firmware */ 829 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 830 }; 831 }; 832 833 aips2: aips-bus@2100000 { 834 compatible = "fsl,aips-bus", "simple-bus"; 835 #address-cells = <1>; 836 #size-cells = <1>; 837 reg = <0x02100000 0x100000>; 838 ranges; 839 840 crypto: caam@2100000 { 841 compatible = "fsl,sec-v4.0"; 842 #address-cells = <1>; 843 #size-cells = <1>; 844 reg = <0x2100000 0x10000>; 845 ranges = <0 0x2100000 0x10000>; 846 interrupt-parent = <&intc>; 847 clocks = <&clks IMX6SX_CLK_CAAM_MEM>, 848 <&clks IMX6SX_CLK_CAAM_ACLK>, 849 <&clks IMX6SX_CLK_CAAM_IPG>, 850 <&clks IMX6SX_CLK_EIM_SLOW>; 851 clock-names = "mem", "aclk", "ipg", "emi_slow"; 852 853 sec_jr0: jr0@1000 { 854 compatible = "fsl,sec-v4.0-job-ring"; 855 reg = <0x1000 0x1000>; 856 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 857 }; 858 859 sec_jr1: jr1@2000 { 860 compatible = "fsl,sec-v4.0-job-ring"; 861 reg = <0x2000 0x1000>; 862 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 863 }; 864 }; 865 866 usbotg1: usb@2184000 { 867 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; 868 reg = <0x02184000 0x200>; 869 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&clks IMX6SX_CLK_USBOH3>; 871 fsl,usbphy = <&usbphy1>; 872 fsl,usbmisc = <&usbmisc 0>; 873 fsl,anatop = <&anatop>; 874 ahb-burst-config = <0x0>; 875 tx-burst-size-dword = <0x10>; 876 rx-burst-size-dword = <0x10>; 877 status = "disabled"; 878 }; 879 880 usbotg2: usb@2184200 { 881 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; 882 reg = <0x02184200 0x200>; 883 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 884 clocks = <&clks IMX6SX_CLK_USBOH3>; 885 fsl,usbphy = <&usbphy2>; 886 fsl,usbmisc = <&usbmisc 1>; 887 ahb-burst-config = <0x0>; 888 tx-burst-size-dword = <0x10>; 889 rx-burst-size-dword = <0x10>; 890 status = "disabled"; 891 }; 892 893 usbh: usb@2184400 { 894 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; 895 reg = <0x02184400 0x200>; 896 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 897 clocks = <&clks IMX6SX_CLK_USBOH3>; 898 fsl,usbphy = <&usbphynop1>; 899 fsl,usbmisc = <&usbmisc 2>; 900 phy_type = "hsic"; 901 fsl,anatop = <&anatop>; 902 dr_mode = "host"; 903 ahb-burst-config = <0x0>; 904 tx-burst-size-dword = <0x10>; 905 rx-burst-size-dword = <0x10>; 906 status = "disabled"; 907 }; 908 909 usbmisc: usbmisc@2184800 { 910 #index-cells = <1>; 911 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc"; 912 reg = <0x02184800 0x200>; 913 clocks = <&clks IMX6SX_CLK_USBOH3>; 914 }; 915 916 fec1: ethernet@2188000 { 917 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; 918 reg = <0x02188000 0x4000>; 919 interrupt-names = "int0", "pps"; 920 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 921 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 922 clocks = <&clks IMX6SX_CLK_ENET>, 923 <&clks IMX6SX_CLK_ENET_AHB>, 924 <&clks IMX6SX_CLK_ENET_PTP>, 925 <&clks IMX6SX_CLK_ENET_REF>, 926 <&clks IMX6SX_CLK_ENET_PTP>; 927 clock-names = "ipg", "ahb", "ptp", 928 "enet_clk_ref", "enet_out"; 929 fsl,num-tx-queues = <3>; 930 fsl,num-rx-queues = <3>; 931 status = "disabled"; 932 }; 933 934 mlb: mlb@218c000 { 935 reg = <0x0218c000 0x4000>; 936 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 939 clocks = <&clks IMX6SX_CLK_MLB>; 940 status = "disabled"; 941 }; 942 943 usdhc1: usdhc@2190000 { 944 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 945 reg = <0x02190000 0x4000>; 946 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 947 clocks = <&clks IMX6SX_CLK_USDHC1>, 948 <&clks IMX6SX_CLK_USDHC1>, 949 <&clks IMX6SX_CLK_USDHC1>; 950 clock-names = "ipg", "ahb", "per"; 951 bus-width = <4>; 952 status = "disabled"; 953 }; 954 955 usdhc2: usdhc@2194000 { 956 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 957 reg = <0x02194000 0x4000>; 958 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 959 clocks = <&clks IMX6SX_CLK_USDHC2>, 960 <&clks IMX6SX_CLK_USDHC2>, 961 <&clks IMX6SX_CLK_USDHC2>; 962 clock-names = "ipg", "ahb", "per"; 963 bus-width = <4>; 964 status = "disabled"; 965 }; 966 967 usdhc3: usdhc@2198000 { 968 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 969 reg = <0x02198000 0x4000>; 970 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 971 clocks = <&clks IMX6SX_CLK_USDHC3>, 972 <&clks IMX6SX_CLK_USDHC3>, 973 <&clks IMX6SX_CLK_USDHC3>; 974 clock-names = "ipg", "ahb", "per"; 975 bus-width = <4>; 976 status = "disabled"; 977 }; 978 979 usdhc4: usdhc@219c000 { 980 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 981 reg = <0x0219c000 0x4000>; 982 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&clks IMX6SX_CLK_USDHC4>, 984 <&clks IMX6SX_CLK_USDHC4>, 985 <&clks IMX6SX_CLK_USDHC4>; 986 clock-names = "ipg", "ahb", "per"; 987 bus-width = <4>; 988 status = "disabled"; 989 }; 990 991 i2c1: i2c@21a0000 { 992 #address-cells = <1>; 993 #size-cells = <0>; 994 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 995 reg = <0x021a0000 0x4000>; 996 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 997 clocks = <&clks IMX6SX_CLK_I2C1>; 998 status = "disabled"; 999 }; 1000 1001 i2c2: i2c@21a4000 { 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 1005 reg = <0x021a4000 0x4000>; 1006 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1007 clocks = <&clks IMX6SX_CLK_I2C2>; 1008 status = "disabled"; 1009 }; 1010 1011 i2c3: i2c@21a8000 { 1012 #address-cells = <1>; 1013 #size-cells = <0>; 1014 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 1015 reg = <0x021a8000 0x4000>; 1016 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1017 clocks = <&clks IMX6SX_CLK_I2C3>; 1018 status = "disabled"; 1019 }; 1020 1021 memory-controller@21b0000 { 1022 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; 1023 reg = <0x021b0000 0x4000>; 1024 clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>; 1025 }; 1026 1027 fec2: ethernet@21b4000 { 1028 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; 1029 reg = <0x021b4000 0x4000>; 1030 interrupt-names = "int0", "pps"; 1031 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1032 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1033 clocks = <&clks IMX6SX_CLK_ENET>, 1034 <&clks IMX6SX_CLK_ENET_AHB>, 1035 <&clks IMX6SX_CLK_ENET_PTP>, 1036 <&clks IMX6SX_CLK_ENET2_REF_125M>, 1037 <&clks IMX6SX_CLK_ENET_PTP>; 1038 clock-names = "ipg", "ahb", "ptp", 1039 "enet_clk_ref", "enet_out"; 1040 status = "disabled"; 1041 }; 1042 1043 weim: weim@21b8000 { 1044 #address-cells = <2>; 1045 #size-cells = <1>; 1046 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim"; 1047 reg = <0x021b8000 0x4000>; 1048 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1049 clocks = <&clks IMX6SX_CLK_EIM_SLOW>; 1050 fsl,weim-cs-gpr = <&gpr>; 1051 status = "disabled"; 1052 }; 1053 1054 ocotp: ocotp@21bc000 { 1055 #address-cells = <1>; 1056 #size-cells = <1>; 1057 compatible = "fsl,imx6sx-ocotp", "syscon"; 1058 reg = <0x021bc000 0x4000>; 1059 clocks = <&clks IMX6SX_CLK_OCOTP>; 1060 1061 tempmon_calib: calib@38 { 1062 reg = <0x38 4>; 1063 }; 1064 1065 tempmon_temp_grade: temp-grade@20 { 1066 reg = <0x20 4>; 1067 }; 1068 }; 1069 1070 sai1: sai@21d4000 { 1071 compatible = "fsl,imx6sx-sai"; 1072 reg = <0x021d4000 0x4000>; 1073 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1074 clocks = <&clks IMX6SX_CLK_SAI1_IPG>, 1075 <&clks IMX6SX_CLK_SAI1>, 1076 <&clks 0>, <&clks 0>; 1077 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1078 dma-names = "rx", "tx"; 1079 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>; 1080 status = "disabled"; 1081 }; 1082 1083 audmux: audmux@21d8000 { 1084 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux"; 1085 reg = <0x021d8000 0x4000>; 1086 status = "disabled"; 1087 }; 1088 1089 sai2: sai@21dc000 { 1090 compatible = "fsl,imx6sx-sai"; 1091 reg = <0x021dc000 0x4000>; 1092 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1093 clocks = <&clks IMX6SX_CLK_SAI2_IPG>, 1094 <&clks IMX6SX_CLK_SAI2>, 1095 <&clks 0>, <&clks 0>; 1096 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1097 dma-names = "rx", "tx"; 1098 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>; 1099 status = "disabled"; 1100 }; 1101 1102 qspi1: spi@21e0000 { 1103 #address-cells = <1>; 1104 #size-cells = <0>; 1105 compatible = "fsl,imx6sx-qspi"; 1106 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; 1107 reg-names = "QuadSPI", "QuadSPI-memory"; 1108 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1109 clocks = <&clks IMX6SX_CLK_QSPI1>, 1110 <&clks IMX6SX_CLK_QSPI1>; 1111 clock-names = "qspi_en", "qspi"; 1112 status = "disabled"; 1113 }; 1114 1115 qspi2: spi@21e4000 { 1116 #address-cells = <1>; 1117 #size-cells = <0>; 1118 compatible = "fsl,imx6sx-qspi"; 1119 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>; 1120 reg-names = "QuadSPI", "QuadSPI-memory"; 1121 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 1122 clocks = <&clks IMX6SX_CLK_QSPI2>, 1123 <&clks IMX6SX_CLK_QSPI2>; 1124 clock-names = "qspi_en", "qspi"; 1125 status = "disabled"; 1126 }; 1127 1128 uart2: serial@21e8000 { 1129 compatible = "fsl,imx6sx-uart", 1130 "fsl,imx6q-uart", "fsl,imx21-uart"; 1131 reg = <0x021e8000 0x4000>; 1132 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1133 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1134 <&clks IMX6SX_CLK_UART_SERIAL>; 1135 clock-names = "ipg", "per"; 1136 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; 1137 dma-names = "rx", "tx"; 1138 status = "disabled"; 1139 }; 1140 1141 uart3: serial@21ec000 { 1142 compatible = "fsl,imx6sx-uart", 1143 "fsl,imx6q-uart", "fsl,imx21-uart"; 1144 reg = <0x021ec000 0x4000>; 1145 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1146 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1147 <&clks IMX6SX_CLK_UART_SERIAL>; 1148 clock-names = "ipg", "per"; 1149 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; 1150 dma-names = "rx", "tx"; 1151 status = "disabled"; 1152 }; 1153 1154 uart4: serial@21f0000 { 1155 compatible = "fsl,imx6sx-uart", 1156 "fsl,imx6q-uart", "fsl,imx21-uart"; 1157 reg = <0x021f0000 0x4000>; 1158 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1159 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1160 <&clks IMX6SX_CLK_UART_SERIAL>; 1161 clock-names = "ipg", "per"; 1162 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; 1163 dma-names = "rx", "tx"; 1164 status = "disabled"; 1165 }; 1166 1167 uart5: serial@21f4000 { 1168 compatible = "fsl,imx6sx-uart", 1169 "fsl,imx6q-uart", "fsl,imx21-uart"; 1170 reg = <0x021f4000 0x4000>; 1171 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1172 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1173 <&clks IMX6SX_CLK_UART_SERIAL>; 1174 clock-names = "ipg", "per"; 1175 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; 1176 dma-names = "rx", "tx"; 1177 status = "disabled"; 1178 }; 1179 1180 i2c4: i2c@21f8000 { 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 1184 reg = <0x021f8000 0x4000>; 1185 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1186 clocks = <&clks IMX6SX_CLK_I2C4>; 1187 status = "disabled"; 1188 }; 1189 }; 1190 1191 aips3: aips-bus@2200000 { 1192 compatible = "fsl,aips-bus", "simple-bus"; 1193 #address-cells = <1>; 1194 #size-cells = <1>; 1195 reg = <0x02200000 0x100000>; 1196 ranges; 1197 1198 spba-bus@2240000 { 1199 compatible = "fsl,spba-bus", "simple-bus"; 1200 #address-cells = <1>; 1201 #size-cells = <1>; 1202 reg = <0x02240000 0x40000>; 1203 ranges; 1204 1205 csi1: csi@2214000 { 1206 reg = <0x02214000 0x4000>; 1207 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1208 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, 1209 <&clks IMX6SX_CLK_CSI>, 1210 <&clks IMX6SX_CLK_DCIC1>; 1211 clock-names = "disp-axi", "csi_mclk", "dcic"; 1212 status = "disabled"; 1213 }; 1214 1215 pxp: pxp@2218000 { 1216 compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp"; 1217 reg = <0x02218000 0x4000>; 1218 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1219 clocks = <&clks IMX6SX_CLK_PXP_AXI>; 1220 clock-names = "axi"; 1221 power-domains = <&pd_disp>; 1222 status = "disabled"; 1223 }; 1224 1225 csi2: csi@221c000 { 1226 reg = <0x0221c000 0x4000>; 1227 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1228 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, 1229 <&clks IMX6SX_CLK_CSI>, 1230 <&clks IMX6SX_CLK_DCIC2>; 1231 clock-names = "disp-axi", "csi_mclk", "dcic"; 1232 status = "disabled"; 1233 }; 1234 1235 lcdif1: lcdif@2220000 { 1236 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; 1237 reg = <0x02220000 0x4000>; 1238 interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>; 1239 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, 1240 <&clks IMX6SX_CLK_LCDIF_APB>, 1241 <&clks IMX6SX_CLK_DISPLAY_AXI>; 1242 clock-names = "pix", "axi", "disp_axi"; 1243 power-domains = <&pd_disp>; 1244 status = "disabled"; 1245 }; 1246 1247 lcdif2: lcdif@2224000 { 1248 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; 1249 reg = <0x02224000 0x4000>; 1250 interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>; 1251 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>, 1252 <&clks IMX6SX_CLK_LCDIF_APB>, 1253 <&clks IMX6SX_CLK_DISPLAY_AXI>; 1254 clock-names = "pix", "axi", "disp_axi"; 1255 power-domains = <&pd_disp>; 1256 status = "disabled"; 1257 }; 1258 1259 vadc: vadc@2228000 { 1260 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>; 1261 reg-names = "vadc-vafe", "vadc-vdec"; 1262 clocks = <&clks IMX6SX_CLK_VADC>, 1263 <&clks IMX6SX_CLK_CSI>; 1264 clock-names = "vadc", "csi"; 1265 power-domains = <&pd_disp>; 1266 status = "disabled"; 1267 }; 1268 }; 1269 1270 adc1: adc@2280000 { 1271 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; 1272 reg = <0x02280000 0x4000>; 1273 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1274 clocks = <&clks IMX6SX_CLK_IPG>; 1275 clock-names = "adc"; 1276 fsl,adck-max-frequency = <30000000>, <40000000>, 1277 <20000000>; 1278 status = "disabled"; 1279 }; 1280 1281 adc2: adc@2284000 { 1282 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; 1283 reg = <0x02284000 0x4000>; 1284 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1285 clocks = <&clks IMX6SX_CLK_IPG>; 1286 clock-names = "adc"; 1287 fsl,adck-max-frequency = <30000000>, <40000000>, 1288 <20000000>; 1289 status = "disabled"; 1290 }; 1291 1292 wdog3: wdog@2288000 { 1293 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; 1294 reg = <0x02288000 0x4000>; 1295 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1296 clocks = <&clks IMX6SX_CLK_IPG>; 1297 status = "disabled"; 1298 }; 1299 1300 ecspi5: spi@228c000 { 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 1304 reg = <0x0228c000 0x4000>; 1305 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1306 clocks = <&clks IMX6SX_CLK_ECSPI5>, 1307 <&clks IMX6SX_CLK_ECSPI5>; 1308 clock-names = "ipg", "per"; 1309 status = "disabled"; 1310 }; 1311 1312 uart6: serial@22a0000 { 1313 compatible = "fsl,imx6sx-uart", 1314 "fsl,imx6q-uart", "fsl,imx21-uart"; 1315 reg = <0x022a0000 0x4000>; 1316 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1317 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1318 <&clks IMX6SX_CLK_UART_SERIAL>; 1319 clock-names = "ipg", "per"; 1320 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>; 1321 dma-names = "rx", "tx"; 1322 status = "disabled"; 1323 }; 1324 1325 pwm5: pwm@22a4000 { 1326 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 1327 reg = <0x022a4000 0x4000>; 1328 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1329 clocks = <&clks IMX6SX_CLK_PWM5>, 1330 <&clks IMX6SX_CLK_PWM5>; 1331 clock-names = "ipg", "per"; 1332 #pwm-cells = <2>; 1333 }; 1334 1335 pwm6: pwm@22a8000 { 1336 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 1337 reg = <0x022a8000 0x4000>; 1338 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1339 clocks = <&clks IMX6SX_CLK_PWM6>, 1340 <&clks IMX6SX_CLK_PWM6>; 1341 clock-names = "ipg", "per"; 1342 #pwm-cells = <2>; 1343 }; 1344 1345 pwm7: pwm@22ac000 { 1346 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 1347 reg = <0x022ac000 0x4000>; 1348 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1349 clocks = <&clks IMX6SX_CLK_PWM7>, 1350 <&clks IMX6SX_CLK_PWM7>; 1351 clock-names = "ipg", "per"; 1352 #pwm-cells = <2>; 1353 }; 1354 1355 pwm8: pwm@22b0000 { 1356 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 1357 reg = <0x0022b0000 0x4000>; 1358 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1359 clocks = <&clks IMX6SX_CLK_PWM8>, 1360 <&clks IMX6SX_CLK_PWM8>; 1361 clock-names = "ipg", "per"; 1362 #pwm-cells = <2>; 1363 }; 1364 }; 1365 1366 pcie: pcie@8ffc000 { 1367 compatible = "fsl,imx6sx-pcie", "snps,dw-pcie"; 1368 reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>; 1369 reg-names = "dbi", "config"; 1370 #address-cells = <3>; 1371 #size-cells = <2>; 1372 device_type = "pci"; 1373 bus-range = <0x00 0xff>; 1374 ranges = <0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */ 1375 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */ 1376 num-lanes = <1>; 1377 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1378 interrupt-names = "msi"; 1379 #interrupt-cells = <1>; 1380 interrupt-map-mask = <0 0 0 0x7>; 1381 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1382 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1383 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1384 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1385 clocks = <&clks IMX6SX_CLK_PCIE_AXI>, 1386 <&clks IMX6SX_CLK_LVDS1_OUT>, 1387 <&clks IMX6SX_CLK_PCIE_REF_125M>, 1388 <&clks IMX6SX_CLK_DISPLAY_AXI>; 1389 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; 1390 power-domains = <&pd_disp>, <&pd_pci>; 1391 power-domain-names = "pcie", "pcie_phy"; 1392 status = "disabled"; 1393 }; 1394 }; 1395}; 1396