1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2014 - 2017 Xilinx, Inc. Michal Simek
4  */
5 #include <common.h>
6 #include <debug_uart.h>
7 #include <hang.h>
8 #include <image.h>
9 #include <init.h>
10 #include <log.h>
11 #include <spl.h>
12 
13 #include <asm/io.h>
14 #include <asm/spl.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/arch/ps7_init_gpl.h>
18 
board_init_f(ulong dummy)19 void board_init_f(ulong dummy)
20 {
21 	ps7_init();
22 
23 	arch_cpu_init();
24 
25 #ifdef CONFIG_DEBUG_UART
26 	/* Uart debug for sure */
27 	debug_uart_init();
28 	puts("Debug uart enabled\n"); /* or printch() */
29 #endif
30 }
31 
32 #ifdef CONFIG_SPL_BOARD_INIT
spl_board_init(void)33 void spl_board_init(void)
34 {
35 	preloader_console_init();
36 #if defined(CONFIG_ARCH_EARLY_INIT_R) && defined(CONFIG_SPL_FPGA)
37 	arch_early_init_r();
38 #endif
39 	board_init();
40 }
41 #endif
42 
spl_boot_device(void)43 u32 spl_boot_device(void)
44 {
45 	u32 mode;
46 
47 	switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
48 #ifdef CONFIG_SPL_SPI_SUPPORT
49 	case ZYNQ_BM_QSPI:
50 		mode = BOOT_DEVICE_SPI;
51 		break;
52 #endif
53 	case ZYNQ_BM_NAND:
54 		mode = BOOT_DEVICE_NAND;
55 		break;
56 	case ZYNQ_BM_NOR:
57 		mode = BOOT_DEVICE_NOR;
58 		break;
59 #ifdef CONFIG_SPL_MMC_SUPPORT
60 	case ZYNQ_BM_SD:
61 		mode = BOOT_DEVICE_MMC1;
62 		break;
63 #endif
64 	case ZYNQ_BM_JTAG:
65 		mode = BOOT_DEVICE_RAM;
66 		break;
67 	default:
68 		puts("Unsupported boot mode selected\n");
69 		hang();
70 	}
71 
72 	return mode;
73 }
74 
75 #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)76 int spl_start_uboot(void)
77 {
78 	/* boot linux */
79 	return 0;
80 }
81 #endif
82 
spl_board_prepare_for_boot(void)83 void spl_board_prepare_for_boot(void)
84 {
85 	ps7_post_config();
86 	debug("SPL bye\n");
87 }
88