1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
4 *
5 * Copyright 2007 Embedded Specialties, Inc.
6 *
7 * Copyright 2004, 2007 Freescale Semiconductor.
8 *
9 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
10 */
11
12 #include <common.h>
13 #include <init.h>
14 #include <log.h>
15 #include <net.h>
16 #include <pci.h>
17 #include <asm/processor.h>
18 #include <asm/immap_85xx.h>
19 #include <asm/fsl_pci.h>
20 #include <fsl_ddr_sdram.h>
21 #include <asm/fsl_serdes.h>
22 #include <spd_sdram.h>
23 #include <netdev.h>
24 #include <tsec.h>
25 #include <miiphy.h>
26 #include <linux/delay.h>
27 #include <linux/libfdt.h>
28 #include <fdt_support.h>
29
30 void local_bus_init(void);
31
board_early_init_f(void)32 int board_early_init_f (void)
33 {
34 return 0;
35 }
36
checkboard(void)37 int checkboard (void)
38 {
39 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
40 volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
41
42 printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
43 in_8(rev) >> 4);
44
45 /*
46 * Initialize local bus.
47 */
48 local_bus_init ();
49
50 out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
51 out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
52 return 0;
53 }
54
55 /*
56 * Initialize Local Bus
57 */
58 void
local_bus_init(void)59 local_bus_init(void)
60 {
61 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
62 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
63
64 uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR;
65 sys_info_t sysinfo;
66
67 get_sys_info(&sysinfo);
68
69 lbc_mhz = sysinfo.freq_localbus / 1000000;
70 clkdiv = sysinfo.freq_systembus / sysinfo.freq_localbus;
71
72 debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz);
73
74 out_be32(&gur->lbiuiplldcr1, 0x00078080);
75 if (clkdiv == 16) {
76 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
77 } else if (clkdiv == 8) {
78 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
79 } else if (clkdiv == 4) {
80 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
81 }
82
83 /*
84 * Local Bus Clock > 83.3 MHz. According to timing
85 * specifications set LCRR[EADC] to 2 delay cycles.
86 */
87 if (lbc_mhz > 83) {
88 lcrr &= ~LCRR_EADC;
89 lcrr |= LCRR_EADC_2;
90 }
91
92 /*
93 * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
94 * disable PLL bypass for Local Bus Clock > 83 MHz.
95 */
96 if (lbc_mhz >= 66)
97 lcrr &= (~LCRR_DBYP); /* DLL Enabled */
98
99 else
100 lcrr |= LCRR_DBYP; /* DLL Bypass */
101
102 out_be32(&lbc->lcrr, lcrr);
103 asm("sync;isync;msync");
104
105 /*
106 * According to MPC8548ERMAD Rev.1.3 read back LCRR
107 * and terminate with isync
108 */
109 lcrr = in_be32(&lbc->lcrr);
110 asm ("isync;");
111
112 /* let DLL stabilize */
113 udelay(500);
114
115 out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */
116 out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */
117 }
118
119 /*
120 * Initialize SDRAM memory on the Local Bus.
121 */
lbc_sdram_init(void)122 void lbc_sdram_init(void)
123 {
124 #if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
125
126 uint idx;
127 const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
128 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
129 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
130 uint *sdram_addr2 = (uint *)(CONFIG_SYS_LBC_SDRAM_BASE + size/2);
131
132 puts(" SDRAM: ");
133
134 print_size(size, "\n");
135
136 /*
137 * Setup SDRAM Base and Option Registers
138 */
139 set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
140 set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
141 set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
142 set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
143
144 out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
145 asm("msync");
146
147 out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT);
148 out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
149 asm("msync");
150
151 /*
152 * Issue PRECHARGE ALL command.
153 */
154 out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL);
155 asm("sync;msync");
156 *sdram_addr = 0xff;
157 ppcDcbf((unsigned long) sdram_addr);
158 *sdram_addr2 = 0xff;
159 ppcDcbf((unsigned long) sdram_addr2);
160 udelay(100);
161
162 /*
163 * Issue 8 AUTO REFRESH commands.
164 */
165 for (idx = 0; idx < 8; idx++) {
166 out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH);
167 asm("sync;msync");
168 *sdram_addr = 0xff;
169 ppcDcbf((unsigned long) sdram_addr);
170 *sdram_addr2 = 0xff;
171 ppcDcbf((unsigned long) sdram_addr2);
172 udelay(100);
173 }
174
175 /*
176 * Issue 8 MODE-set command.
177 */
178 out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW);
179 asm("sync;msync");
180 *sdram_addr = 0xff;
181 ppcDcbf((unsigned long) sdram_addr);
182 *sdram_addr2 = 0xff;
183 ppcDcbf((unsigned long) sdram_addr2);
184 udelay(100);
185
186 /*
187 * Issue RFEN command.
188 */
189 out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN);
190 asm("sync;msync");
191 *sdram_addr = 0xff;
192 ppcDcbf((unsigned long) sdram_addr);
193 *sdram_addr2 = 0xff;
194 ppcDcbf((unsigned long) sdram_addr2);
195 udelay(200); /* Overkill. Must wait > 200 bus cycles */
196
197 #endif /* enable SDRAM init */
198 }
199
200 #if defined(CONFIG_SYS_DRAM_TEST)
201 int
testdram(void)202 testdram(void)
203 {
204 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
205 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
206 uint *p;
207
208 printf("Testing DRAM from 0x%08x to 0x%08x\n",
209 CONFIG_SYS_MEMTEST_START,
210 CONFIG_SYS_MEMTEST_END);
211
212 printf("DRAM test phase 1:\n");
213 for (p = pstart; p < pend; p++)
214 *p = 0xaaaaaaaa;
215
216 for (p = pstart; p < pend; p++) {
217 if (*p != 0xaaaaaaaa) {
218 printf ("DRAM test fails at: %08x\n", (uint) p);
219 return 1;
220 }
221 }
222
223 printf("DRAM test phase 2:\n");
224 for (p = pstart; p < pend; p++)
225 *p = 0x55555555;
226
227 for (p = pstart; p < pend; p++) {
228 if (*p != 0x55555555) {
229 printf ("DRAM test fails at: %08x\n", (uint) p);
230 return 1;
231 }
232 }
233
234 printf("DRAM test passed.\n");
235 return 0;
236 }
237 #endif
238
239 #ifdef CONFIG_PCI1
240 static struct pci_controller pci1_hose;
241 #endif /* CONFIG_PCI1 */
242
243 #ifdef CONFIG_PCI
244 void
pci_init_board(void)245 pci_init_board(void)
246 {
247 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
248 int first_free_busno = 0;
249
250 #ifdef CONFIG_PCI1
251 struct fsl_pci_info pci_info;
252 u32 devdisr = in_be32(&gur->devdisr);
253 u32 pordevsr = in_be32(&gur->pordevsr);
254 u32 porpllsr = in_be32(&gur->porpllsr);
255
256 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
257 uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
258 uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
259 uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
260 uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
261
262 printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
263 (pci_32) ? 32 : 64,
264 (pci_speed == 33000000) ? "33" :
265 (pci_speed == 66000000) ? "66" : "unknown",
266 pci_clk_sel ? "sync" : "async",
267 pci_arb ? "arbiter" : "external-arbiter");
268
269 SET_STD_PCI_INFO(pci_info, 1);
270 set_next_law(pci_info.mem_phys,
271 law_size_bits(pci_info.mem_size), pci_info.law);
272 set_next_law(pci_info.io_phys,
273 law_size_bits(pci_info.io_size), pci_info.law);
274
275 first_free_busno = fsl_pci_init_port(&pci_info,
276 &pci1_hose, first_free_busno);
277 } else {
278 printf("PCI: disabled\n");
279 }
280
281 puts("\n");
282 #else
283 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
284 #endif
285
286 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
287
288 fsl_pcie_init_board(first_free_busno);
289 }
290 #endif
291
board_eth_init(struct bd_info * bis)292 int board_eth_init(struct bd_info *bis)
293 {
294 tsec_standard_init(bis);
295 pci_eth_init(bis);
296 return 0; /* otherwise cpu_eth_init gets run */
297 }
298
last_stage_init(void)299 int last_stage_init(void)
300 {
301 return 0;
302 }
303
304 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,struct bd_info * bd)305 int ft_board_setup(void *blob, struct bd_info *bd)
306 {
307 ft_cpu_setup(blob, bd);
308
309 #ifdef CONFIG_FSL_PCI_INIT
310 FT_FSL_PCI_SETUP;
311 #endif
312
313 return 0;
314 }
315 #endif
316