1 /*
2 * ***************************************************************************
3 * Copyright (C) 2015 Marvell International Ltd.
4 * ***************************************************************************
5 * This program is free software: you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the Free
7 * Software Foundation, either version 2 of the License, or any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 * ***************************************************************************
17 */
18 /* pcie_advk.c
19 *
20 * Ported from Linux driver - driver/pci/host/pci-aardvark.c
21 *
22 * Author: Victor Gu <xigu@marvell.com>
23 * Hezi Shahmoon <hezi.shahmoon@marvell.com>
24 *
25 */
26
27 #include <common.h>
28 #include <dm.h>
29 #include <pci.h>
30 #include <asm/io.h>
31 #include <asm-generic/gpio.h>
32 #include <dm/device_compat.h>
33 #include <linux/bitops.h>
34 #include <linux/delay.h>
35 #include <linux/ioport.h>
36
37 /* PCIe core registers */
38 #define PCIE_CORE_CMD_STATUS_REG 0x4
39 #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
40 #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
41 #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
42 #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
43 #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
44 #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
45 #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE 0x2
46 #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE_SHIFT 5
47 #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE 0x2
48 #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
49 #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
50 #define PCIE_CORE_LINK_TRAINING BIT(5)
51 #define PCIE_CORE_ERR_CAPCTL_REG 0x118
52 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
53 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
54 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK BIT(7)
55 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV BIT(8)
56
57 /* PIO registers base address and register offsets */
58 #define PIO_BASE_ADDR 0x4000
59 #define PIO_CTRL (PIO_BASE_ADDR + 0x0)
60 #define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
61 #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
62 #define PIO_STAT (PIO_BASE_ADDR + 0x4)
63 #define PIO_COMPLETION_STATUS_SHIFT 7
64 #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
65 #define PIO_COMPLETION_STATUS_OK 0
66 #define PIO_COMPLETION_STATUS_UR 1
67 #define PIO_COMPLETION_STATUS_CRS 2
68 #define PIO_COMPLETION_STATUS_CA 4
69 #define PIO_NON_POSTED_REQ BIT(10)
70 #define PIO_ERR_STATUS BIT(11)
71 #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
72 #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
73 #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
74 #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
75 #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
76 #define PIO_START (PIO_BASE_ADDR + 0x1c)
77 #define PIO_ISR (PIO_BASE_ADDR + 0x20)
78
79 /* Aardvark Control registers */
80 #define CONTROL_BASE_ADDR 0x4800
81 #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
82 #define PCIE_GEN_SEL_MSK 0x3
83 #define PCIE_GEN_SEL_SHIFT 0x0
84 #define SPEED_GEN_1 0
85 #define SPEED_GEN_2 1
86 #define SPEED_GEN_3 2
87 #define IS_RC_MSK 1
88 #define IS_RC_SHIFT 2
89 #define LANE_CNT_MSK 0x18
90 #define LANE_CNT_SHIFT 0x3
91 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
92 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
93 #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
94 #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT)
95 #define LINK_TRAINING_EN BIT(6)
96 #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
97 #define PCIE_CORE_CTRL2_RESERVED 0x7
98 #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
99 #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
100 #define PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE BIT(6)
101
102 /* PCIe window configuration */
103 #define OB_WIN_BASE_ADDR 0x4c00
104 #define OB_WIN_BLOCK_SIZE 0x20
105 #define OB_WIN_COUNT 8
106 #define OB_WIN_REG_ADDR(win, offset) (OB_WIN_BASE_ADDR + \
107 OB_WIN_BLOCK_SIZE * (win) + \
108 (offset))
109 #define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00)
110 #define OB_WIN_ENABLE BIT(0)
111 #define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04)
112 #define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08)
113 #define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c)
114 #define OB_WIN_MASK_LS(win) OB_WIN_REG_ADDR(win, 0x10)
115 #define OB_WIN_MASK_MS(win) OB_WIN_REG_ADDR(win, 0x14)
116 #define OB_WIN_ACTIONS(win) OB_WIN_REG_ADDR(win, 0x18)
117 #define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4)
118 #define OB_WIN_FUNC_NUM_MASK GENMASK(31, 24)
119 #define OB_WIN_FUNC_NUM_SHIFT 24
120 #define OB_WIN_FUNC_NUM_ENABLE BIT(23)
121 #define OB_WIN_BUS_NUM_BITS_MASK GENMASK(22, 20)
122 #define OB_WIN_BUS_NUM_BITS_SHIFT 20
123 #define OB_WIN_MSG_CODE_ENABLE BIT(22)
124 #define OB_WIN_MSG_CODE_MASK GENMASK(21, 14)
125 #define OB_WIN_MSG_CODE_SHIFT 14
126 #define OB_WIN_MSG_PAYLOAD_LEN BIT(12)
127 #define OB_WIN_ATTR_ENABLE BIT(11)
128 #define OB_WIN_ATTR_TC_MASK GENMASK(10, 8)
129 #define OB_WIN_ATTR_TC_SHIFT 8
130 #define OB_WIN_ATTR_RELAXED BIT(7)
131 #define OB_WIN_ATTR_NOSNOOP BIT(6)
132 #define OB_WIN_ATTR_POISON BIT(5)
133 #define OB_WIN_ATTR_IDO BIT(4)
134 #define OB_WIN_TYPE_MASK GENMASK(3, 0)
135 #define OB_WIN_TYPE_SHIFT 0
136 #define OB_WIN_TYPE_MEM 0x0
137 #define OB_WIN_TYPE_IO 0x4
138 #define OB_WIN_TYPE_CONFIG_TYPE0 0x8
139 #define OB_WIN_TYPE_CONFIG_TYPE1 0x9
140 #define OB_WIN_TYPE_MSG 0xc
141
142 /* LMI registers base address and register offsets */
143 #define LMI_BASE_ADDR 0x6000
144 #define CFG_REG (LMI_BASE_ADDR + 0x0)
145 #define LTSSM_SHIFT 24
146 #define LTSSM_MASK 0x3f
147 #define LTSSM_L0 0x10
148 #define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44)
149
150 /* PCIe core controller registers */
151 #define CTRL_CORE_BASE_ADDR 0x18000
152 #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
153 #define CTRL_MODE_SHIFT 0x0
154 #define CTRL_MODE_MASK 0x1
155 #define PCIE_CORE_MODE_DIRECT 0x0
156 #define PCIE_CORE_MODE_COMMAND 0x1
157
158 /* Transaction types */
159 #define PCIE_CONFIG_RD_TYPE0 0x8
160 #define PCIE_CONFIG_RD_TYPE1 0x9
161 #define PCIE_CONFIG_WR_TYPE0 0xa
162 #define PCIE_CONFIG_WR_TYPE1 0xb
163
164 /* PCI_BDF shifts 8bit, so we need extra 4bit shift */
165 #define PCIE_BDF(dev) (dev << 4)
166 #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
167 #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
168 #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
169 #define PCIE_CONF_REG(reg) ((reg) & 0xffc)
170 #define PCIE_CONF_ADDR(bus, devfn, where) \
171 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
172 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
173
174 /* PCIe Retries & Timeout definitions */
175 #define PIO_MAX_RETRIES 1500
176 #define PIO_WAIT_TIMEOUT 1000
177 #define LINK_MAX_RETRIES 10
178 #define LINK_WAIT_TIMEOUT 100000
179
180 #define CFG_RD_UR_VAL 0xFFFFFFFF
181 #define CFG_RD_CRS_VAL 0xFFFF0001
182
183 /**
184 * struct pcie_advk - Advk PCIe controller state
185 *
186 * @reg_base: The base address of the register space.
187 * @first_busno: This driver supports multiple PCIe controllers.
188 * first_busno stores the bus number of the PCIe root-port
189 * number which may vary depending on the PCIe setup
190 * (PEX switches etc).
191 * @device: The pointer to PCI uclass device.
192 */
193 struct pcie_advk {
194 void *base;
195 int first_busno;
196 struct udevice *dev;
197 struct gpio_desc reset_gpio;
198 };
199
advk_writel(struct pcie_advk * pcie,uint val,uint reg)200 static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg)
201 {
202 writel(val, pcie->base + reg);
203 }
204
advk_readl(struct pcie_advk * pcie,uint reg)205 static inline uint advk_readl(struct pcie_advk *pcie, uint reg)
206 {
207 return readl(pcie->base + reg);
208 }
209
210 /**
211 * pcie_advk_addr_valid() - Check for valid bus address
212 *
213 * @bdf: The PCI device to access
214 * @first_busno: Bus number of the PCIe controller root complex
215 *
216 * Return: 1 on valid, 0 on invalid
217 */
pcie_advk_addr_valid(pci_dev_t bdf,int first_busno)218 static int pcie_advk_addr_valid(pci_dev_t bdf, int first_busno)
219 {
220 /*
221 * In PCIE-E only a single device (0) can exist
222 * on the local bus. Beyound the local bus, there might be
223 * a Switch and everything is possible.
224 */
225 if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))
226 return 0;
227
228 return 1;
229 }
230
231 /**
232 * pcie_advk_wait_pio() - Wait for PIO access to be accomplished
233 *
234 * @pcie: The PCI device to access
235 *
236 * Wait up to 1.5 seconds for PIO access to be accomplished.
237 *
238 * Return 1 (true) if PIO access is accomplished.
239 * Return 0 (false) if PIO access is timed out.
240 */
pcie_advk_wait_pio(struct pcie_advk * pcie)241 static int pcie_advk_wait_pio(struct pcie_advk *pcie)
242 {
243 uint start, isr;
244 uint count;
245
246 for (count = 0; count < PIO_MAX_RETRIES; count++) {
247 start = advk_readl(pcie, PIO_START);
248 isr = advk_readl(pcie, PIO_ISR);
249 if (!start && isr)
250 return 1;
251 /*
252 * Do not check the PIO state too frequently,
253 * 100us delay is appropriate.
254 */
255 udelay(PIO_WAIT_TIMEOUT);
256 }
257
258 dev_err(pcie->dev, "PIO read/write transfer time out\n");
259 return 0;
260 }
261
262 /**
263 * pcie_advk_check_pio_status() - Validate PIO status and get the read result
264 *
265 * @pcie: Pointer to the PCI bus
266 * @read: Read from or write to configuration space - true(read) false(write)
267 * @read_val: Pointer to the read result, only valid when read is true
268 *
269 */
pcie_advk_check_pio_status(struct pcie_advk * pcie,bool read,uint * read_val)270 static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
271 bool read,
272 uint *read_val)
273 {
274 uint reg;
275 unsigned int status;
276 char *strcomp_status, *str_posted;
277
278 reg = advk_readl(pcie, PIO_STAT);
279 status = (reg & PIO_COMPLETION_STATUS_MASK) >>
280 PIO_COMPLETION_STATUS_SHIFT;
281
282 switch (status) {
283 case PIO_COMPLETION_STATUS_OK:
284 if (reg & PIO_ERR_STATUS) {
285 strcomp_status = "COMP_ERR";
286 break;
287 }
288 /* Get the read result */
289 if (read)
290 *read_val = advk_readl(pcie, PIO_RD_DATA);
291 /* No error */
292 strcomp_status = NULL;
293 break;
294 case PIO_COMPLETION_STATUS_UR:
295 if (read) {
296 /* For reading, UR is not an error status. */
297 *read_val = CFG_RD_UR_VAL;
298 strcomp_status = NULL;
299 } else {
300 strcomp_status = "UR";
301 }
302 break;
303 case PIO_COMPLETION_STATUS_CRS:
304 if (read) {
305 /* For reading, CRS is not an error status. */
306 *read_val = CFG_RD_CRS_VAL;
307 strcomp_status = NULL;
308 } else {
309 strcomp_status = "CRS";
310 }
311 break;
312 case PIO_COMPLETION_STATUS_CA:
313 strcomp_status = "CA";
314 break;
315 default:
316 strcomp_status = "Unknown";
317 break;
318 }
319
320 if (!strcomp_status)
321 return 0;
322
323 if (reg & PIO_NON_POSTED_REQ)
324 str_posted = "Non-posted";
325 else
326 str_posted = "Posted";
327
328 dev_err(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n",
329 str_posted, strcomp_status, reg,
330 advk_readl(pcie, PIO_ADDR_LS));
331
332 return -EFAULT;
333 }
334
335 /**
336 * pcie_advk_read_config() - Read from configuration space
337 *
338 * @bus: Pointer to the PCI bus
339 * @bdf: Identifies the PCIe device to access
340 * @offset: The offset into the device's configuration space
341 * @valuep: A pointer at which to store the read value
342 * @size: Indicates the size of access to perform
343 *
344 * Read a value of size @size from offset @offset within the configuration
345 * space of the device identified by the bus, device & function numbers in @bdf
346 * on the PCI bus @bus.
347 *
348 * Return: 0 on success
349 */
pcie_advk_read_config(const struct udevice * bus,pci_dev_t bdf,uint offset,ulong * valuep,enum pci_size_t size)350 static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
351 uint offset, ulong *valuep,
352 enum pci_size_t size)
353 {
354 struct pcie_advk *pcie = dev_get_priv(bus);
355 uint reg;
356 int ret;
357
358 dev_dbg(pcie->dev, "PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
359 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
360
361 if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
362 dev_dbg(pcie->dev, "- out of range\n");
363 *valuep = pci_get_ff(size);
364 return 0;
365 }
366
367 if (advk_readl(pcie, PIO_START)) {
368 dev_err(pcie->dev,
369 "Previous PIO read/write transfer is still running\n");
370 if (offset != PCI_VENDOR_ID)
371 return -EINVAL;
372 *valuep = CFG_RD_CRS_VAL;
373 return 0;
374 }
375
376 /* Program the control register */
377 reg = advk_readl(pcie, PIO_CTRL);
378 reg &= ~PIO_CTRL_TYPE_MASK;
379 if (PCI_BUS(bdf) == pcie->first_busno)
380 reg |= PCIE_CONFIG_RD_TYPE0;
381 else
382 reg |= PCIE_CONFIG_RD_TYPE1;
383 advk_writel(pcie, reg, PIO_CTRL);
384
385 /* Program the address registers */
386 reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
387 advk_writel(pcie, reg, PIO_ADDR_LS);
388 advk_writel(pcie, 0, PIO_ADDR_MS);
389
390 /* Start the transfer */
391 advk_writel(pcie, 1, PIO_ISR);
392 advk_writel(pcie, 1, PIO_START);
393
394 if (!pcie_advk_wait_pio(pcie)) {
395 if (offset != PCI_VENDOR_ID)
396 return -EINVAL;
397 *valuep = CFG_RD_CRS_VAL;
398 return 0;
399 }
400
401 /* Check PIO status and get the read result */
402 ret = pcie_advk_check_pio_status(pcie, true, ®);
403 if (ret)
404 return ret;
405
406 dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08x)\n",
407 offset, size, reg);
408 *valuep = pci_conv_32_to_size(reg, offset, size);
409
410 return 0;
411 }
412
413 /**
414 * pcie_calc_datastrobe() - Calculate data strobe
415 *
416 * @offset: The offset into the device's configuration space
417 * @size: Indicates the size of access to perform
418 *
419 * Calculate data strobe according to offset and size
420 *
421 */
pcie_calc_datastrobe(uint offset,enum pci_size_t size)422 static uint pcie_calc_datastrobe(uint offset, enum pci_size_t size)
423 {
424 uint bytes, data_strobe;
425
426 switch (size) {
427 case PCI_SIZE_8:
428 bytes = 1;
429 break;
430 case PCI_SIZE_16:
431 bytes = 2;
432 break;
433 default:
434 bytes = 4;
435 }
436
437 data_strobe = GENMASK(bytes - 1, 0) << (offset & 0x3);
438
439 return data_strobe;
440 }
441
442 /**
443 * pcie_advk_write_config() - Write to configuration space
444 *
445 * @bus: Pointer to the PCI bus
446 * @bdf: Identifies the PCIe device to access
447 * @offset: The offset into the device's configuration space
448 * @value: The value to write
449 * @size: Indicates the size of access to perform
450 *
451 * Write the value @value of size @size from offset @offset within the
452 * configuration space of the device identified by the bus, device & function
453 * numbers in @bdf on the PCI bus @bus.
454 *
455 * Return: 0 on success
456 */
pcie_advk_write_config(struct udevice * bus,pci_dev_t bdf,uint offset,ulong value,enum pci_size_t size)457 static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
458 uint offset, ulong value,
459 enum pci_size_t size)
460 {
461 struct pcie_advk *pcie = dev_get_priv(bus);
462 uint reg;
463
464 dev_dbg(pcie->dev, "PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
465 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
466 dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08lx)\n",
467 offset, size, value);
468
469 if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
470 dev_dbg(pcie->dev, "- out of range\n");
471 return 0;
472 }
473
474 if (advk_readl(pcie, PIO_START)) {
475 dev_err(pcie->dev,
476 "Previous PIO read/write transfer is still running\n");
477 return -EINVAL;
478 }
479
480 /* Program the control register */
481 reg = advk_readl(pcie, PIO_CTRL);
482 reg &= ~PIO_CTRL_TYPE_MASK;
483 if (PCI_BUS(bdf) == pcie->first_busno)
484 reg |= PCIE_CONFIG_WR_TYPE0;
485 else
486 reg |= PCIE_CONFIG_WR_TYPE1;
487 advk_writel(pcie, reg, PIO_CTRL);
488
489 /* Program the address registers */
490 reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
491 advk_writel(pcie, reg, PIO_ADDR_LS);
492 advk_writel(pcie, 0, PIO_ADDR_MS);
493 dev_dbg(pcie->dev, "\tPIO req. - addr = 0x%08x\n", reg);
494
495 /* Program the data register */
496 reg = pci_conv_size_to_32(0, value, offset, size);
497 advk_writel(pcie, reg, PIO_WR_DATA);
498 dev_dbg(pcie->dev, "\tPIO req. - val = 0x%08x\n", reg);
499
500 /* Program the data strobe */
501 reg = pcie_calc_datastrobe(offset, size);
502 advk_writel(pcie, reg, PIO_WR_DATA_STRB);
503 dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg);
504
505 /* Start the transfer */
506 advk_writel(pcie, 1, PIO_ISR);
507 advk_writel(pcie, 1, PIO_START);
508
509 if (!pcie_advk_wait_pio(pcie)) {
510 return -EINVAL;
511 }
512
513 /* Check PIO status */
514 pcie_advk_check_pio_status(pcie, false, ®);
515
516 return 0;
517 }
518
519 /**
520 * pcie_advk_link_up() - Check if PCIe link is up or not
521 *
522 * @pcie: The PCI device to access
523 *
524 * Return 1 (true) on link up.
525 * Return 0 (false) on link down.
526 */
pcie_advk_link_up(struct pcie_advk * pcie)527 static int pcie_advk_link_up(struct pcie_advk *pcie)
528 {
529 u32 val, ltssm_state;
530
531 val = advk_readl(pcie, CFG_REG);
532 ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
533 return ltssm_state >= LTSSM_L0;
534 }
535
536 /**
537 * pcie_advk_wait_for_link() - Wait for link training to be accomplished
538 *
539 * @pcie: The PCI device to access
540 *
541 * Wait up to 1 second for link training to be accomplished.
542 *
543 * Return 1 (true) if link training ends up with link up success.
544 * Return 0 (false) if link training ends up with link up failure.
545 */
pcie_advk_wait_for_link(struct pcie_advk * pcie)546 static int pcie_advk_wait_for_link(struct pcie_advk *pcie)
547 {
548 int retries;
549
550 /* check if the link is up or not */
551 for (retries = 0; retries < LINK_MAX_RETRIES; retries++) {
552 if (pcie_advk_link_up(pcie)) {
553 printf("PCIE-%d: Link up\n", pcie->first_busno);
554 return 0;
555 }
556
557 udelay(LINK_WAIT_TIMEOUT);
558 }
559
560 printf("PCIE-%d: Link down\n", pcie->first_busno);
561
562 return -ETIMEDOUT;
563 }
564
565 /*
566 * Set PCIe address window register which could be used for memory
567 * mapping.
568 */
pcie_advk_set_ob_win(struct pcie_advk * pcie,u8 win_num,phys_addr_t match,phys_addr_t remap,phys_addr_t mask,u32 actions)569 static void pcie_advk_set_ob_win(struct pcie_advk *pcie, u8 win_num,
570 phys_addr_t match, phys_addr_t remap,
571 phys_addr_t mask, u32 actions)
572 {
573 advk_writel(pcie, OB_WIN_ENABLE |
574 lower_32_bits(match), OB_WIN_MATCH_LS(win_num));
575 advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num));
576 advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num));
577 advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num));
578 advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num));
579 advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num));
580 advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num));
581 }
582
pcie_advk_disable_ob_win(struct pcie_advk * pcie,u8 win_num)583 static void pcie_advk_disable_ob_win(struct pcie_advk *pcie, u8 win_num)
584 {
585 advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num));
586 advk_writel(pcie, 0, OB_WIN_MATCH_MS(win_num));
587 advk_writel(pcie, 0, OB_WIN_REMAP_LS(win_num));
588 advk_writel(pcie, 0, OB_WIN_REMAP_MS(win_num));
589 advk_writel(pcie, 0, OB_WIN_MASK_LS(win_num));
590 advk_writel(pcie, 0, OB_WIN_MASK_MS(win_num));
591 advk_writel(pcie, 0, OB_WIN_ACTIONS(win_num));
592 }
593
pcie_advk_set_ob_region(struct pcie_advk * pcie,int * wins,struct pci_region * region,u32 actions)594 static void pcie_advk_set_ob_region(struct pcie_advk *pcie, int *wins,
595 struct pci_region *region, u32 actions)
596 {
597 phys_addr_t phys_start = region->phys_start;
598 pci_addr_t bus_start = region->bus_start;
599 pci_size_t size = region->size;
600 phys_addr_t win_mask;
601 u64 win_size;
602
603 if (*wins == -1)
604 return;
605
606 /*
607 * The n-th PCIe window is configured by tuple (match, remap, mask)
608 * and an access to address A uses this window it if A matches the
609 * match with given mask.
610 * So every PCIe window size must be a power of two and every start
611 * address must be aligned to window size. Minimal size is 64 KiB
612 * because lower 16 bits of mask must be zero.
613 */
614 while (*wins < OB_WIN_COUNT && size > 0) {
615 /* Calculate the largest aligned window size */
616 win_size = (1ULL << (fls64(size) - 1)) |
617 (phys_start ? (1ULL << __ffs64(phys_start)) : 0);
618 win_size = 1ULL << __ffs64(win_size);
619 if (win_size < 0x10000)
620 break;
621
622 dev_dbg(pcie->dev,
623 "Configuring PCIe window %d: [0x%llx-0x%llx] as 0x%x\n",
624 *wins, (u64)phys_start, (u64)phys_start + win_size,
625 actions);
626 win_mask = ~(win_size - 1) & ~0xffff;
627 pcie_advk_set_ob_win(pcie, *wins, phys_start, bus_start,
628 win_mask, actions);
629
630 phys_start += win_size;
631 bus_start += win_size;
632 size -= win_size;
633 (*wins)++;
634 }
635
636 if (size > 0) {
637 *wins = -1;
638 dev_err(pcie->dev,
639 "Invalid PCIe region [0x%llx-0x%llx]\n",
640 (u64)region->phys_start,
641 (u64)region->phys_start + region->size);
642 }
643 }
644
645 /**
646 * pcie_advk_setup_hw() - PCIe initailzation
647 *
648 * @pcie: The PCI device to access
649 *
650 * Return: 0 on success
651 */
pcie_advk_setup_hw(struct pcie_advk * pcie)652 static int pcie_advk_setup_hw(struct pcie_advk *pcie)
653 {
654 struct pci_region *io, *mem, *pref;
655 int i, wins;
656 u32 reg;
657
658 /* Set to Direct mode */
659 reg = advk_readl(pcie, CTRL_CONFIG_REG);
660 reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
661 reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
662 advk_writel(pcie, reg, CTRL_CONFIG_REG);
663
664 /* Set PCI global control register to RC mode */
665 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
666 reg |= (IS_RC_MSK << IS_RC_SHIFT);
667 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
668
669 /*
670 * Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab.
671 * VENDOR_ID_REG contains vendor id in low 16 bits and subsystem vendor
672 * id in high 16 bits. Updating this register changes readback value of
673 * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround
674 * for erratum 4.1: "The value of device and vendor ID is incorrect".
675 */
676 advk_writel(pcie, 0x11ab11ab, VENDOR_ID_REG);
677
678 /* Set Advanced Error Capabilities and Control PF0 register */
679 reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
680 PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
681 PCIE_CORE_ERR_CAPCTL_ECRC_CHECK |
682 PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV;
683 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
684
685 /* Set PCIe Device Control and Status 1 PF0 register */
686 reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
687 (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE <<
688 PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SIZE_SHIFT) |
689 (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE <<
690 PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT) |
691 PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE;
692 advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
693
694 /* Program PCIe Control 2 to disable strict ordering */
695 reg = PCIE_CORE_CTRL2_RESERVED |
696 PCIE_CORE_CTRL2_TD_ENABLE;
697 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
698
699 /* Set GEN2 */
700 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
701 reg &= ~PCIE_GEN_SEL_MSK;
702 reg |= SPEED_GEN_2;
703 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
704
705 /* Set lane X1 */
706 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
707 reg &= ~LANE_CNT_MSK;
708 reg |= LANE_COUNT_1;
709 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
710
711 /* Enable link training */
712 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
713 reg |= LINK_TRAINING_EN;
714 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
715
716 /*
717 * Enable AXI address window location generation:
718 * When it is enabled, the default outbound window
719 * configurations (Default User Field: 0xD0074CFC)
720 * are used to transparent address translation for
721 * the outbound transactions. Thus, PCIe address
722 * windows are not required for transparent memory
723 * access when default outbound window configuration
724 * is set for memory access.
725 */
726 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
727 reg |= PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE;
728 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
729
730 /*
731 * Bypass the address window mapping for PIO:
732 * Since PIO access already contains all required
733 * info over AXI interface by PIO registers, the
734 * address window is not required.
735 */
736 reg = advk_readl(pcie, PIO_CTRL);
737 reg |= PIO_CTRL_ADDR_WIN_DISABLE;
738 advk_writel(pcie, reg, PIO_CTRL);
739
740 /*
741 * Set memory access in Default User Field so it
742 * is not required to configure PCIe address for
743 * transparent memory access.
744 */
745 advk_writel(pcie, OB_WIN_TYPE_MEM, OB_WIN_DEFAULT_ACTIONS);
746
747 /*
748 * Configure PCIe address windows for non-memory or
749 * non-transparent access as by default PCIe uses
750 * transparent memory access.
751 */
752 wins = 0;
753 pci_get_regions(pcie->dev, &io, &mem, &pref);
754 if (io)
755 pcie_advk_set_ob_region(pcie, &wins, io, OB_WIN_TYPE_IO);
756 if (mem && mem->phys_start != mem->bus_start)
757 pcie_advk_set_ob_region(pcie, &wins, mem, OB_WIN_TYPE_MEM);
758 if (pref && pref->phys_start != pref->bus_start)
759 pcie_advk_set_ob_region(pcie, &wins, pref, OB_WIN_TYPE_MEM);
760
761 /* Disable remaining PCIe outbound windows */
762 for (i = ((wins >= 0) ? wins : 0); i < OB_WIN_COUNT; i++)
763 pcie_advk_disable_ob_win(pcie, i);
764
765 if (wins == -1)
766 return -EINVAL;
767
768 /* Wait for PCIe link up */
769 if (pcie_advk_wait_for_link(pcie))
770 return -ENXIO;
771
772 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
773 reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
774 PCIE_CORE_CMD_IO_ACCESS_EN |
775 PCIE_CORE_CMD_MEM_IO_REQ_EN;
776 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
777
778 return 0;
779 }
780
781 /**
782 * pcie_advk_probe() - Probe the PCIe bus for active link
783 *
784 * @dev: A pointer to the device being operated on
785 *
786 * Probe for an active link on the PCIe bus and configure the controller
787 * to enable this port.
788 *
789 * Return: 0 on success, else -ENODEV
790 */
pcie_advk_probe(struct udevice * dev)791 static int pcie_advk_probe(struct udevice *dev)
792 {
793 struct pcie_advk *pcie = dev_get_priv(dev);
794
795 gpio_request_by_name(dev, "reset-gpios", 0, &pcie->reset_gpio,
796 GPIOD_IS_OUT);
797 /*
798 * Issue reset to add-in card through the dedicated GPIO.
799 * Some boards are connecting the card reset pin to common system
800 * reset wire and others are using separate GPIO port.
801 * In the last case we have to release a reset of the addon card
802 * using this GPIO.
803 *
804 * FIX-ME:
805 * The PCIe RESET signal is not supposed to be released along
806 * with the SOC RESET signal. It should be lowered as early as
807 * possible before PCIe PHY initialization. Moreover, the PCIe
808 * clock should be gated as well.
809 */
810 if (dm_gpio_is_valid(&pcie->reset_gpio)) {
811 dev_dbg(dev, "Toggle PCIE Reset GPIO ...\n");
812 dm_gpio_set_value(&pcie->reset_gpio, 1);
813 mdelay(200);
814 dm_gpio_set_value(&pcie->reset_gpio, 0);
815 } else {
816 dev_warn(dev, "PCIE Reset on GPIO support is missing\n");
817 }
818
819 pcie->first_busno = dev_seq(dev);
820 pcie->dev = pci_get_controller(dev);
821
822 return pcie_advk_setup_hw(pcie);
823 }
824
pcie_advk_remove(struct udevice * dev)825 static int pcie_advk_remove(struct udevice *dev)
826 {
827 struct pcie_advk *pcie = dev_get_priv(dev);
828 u32 reg;
829 int i;
830
831 for (i = 0; i < OB_WIN_COUNT; i++)
832 pcie_advk_disable_ob_win(pcie, i);
833
834 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
835 reg &= ~(PCIE_CORE_CMD_MEM_ACCESS_EN |
836 PCIE_CORE_CMD_IO_ACCESS_EN |
837 PCIE_CORE_CMD_MEM_IO_REQ_EN);
838 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
839
840 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
841 reg &= ~LINK_TRAINING_EN;
842 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
843
844 return 0;
845 }
846
847 /**
848 * pcie_advk_of_to_plat() - Translate from DT to device state
849 *
850 * @dev: A pointer to the device being operated on
851 *
852 * Translate relevant data from the device tree pertaining to device @dev into
853 * state that the driver will later make use of. This state is stored in the
854 * device's private data structure.
855 *
856 * Return: 0 on success, else -EINVAL
857 */
pcie_advk_of_to_plat(struct udevice * dev)858 static int pcie_advk_of_to_plat(struct udevice *dev)
859 {
860 struct pcie_advk *pcie = dev_get_priv(dev);
861
862 /* Get the register base address */
863 pcie->base = (void *)dev_read_addr_index(dev, 0);
864 if ((fdt_addr_t)pcie->base == FDT_ADDR_T_NONE)
865 return -EINVAL;
866
867 return 0;
868 }
869
870 static const struct dm_pci_ops pcie_advk_ops = {
871 .read_config = pcie_advk_read_config,
872 .write_config = pcie_advk_write_config,
873 };
874
875 static const struct udevice_id pcie_advk_ids[] = {
876 { .compatible = "marvell,armada-3700-pcie" },
877 { }
878 };
879
880 U_BOOT_DRIVER(pcie_advk) = {
881 .name = "pcie_advk",
882 .id = UCLASS_PCI,
883 .of_match = pcie_advk_ids,
884 .ops = &pcie_advk_ops,
885 .of_to_plat = pcie_advk_of_to_plat,
886 .probe = pcie_advk_probe,
887 .remove = pcie_advk_remove,
888 .flags = DM_FLAG_OS_PREPARE,
889 .priv_auto = sizeof(struct pcie_advk),
890 };
891