1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2007,2009 Wind River Systems <www.windriver.com> 4 * Copyright 2007 Embedded Specialties, Inc. 5 * Copyright 2004, 2007 Freescale Semiconductor. 6 */ 7 8 /* 9 * sbc8548 board configuration file 10 * Please refer to board/sbc8548/README for more info. 11 */ 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 #include <linux/stringify.h> 16 17 /* 18 * Top level Makefile configuration choices 19 */ 20 #ifdef CONFIG_PCI 21 #define CONFIG_PCI_INDIRECT_BRIDGE 22 #define CONFIG_PCI1 23 #endif 24 25 #ifdef CONFIG_66 26 #define CONFIG_SYS_CLK_DIV 1 27 #endif 28 29 #ifdef CONFIG_33 30 #define CONFIG_SYS_CLK_DIV 2 31 #endif 32 33 #ifdef CONFIG_PCIE 34 #define CONFIG_PCIE1 35 #endif 36 37 /* 38 * High Level Configuration Options 39 */ 40 41 /* 42 * If you want to boot from the SODIMM flash, instead of the soldered 43 * on flash, set this, and change JP12, SW2:8 accordingly. 44 */ 45 #undef CONFIG_SYS_ALT_BOOT 46 47 #undef CONFIG_RIO 48 49 #ifdef CONFIG_PCI 50 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 51 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 52 #endif 53 54 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 55 56 /* 57 * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4] 58 */ 59 #ifndef CONFIG_SYS_CLK_DIV 60 #define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */ 61 #endif 62 #define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV) 63 64 /* 65 * These can be toggled for performance analysis, otherwise use default. 66 */ 67 #define CONFIG_L2_CACHE /* toggle L2 cache */ 68 #define CONFIG_BTB /* toggle branch predition */ 69 70 /* 71 * Only possible on E500 Version 2 or newer cores. 72 */ 73 #define CONFIG_ENABLE_36BIT_PHYS 1 74 75 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 76 77 #define CONFIG_SYS_CCSRBAR 0xe0000000 78 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 79 80 /* DDR Setup */ 81 #undef CONFIG_DDR_ECC /* only for ECC DDR module */ 82 /* 83 * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD 84 * to collide, meaning you couldn't reliably read either. So 85 * physically remove the LBC PC100 SDRAM module from the board 86 * before enabling the two SPD options below, or check that you 87 * have the hardware fix on your board via "i2c probe" and looking 88 * for a device at 0x53. 89 */ 90 #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 91 #undef CONFIG_DDR_SPD 92 93 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 94 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 95 96 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 97 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 98 #define CONFIG_VERY_BIG_RAM 99 100 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 101 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 102 103 /* 104 * The hardware fix for the I2C address collision puts the DDR 105 * SPD at 0x53, but if we are running on an older board w/o the 106 * fix, it will still be at 0x51. We check 0x53 1st. 107 */ 108 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 109 #define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */ 110 111 /* 112 * Make sure required options are set 113 */ 114 #ifndef CONFIG_SPD_EEPROM 115 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 116 #define CONFIG_SYS_DDR_CONTROL 0xc300c000 117 #endif 118 119 /* 120 * FLASH on the Local Bus 121 * Two banks, one 8MB the other 64MB, using the CFI driver. 122 * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have 123 * CS0 the 8MB boot flash, and CS6 the 64MB flash. 124 * 125 * Default: 126 * ec00_0000 efff_ffff 64MB SODIMM 127 * ff80_0000 ffff_ffff 8MB soldered flash 128 * 129 * Alternate: 130 * ef80_0000 efff_ffff 8MB soldered flash 131 * fc00_0000 ffff_ffff 64MB SODIMM 132 * 133 * BR0_8M: 134 * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 135 * Port Size = 8 bits = BRx[19:20] = 01 136 * Use GPCM = BRx[24:26] = 000 137 * Valid = BRx[31] = 1 138 * 139 * BR0_64M: 140 * Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0 141 * Port Size = 32 bits = BRx[19:20] = 11 142 * 143 * 0 4 8 12 16 20 24 28 144 * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0_8M 145 * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801 BR0_64M 146 */ 147 #define CONFIG_SYS_BR0_8M 0xff800801 148 #define CONFIG_SYS_BR0_64M 0xfc001801 149 150 /* 151 * BR6_8M: 152 * Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0 153 * Port Size = 8 bits = BRx[19:20] = 01 154 * Use GPCM = BRx[24:26] = 000 155 * Valid = BRx[31] = 1 156 157 * BR6_64M: 158 * Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0 159 * Port Size = 32 bits = BRx[19:20] = 11 160 * 161 * 0 4 8 12 16 20 24 28 162 * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801 BR6_8M 163 * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801 BR6_64M 164 */ 165 #define CONFIG_SYS_BR6_8M 0xef800801 166 #define CONFIG_SYS_BR6_64M 0xec001801 167 168 /* 169 * OR0_8M: 170 * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 171 * XAM = OR0[17:18] = 11 172 * CSNT = OR0[20] = 1 173 * ACS = half cycle delay = OR0[21:22] = 11 174 * SCY = 6 = OR0[24:27] = 0110 175 * TRLX = use relaxed timing = OR0[29] = 1 176 * EAD = use external address latch delay = OR0[31] = 1 177 * 178 * OR0_64M: 179 * Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0 180 * 181 * 182 * 0 4 8 12 16 20 24 28 183 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0_8M 184 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR0_64M 185 */ 186 #define CONFIG_SYS_OR0_8M 0xff806e65 187 #define CONFIG_SYS_OR0_64M 0xfc006e65 188 189 /* 190 * OR6_8M: 191 * Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0 192 * XAM = OR6[17:18] = 11 193 * CSNT = OR6[20] = 1 194 * ACS = half cycle delay = OR6[21:22] = 11 195 * SCY = 6 = OR6[24:27] = 0110 196 * TRLX = use relaxed timing = OR6[29] = 1 197 * EAD = use external address latch delay = OR6[31] = 1 198 * 199 * OR6_64M: 200 * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0 201 * 202 * 0 4 8 12 16 20 24 28 203 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR6_8M 204 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6_64M 205 */ 206 #define CONFIG_SYS_OR6_8M 0xff806e65 207 #define CONFIG_SYS_OR6_64M 0xfc006e65 208 209 #ifndef CONFIG_SYS_ALT_BOOT /* JP12 in default position */ 210 #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ 211 #define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */ 212 213 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M 214 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_8M 215 216 #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_64M 217 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_64M 218 #else /* JP12 in alternate position */ 219 #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* start 64MB Flash */ 220 #define CONFIG_SYS_ALT_FLASH 0xef800000 /* 8MB soldered flash */ 221 222 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M 223 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_64M 224 225 #define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_8M 226 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_8M 227 #endif 228 229 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK 230 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ 231 CONFIG_SYS_ALT_FLASH} 232 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 233 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ 234 #undef CONFIG_SYS_FLASH_CHECKSUM 235 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 236 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 237 238 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 239 240 #define CONFIG_SYS_FLASH_EMPTY_INFO 241 242 /* CS5 = Local bus peripherals controlled by the EPLD */ 243 244 #define CONFIG_SYS_BR5_PRELIM 0xf8000801 245 #define CONFIG_SYS_OR5_PRELIM 0xff006e65 246 #define CONFIG_SYS_EPLD_BASE 0xf8000000 247 #define CONFIG_SYS_LED_DISP_BASE 0xf8000000 248 #define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000 249 #define CONFIG_SYS_BD_REV 0xf8300000 250 #define CONFIG_SYS_EEPROM_BASE 0xf8b00000 251 252 /* 253 * SDRAM on the Local Bus (CS3 and CS4) 254 * Note that most boards have a hardware errata where both the 255 * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible 256 * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM. 257 * A hardware workaround is also available, see README.sbc8548 file. 258 */ 259 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 260 #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ 261 262 /* 263 * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. 264 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 265 * 266 * For BR3, need: 267 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 268 * port-size = 32-bits = BR2[19:20] = 11 269 * no parity checking = BR2[21:22] = 00 270 * SDRAM for MSEL = BR2[24:26] = 011 271 * Valid = BR[31] = 1 272 * 273 * 0 4 8 12 16 20 24 28 274 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 275 * 276 */ 277 278 #define CONFIG_SYS_BR3_PRELIM 0xf0001861 279 280 /* 281 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 282 * 283 * For OR3, need: 284 * 64MB mask for AM, OR3[0:7] = 1111 1100 285 * XAM, OR3[17:18] = 11 286 * 10 columns OR3[19-21] = 011 287 * 12 rows OR3[23-25] = 011 288 * EAD set for extra time OR[31] = 0 289 * 290 * 0 4 8 12 16 20 24 28 291 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 292 */ 293 294 #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 295 296 /* 297 * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM. 298 * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000. 299 * 300 * For BR4, need: 301 * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0 302 * port-size = 32-bits = BR2[19:20] = 11 303 * no parity checking = BR2[21:22] = 00 304 * SDRAM for MSEL = BR2[24:26] = 011 305 * Valid = BR[31] = 1 306 * 307 * 0 4 8 12 16 20 24 28 308 * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861 309 * 310 */ 311 312 #define CONFIG_SYS_BR4_PRELIM 0xf4001861 313 314 /* 315 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 316 * 317 * For OR4, need: 318 * 64MB mask for AM, OR3[0:7] = 1111 1100 319 * XAM, OR3[17:18] = 11 320 * 10 columns OR3[19-21] = 011 321 * 12 rows OR3[23-25] = 011 322 * EAD set for extra time OR[31] = 0 323 * 324 * 0 4 8 12 16 20 24 28 325 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 326 */ 327 328 #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 329 330 #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ 331 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 332 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 333 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 334 335 /* 336 * Common settings for all Local Bus SDRAM commands. 337 */ 338 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 339 | LSDMR_BSMA1516 \ 340 | LSDMR_PRETOACT3 \ 341 | LSDMR_ACTTORW3 \ 342 | LSDMR_BUFCMD \ 343 | LSDMR_BL8 \ 344 | LSDMR_WRC2 \ 345 | LSDMR_CL3 \ 346 ) 347 348 #define CONFIG_SYS_LBC_LSDMR_PCHALL \ 349 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 350 #define CONFIG_SYS_LBC_LSDMR_ARFRSH \ 351 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 352 #define CONFIG_SYS_LBC_LSDMR_MRW \ 353 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 354 #define CONFIG_SYS_LBC_LSDMR_RFEN \ 355 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN) 356 357 #define CONFIG_SYS_INIT_RAM_LOCK 1 358 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 359 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 360 361 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ 362 363 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 364 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 365 366 /* 367 * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and 368 * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM 369 * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg 370 * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right 371 * thing for MONITOR_LEN in both cases. 372 */ 373 #define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1) 374 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 375 376 /* Serial Port */ 377 #define CONFIG_SYS_NS16550_SERIAL 378 #define CONFIG_SYS_NS16550_REG_SIZE 1 379 #define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV) 380 381 #define CONFIG_SYS_BAUDRATE_TABLE \ 382 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 383 384 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 385 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 386 387 /* 388 * I2C 389 */ 390 #define CONFIG_SYS_I2C 391 #define CONFIG_SYS_I2C_FSL 392 #define CONFIG_SYS_FSL_I2C_SPEED 400000 393 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 394 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 395 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 396 397 /* 398 * General PCI 399 * Memory space is mapped 1-1, but I/O space must start from 0. 400 */ 401 #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ 402 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 403 404 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 405 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 406 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 407 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 408 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 409 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 410 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 411 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ 412 413 #ifdef CONFIG_PCIE1 414 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 415 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 416 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 417 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 418 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 419 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 420 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 421 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 422 #endif 423 424 #ifdef CONFIG_RIO 425 /* 426 * RapidIO MMU 427 */ 428 #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000 429 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ 430 #endif 431 432 #if defined(CONFIG_PCI) 433 434 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 435 436 #endif /* CONFIG_PCI */ 437 438 #if defined(CONFIG_TSEC_ENET) 439 440 #define CONFIG_TSEC1 1 441 #define CONFIG_TSEC1_NAME "eTSEC0" 442 #define CONFIG_TSEC2 1 443 #define CONFIG_TSEC2_NAME "eTSEC1" 444 #undef CONFIG_MPC85XX_FEC 445 446 #define TSEC1_PHY_ADDR 0x19 447 #define TSEC2_PHY_ADDR 0x1a 448 449 #define TSEC1_PHYIDX 0 450 #define TSEC2_PHYIDX 0 451 452 #define TSEC1_FLAGS TSEC_GIGABIT 453 #define TSEC2_FLAGS TSEC_GIGABIT 454 455 /* Options are: eTSEC[0-3] */ 456 #define CONFIG_ETHPRIME "eTSEC0" 457 #endif /* CONFIG_TSEC_ENET */ 458 459 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 460 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 461 462 /* 463 * BOOTP options 464 */ 465 #define CONFIG_BOOTP_BOOTFILESIZE 466 467 #undef CONFIG_WATCHDOG /* watchdog disabled */ 468 469 /* 470 * Miscellaneous configurable options 471 */ 472 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 473 474 /* 475 * For booting Linux, the board info and command line data 476 * have to be in the first 8 MB of memory, since this is 477 * the maximum mapped by the Linux kernel during initialization. 478 */ 479 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 480 481 #if defined(CONFIG_CMD_KGDB) 482 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 483 #endif 484 485 /* 486 * Environment Configuration 487 */ 488 #if defined(CONFIG_TSEC_ENET) 489 #define CONFIG_HAS_ETH0 490 #define CONFIG_HAS_ETH1 491 #endif 492 493 #define CONFIG_IPADDR 192.168.0.55 494 495 #define CONFIG_HOSTNAME "sbc8548" 496 #define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx" 497 #define CONFIG_BOOTFILE "/uImage" 498 #define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */ 499 500 #define CONFIG_SERVERIP 192.168.0.2 501 #define CONFIG_GATEWAYIP 192.168.0.1 502 #define CONFIG_NETMASK 255.255.255.0 503 504 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 505 506 #define CONFIG_EXTRA_ENV_SETTINGS \ 507 "netdev=eth0\0" \ 508 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 509 "tftpflash=tftpboot $loadaddr $uboot; " \ 510 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 511 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 512 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 513 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 514 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 515 "consoledev=ttyS0\0" \ 516 "ramdiskaddr=2000000\0" \ 517 "ramdiskfile=uRamdisk\0" \ 518 "fdtaddr=1e00000\0" \ 519 "fdtfile=sbc8548.dtb\0" 520 521 #define CONFIG_NFSBOOTCOMMAND \ 522 "setenv bootargs root=/dev/nfs rw " \ 523 "nfsroot=$serverip:$rootpath " \ 524 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 525 "console=$consoledev,$baudrate $othbootargs;" \ 526 "tftp $loadaddr $bootfile;" \ 527 "tftp $fdtaddr $fdtfile;" \ 528 "bootm $loadaddr - $fdtaddr" 529 530 #define CONFIG_RAMBOOTCOMMAND \ 531 "setenv bootargs root=/dev/ram rw " \ 532 "console=$consoledev,$baudrate $othbootargs;" \ 533 "tftp $ramdiskaddr $ramdiskfile;" \ 534 "tftp $loadaddr $bootfile;" \ 535 "tftp $fdtaddr $fdtfile;" \ 536 "bootm $loadaddr $ramdiskaddr $fdtaddr" 537 538 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 539 540 #endif /* __CONFIG_H */ 541