1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2010 4 * Texas Instruments, <www.ti.com> 5 * 6 * Aneesh V <aneesh@ti.com> 7 * Sricharan R <r.sricharan@ti.com> 8 */ 9 #ifndef _CLOCKS_OMAP5_H_ 10 #define _CLOCKS_OMAP5_H_ 11 #include <asm/omap_common.h> 12 13 /* 14 * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per 15 * loop, allow for a minimum of 2 ms wait (in reality the wait will be 16 * much more than that) 17 */ 18 #define LDELAY 1000000 19 20 /* CM_DLL_CTRL */ 21 #define CM_DLL_CTRL_OVERRIDE_SHIFT 0 22 #define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) 23 #define CM_DLL_CTRL_NO_OVERRIDE 0 24 25 /* CM_CLKMODE_DPLL */ 26 #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 27 #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) 28 #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 29 #define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) 30 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 31 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) 32 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 33 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) 34 #define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 35 #define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) 36 #define CM_CLKMODE_DPLL_EN_SHIFT 0 37 #define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) 38 39 #define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 40 #define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 41 42 #define DPLL_EN_STOP 1 43 #define DPLL_EN_MN_BYPASS 4 44 #define DPLL_EN_LOW_POWER_BYPASS 5 45 #define DPLL_EN_FAST_RELOCK_BYPASS 6 46 #define DPLL_EN_LOCK 7 47 48 /* CM_IDLEST_DPLL fields */ 49 #define ST_DPLL_CLK_MASK 1 50 51 /* SGX */ 52 #define CLKSEL_GPU_HYD_GCLK_MASK (1 << 25) 53 #define CLKSEL_GPU_CORE_GCLK_MASK (1 << 24) 54 55 /* CM_CLKSEL_DPLL */ 56 #define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 57 #define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) 58 #define CM_CLKSEL_DPLL_M_SHIFT 8 59 #define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) 60 #define CM_CLKSEL_DPLL_N_SHIFT 0 61 #define CM_CLKSEL_DPLL_N_MASK 0x7F 62 #define CM_CLKSEL_DCC_EN_SHIFT 22 63 #define CM_CLKSEL_DCC_EN_MASK (1 << 22) 64 65 /* CM_SYS_CLKSEL */ 66 #define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 67 68 /* CM_CLKSEL_CORE */ 69 #define CLKSEL_CORE_SHIFT 0 70 #define CLKSEL_L3_SHIFT 4 71 #define CLKSEL_L4_SHIFT 8 72 73 #define CLKSEL_CORE_X2_DIV_1 0 74 #define CLKSEL_L3_CORE_DIV_2 1 75 #define CLKSEL_L4_L3_DIV_2 1 76 77 /* CM_ABE_PLL_REF_CLKSEL */ 78 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 79 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1 80 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 81 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 82 83 /* CM_CLKSEL_ABE_PLL_SYS */ 84 #define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_SHIFT 0 85 #define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK 1 86 #define CM_ABE_PLL_SYS_CLKSEL_SYSCLK1 0 87 #define CM_ABE_PLL_SYS_CLKSEL_SYSCLK2 1 88 89 /* CM_BYPCLK_DPLL_IVA */ 90 #define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 91 #define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 92 93 #define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1 94 95 /* CM_SHADOW_FREQ_CONFIG1 */ 96 #define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 97 #define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 98 #define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 99 100 #define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 101 #define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) 102 103 #define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 104 #define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) 105 106 /*CM_<clock_domain>__CLKCTRL */ 107 #define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 108 #define CD_CLKCTRL_CLKTRCTRL_MASK 3 109 110 #define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 111 #define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 112 #define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 113 #define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 114 115 116 /* CM_<clock_domain>_<module>_CLKCTRL */ 117 #define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 118 #define MODULE_CLKCTRL_MODULEMODE_MASK 3 119 #define MODULE_CLKCTRL_IDLEST_SHIFT 16 120 #define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) 121 122 #define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 123 #define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 124 #define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 125 126 #define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 127 #define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 128 #define MODULE_CLKCTRL_IDLEST_IDLE 2 129 #define MODULE_CLKCTRL_IDLEST_DISABLED 3 130 131 /* CM_L4PER_GPIO4_CLKCTRL */ 132 #define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) 133 134 /* CM_L3INIT_HSMMCn_CLKCTRL */ 135 #define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) 136 #define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (3 << 25) 137 138 /* CM_L3INIT_SATA_CLKCTRL */ 139 #define SATA_CLKCTRL_OPTFCLKEN_MASK (1 << 8) 140 141 /* CM_WKUP_GPTIMER1_CLKCTRL */ 142 #define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) 143 144 /* CM_CAM_ISS_CLKCTRL */ 145 #define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) 146 147 /* CM_DSS_DSS_CLKCTRL */ 148 #define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 149 150 /* CM_L3INIT_USBPHY_CLKCTRL */ 151 #define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8 152 153 /* CM_L3INIT_USB_HOST_HS_CLKCTRL */ 154 #define OPTFCLKEN_FUNC48M_CLK (1 << 15) 155 #define OPTFCLKEN_HSIC480M_P2_CLK (1 << 14) 156 #define OPTFCLKEN_HSIC480M_P1_CLK (1 << 13) 157 #define OPTFCLKEN_HSIC60M_P2_CLK (1 << 12) 158 #define OPTFCLKEN_HSIC60M_P1_CLK (1 << 11) 159 #define OPTFCLKEN_UTMI_P3_CLK (1 << 10) 160 #define OPTFCLKEN_UTMI_P2_CLK (1 << 9) 161 #define OPTFCLKEN_UTMI_P1_CLK (1 << 8) 162 #define OPTFCLKEN_HSIC480M_P3_CLK (1 << 7) 163 #define OPTFCLKEN_HSIC60M_P3_CLK (1 << 6) 164 165 /* CM_L3INIT_USB_TLL_HS_CLKCTRL */ 166 #define OPTFCLKEN_USB_CH0_CLK_ENABLE (1 << 8) 167 #define OPTFCLKEN_USB_CH1_CLK_ENABLE (1 << 9) 168 #define OPTFCLKEN_USB_CH2_CLK_ENABLE (1 << 10) 169 170 /* CM_COREAON_USB_PHY_CORE_CLKCTRL */ 171 #define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8) 172 173 /* CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL */ 174 #define L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK (1 << 8) 175 176 /* CM_L3INIT_USB_OTG_SS_CLKCTRL */ 177 #define OTG_SS_CLKCTRL_MODULEMODE_HW (1 << 0) 178 #define OPTFCLKEN_REFCLK960M (1 << 8) 179 180 /* CM_L3INIT_OCP2SCP1_CLKCTRL */ 181 #define OCP2SCP1_CLKCTRL_MODULEMODE_HW (1 << 0) 182 183 /* CM_MPU_MPU_CLKCTRL */ 184 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 185 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24) 186 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26 187 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 26) 188 189 /* CM_WKUPAON_SCRM_CLKCTRL */ 190 #define OPTFCLKEN_SCRM_PER_SHIFT 9 191 #define OPTFCLKEN_SCRM_PER_MASK (1 << 9) 192 #define OPTFCLKEN_SCRM_CORE_SHIFT 8 193 #define OPTFCLKEN_SCRM_CORE_MASK (1 << 8) 194 195 /* CM_COREAON_IO_SRCOMP_CLKCTRL */ 196 #define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8 197 #define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8) 198 199 /* PRM_RSTTIME */ 200 #define RSTTIME1_SHIFT 0 201 #define RSTTIME1_MASK (0x3ff << 0) 202 203 /* Clock frequencies */ 204 #define OMAP_SYS_CLK_IND_38_4_MHZ 6 205 206 /* PRM_VC_VAL_BYPASS */ 207 #define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 208 209 /* CTRL_CORE_SRCOMP_NORTH_SIDE */ 210 #define USB2PHY_DISCHGDET (1 << 29) 211 #define USB2PHY_AUTORESUME_EN (1 << 30) 212 213 /* SMPS */ 214 #define SMPS_I2C_SLAVE_ADDR 0x12 215 #define SMPS_REG_ADDR_12_MPU 0x23 216 #define SMPS_REG_ADDR_45_IVA 0x2B 217 #define SMPS_REG_ADDR_8_CORE 0x37 218 219 /* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */ 220 /* ES1.0 settings */ 221 #define VDD_MPU 1040 222 #define VDD_MM 1040 223 #define VDD_CORE 1040 224 225 #define VDD_MPU_LOW 890 226 #define VDD_MM_LOW 890 227 #define VDD_CORE_LOW 890 228 229 /* ES2.0 settings */ 230 #define VDD_MPU_ES2 1060 231 #define VDD_MM_ES2 1025 232 #define VDD_CORE_ES2 1040 233 234 #define VDD_MPU_ES2_HIGH 1250 235 #define VDD_MM_ES2_OD 1120 236 237 /* Efuse register offsets for OMAP5 platform */ 238 #define OMAP5_ES2_EFUSE_BASE 0x4A002000 239 #define OMAP5_ES2_PROD_REGBITS 16 240 241 /* CONTROL_STD_FUSE_OPP_VDD_CORE_3 */ 242 #define OMAP5_ES2_PROD_CORE_OPNO_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1D8) 243 244 /* CONTROL_STD_FUSE_OPP_VDD_MM_4 */ 245 #define OMAP5_ES2_PROD_MM_OPNO_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1A4) 246 /* CONTROL_STD_FUSE_OPP_VDD_MM_5 */ 247 #define OMAP5_ES2_PROD_MM_OPOD_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1A8) 248 /* CONTROL_STD_FUSE_OPP_VDD_MPU_6 */ 249 #define OMAP5_ES2_PROD_MPU_OPNO_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1C4) 250 /* CONTROL_STD_FUSE_OPP_VDD_MPU_7 */ 251 #define OMAP5_ES2_PROD_MPU_OPHI_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1C8) 252 253 /* DRA74x/75x/72x voltage settings in mv for OPP_NOM per DM */ 254 #define VDD_MPU_DRA7_NOM 1150 255 #define VDD_CORE_DRA7_NOM 1150 256 #define VDD_EVE_DRA7_NOM 1060 257 #define VDD_GPU_DRA7_NOM 1060 258 #define VDD_IVA_DRA7_NOM 1060 259 260 /* DRA74x/75x/72x voltage settings in mv for OPP_OD per DM */ 261 #define VDD_EVE_DRA7_OD 1150 262 #define VDD_GPU_DRA7_OD 1150 263 #define VDD_IVA_DRA7_OD 1150 264 265 /* DRA74x/75x/72x voltage settings in mv for OPP_HIGH per DM */ 266 #define VDD_EVE_DRA7_HIGH 1250 267 #define VDD_GPU_DRA7_HIGH 1250 268 #define VDD_IVA_DRA7_HIGH 1250 269 270 /* Efuse register offsets for DRA7xx platform */ 271 #define DRA752_EFUSE_BASE 0x4A002000 272 #define DRA752_EFUSE_REGBITS 16 273 /* STD_FUSE_OPP_VMIN_IVA_2 */ 274 #define STD_FUSE_OPP_VMIN_IVA_NOM (DRA752_EFUSE_BASE + 0x05CC) 275 /* STD_FUSE_OPP_VMIN_IVA_3 */ 276 #define STD_FUSE_OPP_VMIN_IVA_OD (DRA752_EFUSE_BASE + 0x05D0) 277 /* STD_FUSE_OPP_VMIN_IVA_4 */ 278 #define STD_FUSE_OPP_VMIN_IVA_HIGH (DRA752_EFUSE_BASE + 0x05D4) 279 /* STD_FUSE_OPP_VMIN_DSPEVE_2 */ 280 #define STD_FUSE_OPP_VMIN_DSPEVE_NOM (DRA752_EFUSE_BASE + 0x05E0) 281 /* STD_FUSE_OPP_VMIN_DSPEVE_3 */ 282 #define STD_FUSE_OPP_VMIN_DSPEVE_OD (DRA752_EFUSE_BASE + 0x05E4) 283 /* STD_FUSE_OPP_VMIN_DSPEVE_4 */ 284 #define STD_FUSE_OPP_VMIN_DSPEVE_HIGH (DRA752_EFUSE_BASE + 0x05E8) 285 /* STD_FUSE_OPP_VMIN_CORE_2 */ 286 #define STD_FUSE_OPP_VMIN_CORE_NOM (DRA752_EFUSE_BASE + 0x05F4) 287 /* STD_FUSE_OPP_VMIN_GPU_2 */ 288 #define STD_FUSE_OPP_VMIN_GPU_NOM (DRA752_EFUSE_BASE + 0x1B08) 289 /* STD_FUSE_OPP_VMIN_GPU_3 */ 290 #define STD_FUSE_OPP_VMIN_GPU_OD (DRA752_EFUSE_BASE + 0x1B0C) 291 /* STD_FUSE_OPP_VMIN_GPU_4 */ 292 #define STD_FUSE_OPP_VMIN_GPU_HIGH (DRA752_EFUSE_BASE + 0x1B10) 293 /* STD_FUSE_OPP_VMIN_MPU_2 */ 294 #define STD_FUSE_OPP_VMIN_MPU_NOM (DRA752_EFUSE_BASE + 0x1B20) 295 /* STD_FUSE_OPP_VMIN_MPU_3 */ 296 #define STD_FUSE_OPP_VMIN_MPU_OD (DRA752_EFUSE_BASE + 0x1B24) 297 /* STD_FUSE_OPP_VMIN_MPU_4 */ 298 #define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28) 299 300 #if defined(CONFIG_DRA7_MPU_OPP_HIGH) 301 #define DRA7_MPU_OPP OPP_HIGH 302 #elif defined(CONFIG_DRA7_MPU_OPP_OD) 303 #define DRA7_MPU_OPP OPP_OD 304 #else /* OPP_NOM default */ 305 #define DRA7_MPU_OPP OPP_NOM 306 #endif 307 308 /* OPP_NOM only available option for CORE */ 309 #define DRA7_CORE_OPP OPP_NOM 310 311 #if defined(CONFIG_DRA7_DSPEVE_OPP_HIGH) 312 #define DRA7_DSPEVE_OPP OPP_HIGH 313 #elif defined(CONFIG_DRA7_DSPEVE_OPP_OD) 314 #define DRA7_DSPEVE_OPP OPP_OD 315 #else /* OPP_NOM default */ 316 #define DRA7_DSPEVE_OPP OPP_NOM 317 #endif 318 319 #if defined(CONFIG_DRA7_IVA_OPP_HIGH) 320 #define DRA7_IVA_OPP OPP_HIGH 321 #elif defined(CONFIG_DRA7_IVA_OPP_OD) 322 #define DRA7_IVA_OPP OPP_OD 323 #else /* OPP_NOM default */ 324 #define DRA7_IVA_OPP OPP_NOM 325 #endif 326 327 #if defined(CONFIG_DRA7_GPU_OPP_HIGH) 328 #define DRA7_GPU_OPP OPP_HIGH 329 #elif defined(CONFIG_DRA7_GPU_OPP_OD) 330 #define DRA7_GPU_OPP OPP_OD 331 #else /* OPP_NOM default */ 332 #define DRA7_GPU_OPP OPP_NOM 333 #endif 334 335 /* Standard offset is 0.5v expressed in uv */ 336 #define PALMAS_SMPS_BASE_VOLT_UV 500000 337 338 /* Offset is 0.73V for LP873x */ 339 #define LP873X_BUCK_BASE_VOLT_UV 730000 340 341 /* Offset is 0.73V for LP87565 */ 342 #define LP87565_BUCK_BASE_VOLT_UV 730000 343 344 /* TPS659038 */ 345 #define TPS659038_I2C_SLAVE_ADDR 0x58 346 #define TPS659038_REG_ADDR_SMPS12 0x23 347 #define TPS659038_REG_ADDR_SMPS45 0x2B 348 #define TPS659038_REG_ADDR_SMPS6 0x2F 349 #define TPS659038_REG_ADDR_SMPS7 0x33 350 #define TPS659038_REG_ADDR_SMPS8 0x37 351 352 /* TPS65917 */ 353 #define TPS65917_I2C_SLAVE_ADDR 0x58 354 #define TPS65917_REG_ADDR_SMPS1 0x23 355 #define TPS65917_REG_ADDR_SMPS2 0x27 356 #define TPS65917_REG_ADDR_SMPS3 0x2F 357 #define TPS65917_REG_ADDR_SMPS4 0x33 358 359 /* LP873X */ 360 #define LP873X_I2C_SLAVE_ADDR 0x60 361 #define LP873X_REG_ADDR_BUCK0 0x6 362 #define LP873X_REG_ADDR_BUCK1 0x7 363 #define LP873X_REG_ADDR_LDO1 0xA 364 365 /* LP87565 */ 366 #define LP87565_I2C_SLAVE_ADDR 0x61 367 #define LP87565_REG_ADDR_BUCK01 0xA 368 #define LP87565_REG_ADDR_BUCK23 0xE 369 370 /* TPS */ 371 #define TPS62361_I2C_SLAVE_ADDR 0x60 372 #define TPS62361_REG_ADDR_SET0 0x0 373 #define TPS62361_REG_ADDR_SET1 0x1 374 #define TPS62361_REG_ADDR_SET2 0x2 375 #define TPS62361_REG_ADDR_SET3 0x3 376 #define TPS62361_REG_ADDR_CTRL 0x4 377 #define TPS62361_REG_ADDR_TEMP 0x5 378 #define TPS62361_REG_ADDR_RMP_CTRL 0x6 379 #define TPS62361_REG_ADDR_CHIP_ID 0x8 380 #define TPS62361_REG_ADDR_CHIP_ID_2 0x9 381 382 #define TPS62361_BASE_VOLT_MV 500 383 #define TPS62361_VSEL0_GPIO 7 384 385 /* Defines for DPLL setup */ 386 #define DPLL_LOCKED_FREQ_TOLERANCE_0 0 387 #define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500 388 #define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000 389 390 #define DPLL_NO_LOCK 0 391 #define DPLL_LOCK 1 392 393 #if defined(CONFIG_DRA7XX) 394 #define V_OSCK 20000000 /* Clock output from T2 */ 395 #else 396 #define V_OSCK 19200000 /* Clock output from T2 */ 397 #endif 398 399 #define V_SCLK V_OSCK 400 401 /* CKO buffer control */ 402 #define CKOBUFFER_CLK_ENABLE_MASK (1 << 28) 403 404 /* AUXCLKx reg fields */ 405 #define AUXCLK_ENABLE_MASK (1 << 8) 406 #define AUXCLK_SRCSELECT_SHIFT 1 407 #define AUXCLK_SRCSELECT_MASK (3 << 1) 408 #define AUXCLK_CLKDIV_SHIFT 16 409 #define AUXCLK_CLKDIV_MASK (0xF << 16) 410 411 #define AUXCLK_SRCSELECT_SYS_CLK 0 412 #define AUXCLK_SRCSELECT_CORE_DPLL 1 413 #define AUXCLK_SRCSELECT_PER_DPLL 2 414 #define AUXCLK_SRCSELECT_ALTERNATE 3 415 416 #endif /* _CLOCKS_OMAP5_H_ */ 417