1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007
4 * Sascha Hauer, Pengutronix
5 *
6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 */
8
9 #include <bootm.h>
10 #include <common.h>
11 #include <dm.h>
12 #include <init.h>
13 #include <log.h>
14 #include <net.h>
15 #include <netdev.h>
16 #include <linux/errno.h>
17 #include <asm/io.h>
18 #include <asm/arch/imx-regs.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/arch/crm_regs.h>
22 #include <asm/mach-imx/boot_mode.h>
23 #include <imx_thermal.h>
24 #include <ipu_pixfmt.h>
25 #include <thermal.h>
26 #include <sata.h>
27 #include <dm/device-internal.h>
28 #include <dm/uclass-internal.h>
29
30 #ifdef CONFIG_FSL_ESDHC_IMX
31 #include <fsl_esdhc_imx.h>
32 #endif
33
34 static u32 reset_cause = -1;
35
get_imx_reset_cause(void)36 u32 get_imx_reset_cause(void)
37 {
38 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
39
40 if (reset_cause == -1) {
41 reset_cause = readl(&src_regs->srsr);
42 /* preserve the value for U-Boot proper */
43 #if !defined(CONFIG_SPL_BUILD)
44 writel(reset_cause, &src_regs->srsr);
45 #endif
46 }
47
48 return reset_cause;
49 }
50
51 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
get_reset_cause(void)52 static char *get_reset_cause(void)
53 {
54 switch (get_imx_reset_cause()) {
55 case 0x00001:
56 case 0x00011:
57 return "POR";
58 case 0x00004:
59 return "CSU";
60 case 0x00008:
61 return "IPP USER";
62 case 0x00010:
63 #ifdef CONFIG_MX7
64 return "WDOG1";
65 #else
66 return "WDOG";
67 #endif
68 case 0x00020:
69 return "JTAG HIGH-Z";
70 case 0x00040:
71 return "JTAG SW";
72 case 0x00080:
73 return "WDOG3";
74 #ifdef CONFIG_MX7
75 case 0x00100:
76 return "WDOG4";
77 case 0x00200:
78 return "TEMPSENSE";
79 #elif defined(CONFIG_IMX8M)
80 case 0x00100:
81 return "WDOG2";
82 case 0x00200:
83 return "TEMPSENSE";
84 #else
85 case 0x00100:
86 return "TEMPSENSE";
87 case 0x10000:
88 return "WARM BOOT";
89 #endif
90 default:
91 return "unknown reset";
92 }
93 }
94 #endif
95
96 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
97
get_imx_type(u32 imxtype)98 const char *get_imx_type(u32 imxtype)
99 {
100 switch (imxtype) {
101 case MXC_CPU_IMX8MP:
102 return "8MP[8]"; /* Quad-core version of the imx8mp */
103 case MXC_CPU_IMX8MPD:
104 return "8MP Dual[3]"; /* Dual-core version of the imx8mp */
105 case MXC_CPU_IMX8MPL:
106 return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */
107 case MXC_CPU_IMX8MP6:
108 return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */
109 case MXC_CPU_IMX8MN:
110 return "8MNano Quad"; /* Quad-core version */
111 case MXC_CPU_IMX8MND:
112 return "8MNano Dual"; /* Dual-core version */
113 case MXC_CPU_IMX8MNS:
114 return "8MNano Solo"; /* Single-core version */
115 case MXC_CPU_IMX8MNL:
116 return "8MNano QuadLite"; /* Quad-core Lite version */
117 case MXC_CPU_IMX8MNDL:
118 return "8MNano DualLite"; /* Dual-core Lite version */
119 case MXC_CPU_IMX8MNSL:
120 return "8MNano SoloLite";/* Single-core Lite version of the imx8mn */
121 case MXC_CPU_IMX8MNUQ:
122 return "8MNano UltraLite Quad";/* Quad-core UltraLite version of the imx8mn */
123 case MXC_CPU_IMX8MNUD:
124 return "8MNano UltraLite Dual";/* Dual-core UltraLite version of the imx8mn */
125 case MXC_CPU_IMX8MNUS:
126 return "8MNano UltraLite Solo";/* Single-core UltraLite version of the imx8mn */
127 case MXC_CPU_IMX8MM:
128 return "8MMQ"; /* Quad-core version of the imx8mm */
129 case MXC_CPU_IMX8MML:
130 return "8MMQL"; /* Quad-core Lite version of the imx8mm */
131 case MXC_CPU_IMX8MMD:
132 return "8MMD"; /* Dual-core version of the imx8mm */
133 case MXC_CPU_IMX8MMDL:
134 return "8MMDL"; /* Dual-core Lite version of the imx8mm */
135 case MXC_CPU_IMX8MMS:
136 return "8MMS"; /* Single-core version of the imx8mm */
137 case MXC_CPU_IMX8MMSL:
138 return "8MMSL"; /* Single-core Lite version of the imx8mm */
139 case MXC_CPU_IMX8MQ:
140 return "8MQ"; /* Quad-core version of the imx8mq */
141 case MXC_CPU_IMX8MQL:
142 return "8MQLite"; /* Quad-core Lite version of the imx8mq */
143 case MXC_CPU_IMX8MD:
144 return "8MD"; /* Dual-core version of the imx8mq */
145 case MXC_CPU_MX7S:
146 return "7S"; /* Single-core version of the mx7 */
147 case MXC_CPU_MX7D:
148 return "7D"; /* Dual-core version of the mx7 */
149 case MXC_CPU_MX6QP:
150 return "6QP"; /* Quad-Plus version of the mx6 */
151 case MXC_CPU_MX6DP:
152 return "6DP"; /* Dual-Plus version of the mx6 */
153 case MXC_CPU_MX6Q:
154 return "6Q"; /* Quad-core version of the mx6 */
155 case MXC_CPU_MX6D:
156 return "6D"; /* Dual-core version of the mx6 */
157 case MXC_CPU_MX6DL:
158 return "6DL"; /* Dual Lite version of the mx6 */
159 case MXC_CPU_MX6SOLO:
160 return "6SOLO"; /* Solo version of the mx6 */
161 case MXC_CPU_MX6SL:
162 return "6SL"; /* Solo-Lite version of the mx6 */
163 case MXC_CPU_MX6SLL:
164 return "6SLL"; /* SLL version of the mx6 */
165 case MXC_CPU_MX6SX:
166 return "6SX"; /* SoloX version of the mx6 */
167 case MXC_CPU_MX6UL:
168 return "6UL"; /* Ultra-Lite version of the mx6 */
169 case MXC_CPU_MX6ULL:
170 return "6ULL"; /* ULL version of the mx6 */
171 case MXC_CPU_MX6ULZ:
172 return "6ULZ"; /* ULZ version of the mx6 */
173 case MXC_CPU_MX51:
174 return "51";
175 case MXC_CPU_MX53:
176 return "53";
177 default:
178 return "??";
179 }
180 }
181
print_cpuinfo(void)182 int print_cpuinfo(void)
183 {
184 u32 cpurev;
185 __maybe_unused u32 max_freq;
186
187 cpurev = get_cpu_rev();
188
189 #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
190 struct udevice *thermal_dev;
191 int cpu_tmp, minc, maxc, ret;
192
193 printf("CPU: Freescale i.MX%s rev%d.%d",
194 get_imx_type((cpurev & 0x1FF000) >> 12),
195 (cpurev & 0x000F0) >> 4,
196 (cpurev & 0x0000F) >> 0);
197 max_freq = get_cpu_speed_grade_hz();
198 if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
199 printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
200 } else {
201 printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
202 mxc_get_clock(MXC_ARM_CLK) / 1000000);
203 }
204 #else
205 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
206 get_imx_type((cpurev & 0x1FF000) >> 12),
207 (cpurev & 0x000F0) >> 4,
208 (cpurev & 0x0000F) >> 0,
209 mxc_get_clock(MXC_ARM_CLK) / 1000000);
210 #endif
211
212 #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
213 puts("CPU: ");
214 switch (get_cpu_temp_grade(&minc, &maxc)) {
215 case TEMP_AUTOMOTIVE:
216 puts("Automotive temperature grade ");
217 break;
218 case TEMP_INDUSTRIAL:
219 puts("Industrial temperature grade ");
220 break;
221 case TEMP_EXTCOMMERCIAL:
222 puts("Extended Commercial temperature grade ");
223 break;
224 default:
225 puts("Commercial temperature grade ");
226 break;
227 }
228 printf("(%dC to %dC)", minc, maxc);
229 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
230 if (!ret) {
231 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
232
233 if (!ret)
234 printf(" at %dC", cpu_tmp);
235 else
236 debug(" - invalid sensor data\n");
237 } else {
238 debug(" - invalid sensor device\n");
239 }
240 puts("\n");
241 #endif
242
243 printf("Reset cause: %s\n", get_reset_cause());
244 return 0;
245 }
246 #endif
247
cpu_eth_init(struct bd_info * bis)248 int cpu_eth_init(struct bd_info *bis)
249 {
250 int rc = -ENODEV;
251
252 #if defined(CONFIG_FEC_MXC)
253 rc = fecmxc_initialize(bis);
254 #endif
255
256 return rc;
257 }
258
259 #ifdef CONFIG_FSL_ESDHC_IMX
260 /*
261 * Initializes on-chip MMC controllers.
262 * to override, implement board_mmc_init()
263 */
cpu_mmc_init(struct bd_info * bis)264 int cpu_mmc_init(struct bd_info *bis)
265 {
266 return fsl_esdhc_mmc_init(bis);
267 }
268 #endif
269
270 #if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
get_ahb_clk(void)271 u32 get_ahb_clk(void)
272 {
273 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
274 u32 reg, ahb_podf;
275
276 reg = __raw_readl(&imx_ccm->cbcdr);
277 reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
278 ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
279
280 return get_periph_clk() / (ahb_podf + 1);
281 }
282 #endif
283
arch_preboot_os(void)284 void arch_preboot_os(void)
285 {
286 #if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI)
287 imx_pcie_remove();
288 #endif
289
290 #if defined(CONFIG_IMX_AHCI)
291 struct udevice *dev;
292 int rc;
293
294 rc = uclass_find_device(UCLASS_AHCI, 0, &dev);
295 if (!rc && dev) {
296 rc = device_remove(dev, DM_REMOVE_NORMAL);
297 if (rc)
298 printf("Cannot remove SATA device '%s' (err=%d)\n",
299 dev->name, rc);
300 }
301 #endif
302
303 #if defined(CONFIG_SATA)
304 if (!is_mx6sdl()) {
305 sata_remove(0);
306 #if defined(CONFIG_MX6)
307 disable_sata_clock();
308 #endif
309 }
310 #endif
311 #if defined(CONFIG_VIDEO_IPUV3)
312 /* disable video before launching O/S */
313 ipuv3_fb_shutdown();
314 #endif
315 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
316 lcdif_power_down();
317 #endif
318 }
319
320 #ifndef CONFIG_IMX8M
set_chipselect_size(int const cs_size)321 void set_chipselect_size(int const cs_size)
322 {
323 unsigned int reg;
324 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
325 reg = readl(&iomuxc_regs->gpr[1]);
326
327 switch (cs_size) {
328 case CS0_128:
329 reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
330 reg |= 0x5;
331 break;
332 case CS0_64M_CS1_64M:
333 reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
334 reg |= 0x1B;
335 break;
336 case CS0_64M_CS1_32M_CS2_32M:
337 reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
338 reg |= 0x4B;
339 break;
340 case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
341 reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
342 reg |= 0x249;
343 break;
344 default:
345 printf("Unknown chip select size: %d\n", cs_size);
346 break;
347 }
348
349 writel(reg, &iomuxc_regs->gpr[1]);
350 }
351 #endif
352
353 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
354 /*
355 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
356 * defines a 2-bit SPEED_GRADING
357 */
358 #define OCOTP_TESTER3_SPEED_SHIFT 8
359 enum cpu_speed {
360 OCOTP_TESTER3_SPEED_GRADE0,
361 OCOTP_TESTER3_SPEED_GRADE1,
362 OCOTP_TESTER3_SPEED_GRADE2,
363 OCOTP_TESTER3_SPEED_GRADE3,
364 OCOTP_TESTER3_SPEED_GRADE4,
365 };
366
get_cpu_speed_grade_hz(void)367 u32 get_cpu_speed_grade_hz(void)
368 {
369 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
370 struct fuse_bank *bank = &ocotp->bank[1];
371 struct fuse_bank1_regs *fuse =
372 (struct fuse_bank1_regs *)bank->fuse_regs;
373 uint32_t val;
374
375 val = readl(&fuse->tester3);
376 val >>= OCOTP_TESTER3_SPEED_SHIFT;
377
378 if (is_imx8mn() || is_imx8mp()) {
379 val &= 0xf;
380 return 2300000000 - val * 100000000;
381 }
382
383 if (is_imx8mm())
384 val &= 0x7;
385 else
386 val &= 0x3;
387
388 switch(val) {
389 case OCOTP_TESTER3_SPEED_GRADE0:
390 return 800000000;
391 case OCOTP_TESTER3_SPEED_GRADE1:
392 return (is_mx7() ? 500000000 : (is_imx8mq() ? 1000000000 : 1200000000));
393 case OCOTP_TESTER3_SPEED_GRADE2:
394 return (is_mx7() ? 1000000000 : (is_imx8mq() ? 1300000000 : 1600000000));
395 case OCOTP_TESTER3_SPEED_GRADE3:
396 return (is_mx7() ? 1200000000 : (is_imx8mq() ? 1500000000 : 1800000000));
397 case OCOTP_TESTER3_SPEED_GRADE4:
398 return 2000000000;
399 }
400
401 return 0;
402 }
403
404 /*
405 * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
406 * defines a 2-bit SPEED_GRADING
407 */
408 #define OCOTP_TESTER3_TEMP_SHIFT 6
409
410 /* iMX8MP uses OCOTP_TESTER3[6:5] for Market segment */
411 #define IMX8MP_OCOTP_TESTER3_TEMP_SHIFT 5
412
get_cpu_temp_grade(int * minc,int * maxc)413 u32 get_cpu_temp_grade(int *minc, int *maxc)
414 {
415 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
416 struct fuse_bank *bank = &ocotp->bank[1];
417 struct fuse_bank1_regs *fuse =
418 (struct fuse_bank1_regs *)bank->fuse_regs;
419 uint32_t val;
420
421 val = readl(&fuse->tester3);
422 if (is_imx8mp())
423 val >>= IMX8MP_OCOTP_TESTER3_TEMP_SHIFT;
424 else
425 val >>= OCOTP_TESTER3_TEMP_SHIFT;
426 val &= 0x3;
427
428 if (minc && maxc) {
429 if (val == TEMP_AUTOMOTIVE) {
430 *minc = -40;
431 *maxc = 125;
432 } else if (val == TEMP_INDUSTRIAL) {
433 *minc = -40;
434 *maxc = 105;
435 } else if (val == TEMP_EXTCOMMERCIAL) {
436 *minc = -20;
437 *maxc = 105;
438 } else {
439 *minc = 0;
440 *maxc = 95;
441 }
442 }
443 return val;
444 }
445 #endif
446
447 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM)
get_boot_device(void)448 enum boot_device get_boot_device(void)
449 {
450 struct bootrom_sw_info **p =
451 (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
452
453 enum boot_device boot_dev = SD1_BOOT;
454 u8 boot_type = (*p)->boot_dev_type;
455 u8 boot_instance = (*p)->boot_dev_instance;
456
457 switch (boot_type) {
458 case BOOT_TYPE_SD:
459 boot_dev = boot_instance + SD1_BOOT;
460 break;
461 case BOOT_TYPE_MMC:
462 boot_dev = boot_instance + MMC1_BOOT;
463 break;
464 case BOOT_TYPE_NAND:
465 boot_dev = NAND_BOOT;
466 break;
467 case BOOT_TYPE_QSPI:
468 boot_dev = QSPI_BOOT;
469 break;
470 case BOOT_TYPE_WEIM:
471 boot_dev = WEIM_NOR_BOOT;
472 break;
473 case BOOT_TYPE_SPINOR:
474 boot_dev = SPI_NOR_BOOT;
475 break;
476 case BOOT_TYPE_USB:
477 boot_dev = USB_BOOT;
478 break;
479 default:
480 #ifdef CONFIG_IMX8M
481 if (((readl(SRC_BASE_ADDR + 0x58) & 0x00007FFF) >> 12) == 0x4)
482 boot_dev = QSPI_BOOT;
483 #endif
484 break;
485 }
486
487 return boot_dev;
488 }
489 #endif
490
491 #ifdef CONFIG_NXP_BOARD_REVISION
nxp_board_rev(void)492 int nxp_board_rev(void)
493 {
494 /*
495 * Get Board ID information from OCOTP_GP1[15:8]
496 * RevA: 0x1
497 * RevB: 0x2
498 * RevC: 0x3
499 */
500 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
501 struct fuse_bank *bank = &ocotp->bank[4];
502 struct fuse_bank4_regs *fuse =
503 (struct fuse_bank4_regs *)bank->fuse_regs;
504
505 return (readl(&fuse->gp1) >> 8 & 0x0F);
506 }
507
nxp_board_rev_string(void)508 char nxp_board_rev_string(void)
509 {
510 const char *rev = "A";
511
512 return (*rev + nxp_board_rev() - 1);
513 }
514 #endif
515