1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * AM6: SoC specific initialization
4 *
5 * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
6 * Lokesh Vutla <lokeshvutla@ti.com>
7 */
8
9 #include <common.h>
10 #include <fdt_support.h>
11 #include <init.h>
12 #include <asm/global_data.h>
13 #include <asm/io.h>
14 #include <spl.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/sysfw-loader.h>
17 #include <asm/arch/sys_proto.h>
18 #include "common.h"
19 #include <dm.h>
20 #include <dm/uclass-internal.h>
21 #include <dm/pinctrl.h>
22 #include <linux/soc/ti/ti_sci_protocol.h>
23 #include <log.h>
24 #include <mmc.h>
25 #include <stdlib.h>
26
27 DECLARE_GLOBAL_DATA_PTR;
28
29 #ifdef CONFIG_SPL_BUILD
30 #ifdef CONFIG_K3_LOAD_SYSFW
31 #ifdef CONFIG_TI_SECURE_DEVICE
32 struct fwl_data main_cbass_fwls[] = {
33 { "MMCSD1_CFG", 2057, 1 },
34 { "MMCSD0_CFG", 2058, 1 },
35 { "USB3SS0_SLV0", 2176, 2 },
36 { "PCIE0_SLV", 2336, 8 },
37 { "PCIE1_SLV", 2337, 8 },
38 { "PCIE0_CFG", 2688, 1 },
39 { "PCIE1_CFG", 2689, 1 },
40 }, mcu_cbass_fwls[] = {
41 { "MCU_ARMSS0_CORE0_SLV", 1024, 1 },
42 { "MCU_ARMSS0_CORE1_SLV", 1028, 1 },
43 { "MCU_FSS0_S1", 1033, 8 },
44 { "MCU_FSS0_S0", 1036, 8 },
45 { "MCU_CPSW0", 1220, 1 },
46 };
47 #endif
48 #endif
49
ctrl_mmr_unlock(void)50 static void ctrl_mmr_unlock(void)
51 {
52 /* Unlock all WKUP_CTRL_MMR0 module registers */
53 mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
54 mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
55 mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
56 mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
57 mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
58 mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
59
60 /* Unlock all MCU_CTRL_MMR0 module registers */
61 mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
62 mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
63 mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
64 mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
65
66 /* Unlock all CTRL_MMR0 module registers */
67 mmr_unlock(CTRL_MMR0_BASE, 0);
68 mmr_unlock(CTRL_MMR0_BASE, 1);
69 mmr_unlock(CTRL_MMR0_BASE, 2);
70 mmr_unlock(CTRL_MMR0_BASE, 3);
71 mmr_unlock(CTRL_MMR0_BASE, 6);
72 mmr_unlock(CTRL_MMR0_BASE, 7);
73 }
74
75 /*
76 * This uninitialized global variable would normal end up in the .bss section,
77 * but the .bss is cleared between writing and reading this variable, so move
78 * it to the .data section.
79 */
80 u32 bootindex __section(".data");
81
store_boot_index_from_rom(void)82 static void store_boot_index_from_rom(void)
83 {
84 bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
85 }
86
87 #if defined(CONFIG_K3_LOAD_SYSFW) && CONFIG_IS_ENABLED(DM_MMC)
k3_mmc_stop_clock(void)88 void k3_mmc_stop_clock(void)
89 {
90 if (spl_boot_device() == BOOT_DEVICE_MMC1) {
91 struct mmc *mmc = find_mmc_device(0);
92
93 if (!mmc)
94 return;
95
96 mmc->saved_clock = mmc->clock;
97 mmc_set_clock(mmc, 0, true);
98 }
99 }
100
k3_mmc_restart_clock(void)101 void k3_mmc_restart_clock(void)
102 {
103 if (spl_boot_device() == BOOT_DEVICE_MMC1) {
104 struct mmc *mmc = find_mmc_device(0);
105
106 if (!mmc)
107 return;
108
109 mmc_set_clock(mmc, mmc->saved_clock, false);
110 }
111 }
112 #else
k3_mmc_stop_clock(void)113 void k3_mmc_stop_clock(void) {}
k3_mmc_restart_clock(void)114 void k3_mmc_restart_clock(void) {}
115 #endif
116 #if CONFIG_IS_ENABLED(DFU) || CONFIG_IS_ENABLED(USB_STORAGE)
117 #define CTRLMMR_SERDES0_CTRL 0x00104080
118 #define PCIE_LANE0 0x1
fixup_usb_boot(void)119 static int fixup_usb_boot(void)
120 {
121 int ret;
122
123 switch (spl_boot_device()) {
124 case BOOT_DEVICE_USB:
125 /*
126 * If bootmode is Host bootmode, fixup the dr_mode to host
127 * before the dwc3 bind takes place
128 */
129 ret = fdt_find_and_setprop((void *)gd->fdt_blob,
130 "/interconnect@100000/dwc3@4000000/usb@10000",
131 "dr_mode", "host", 11, 0);
132 if (ret)
133 printf("%s: fdt_find_and_setprop() failed:%d\n", __func__,
134 ret);
135 fallthrough;
136 case BOOT_DEVICE_DFU:
137 /*
138 * The serdes mux between PCIe and USB3 needs to be set to PCIe for
139 * accessing the interface at USB 2.0
140 */
141 writel(PCIE_LANE0, CTRLMMR_SERDES0_CTRL);
142 default:
143 break;
144 }
145
146 return 0;
147 }
148
fdtdec_board_setup(const void * fdt_blob)149 int fdtdec_board_setup(const void *fdt_blob)
150 {
151 return fixup_usb_boot();
152 }
153 #endif
board_init_f(ulong dummy)154 void board_init_f(ulong dummy)
155 {
156 #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
157 struct udevice *dev;
158 size_t pool_size;
159 void *pool_addr;
160 int ret;
161 #endif
162 /*
163 * Cannot delay this further as there is a chance that
164 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
165 */
166 store_boot_index_from_rom();
167
168 /* Make all control module registers accessible */
169 ctrl_mmr_unlock();
170
171 #ifdef CONFIG_CPU_V7R
172 disable_linefill_optimization();
173 setup_k3_mpu_regions();
174 #endif
175
176 /* Init DM early in-order to invoke system controller */
177 spl_early_init();
178
179 #ifdef CONFIG_K3_EARLY_CONS
180 /*
181 * Allow establishing an early console as required for example when
182 * doing a UART-based boot. Note that this console may not "survive"
183 * through a SYSFW PM-init step and will need a re-init in some way
184 * due to changing module clock frequencies.
185 */
186 early_console_init();
187 #endif
188
189 #ifdef CONFIG_K3_LOAD_SYSFW
190 /*
191 * Initialize an early full malloc environment. Do so by allocating a
192 * new malloc area inside the currently active pre-relocation "first"
193 * malloc pool of which we use all that's left.
194 */
195 pool_size = CONFIG_VAL(SYS_MALLOC_F_LEN) - gd->malloc_ptr;
196 pool_addr = malloc(pool_size);
197 if (!pool_addr)
198 panic("ERROR: Can't allocate full malloc pool!\n");
199
200 mem_malloc_init((ulong)pool_addr, (ulong)pool_size);
201 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
202 debug("%s: initialized an early full malloc pool at 0x%08lx of 0x%lx bytes\n",
203 __func__, (unsigned long)pool_addr, (unsigned long)pool_size);
204 /*
205 * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
206 * regardless of the result of pinctrl. Do this without probing the
207 * device, but instead by searching the device that would request the
208 * given sequence number if probed. The UART will be used by the system
209 * firmware (SYSFW) image for various purposes and SYSFW depends on us
210 * to initialize its pin settings.
211 */
212 ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
213 if (!ret)
214 pinctrl_select_state(dev, "default");
215
216 /*
217 * Load, start up, and configure system controller firmware while
218 * also populating the SYSFW post-PM configuration callback hook.
219 */
220 k3_sysfw_loader(false, k3_mmc_stop_clock, k3_mmc_restart_clock);
221
222 /* Prepare console output */
223 preloader_console_init();
224
225 /* Disable ROM configured firewalls right after loading sysfw */
226 #ifdef CONFIG_TI_SECURE_DEVICE
227 remove_fwl_configs(main_cbass_fwls, ARRAY_SIZE(main_cbass_fwls));
228 remove_fwl_configs(mcu_cbass_fwls, ARRAY_SIZE(mcu_cbass_fwls));
229 #endif
230 #else
231 /* Prepare console output */
232 preloader_console_init();
233 #endif
234
235 /* Output System Firmware version info */
236 k3_sysfw_print_ver();
237
238 /* Perform EEPROM-based board detection */
239 do_board_detect();
240
241 #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
242 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
243 &dev);
244 if (ret)
245 printf("AVS init failed: %d\n", ret);
246 #endif
247
248 #ifdef CONFIG_K3_AM654_DDRSS
249 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
250 if (ret)
251 panic("DRAM init failed: %d\n", ret);
252 #endif
253 spl_enable_dcache();
254 }
255
spl_mmc_boot_mode(const u32 boot_device)256 u32 spl_mmc_boot_mode(const u32 boot_device)
257 {
258 #if defined(CONFIG_SUPPORT_EMMC_BOOT)
259 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
260
261 u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
262 CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
263
264 /* eMMC boot0 mode is only supported for primary boot */
265 if (bootindex == K3_PRIMARY_BOOTMODE &&
266 bootmode == BOOT_DEVICE_MMC1)
267 return MMCSD_MODE_EMMCBOOT;
268 #endif
269
270 /* Everything else use filesystem if available */
271 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
272 return MMCSD_MODE_FS;
273 #else
274 return MMCSD_MODE_RAW;
275 #endif
276 }
277
__get_backup_bootmedia(u32 devstat)278 static u32 __get_backup_bootmedia(u32 devstat)
279 {
280 u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
281 CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
282
283 switch (bkup_boot) {
284 case BACKUP_BOOT_DEVICE_USB:
285 return BOOT_DEVICE_USB;
286 case BACKUP_BOOT_DEVICE_UART:
287 return BOOT_DEVICE_UART;
288 case BACKUP_BOOT_DEVICE_ETHERNET:
289 return BOOT_DEVICE_ETHERNET;
290 case BACKUP_BOOT_DEVICE_MMC2:
291 {
292 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
293 CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
294 if (port == 0x0)
295 return BOOT_DEVICE_MMC1;
296 return BOOT_DEVICE_MMC2;
297 }
298 case BACKUP_BOOT_DEVICE_SPI:
299 return BOOT_DEVICE_SPI;
300 case BACKUP_BOOT_DEVICE_HYPERFLASH:
301 return BOOT_DEVICE_HYPERFLASH;
302 case BACKUP_BOOT_DEVICE_I2C:
303 return BOOT_DEVICE_I2C;
304 };
305
306 return BOOT_DEVICE_RAM;
307 }
308
__get_primary_bootmedia(u32 devstat)309 static u32 __get_primary_bootmedia(u32 devstat)
310 {
311 u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
312 CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
313
314 if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
315 bootmode = BOOT_DEVICE_SPI;
316
317 if (bootmode == BOOT_DEVICE_MMC2) {
318 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK) >>
319 CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT;
320 if (port == 0x0)
321 bootmode = BOOT_DEVICE_MMC1;
322 } else if (bootmode == BOOT_DEVICE_MMC1) {
323 u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK) >>
324 CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
325 if (port == 0x1)
326 bootmode = BOOT_DEVICE_MMC2;
327 } else if (bootmode == BOOT_DEVICE_DFU) {
328 u32 mode = (devstat & CTRLMMR_MAIN_DEVSTAT_USB_MODE_MASK) >>
329 CTRLMMR_MAIN_DEVSTAT_USB_MODE_SHIFT;
330 if (mode == 0x2)
331 bootmode = BOOT_DEVICE_USB;
332 }
333
334 return bootmode;
335 }
336
spl_boot_device(void)337 u32 spl_boot_device(void)
338 {
339 u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
340
341 if (bootindex == K3_PRIMARY_BOOTMODE)
342 return __get_primary_bootmedia(devstat);
343 else
344 return __get_backup_bootmedia(devstat);
345 }
346 #endif
347
348 #ifdef CONFIG_SYS_K3_SPL_ATF
349
350 #define AM6_DEV_MCU_RTI0 134
351 #define AM6_DEV_MCU_RTI1 135
352 #define AM6_DEV_MCU_ARMSS0_CPU0 159
353 #define AM6_DEV_MCU_ARMSS0_CPU1 245
354
release_resources_for_core_shutdown(void)355 void release_resources_for_core_shutdown(void)
356 {
357 struct ti_sci_handle *ti_sci = get_ti_sci_handle();
358 struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
359 struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
360 int ret;
361 u32 i;
362
363 const u32 put_device_ids[] = {
364 AM6_DEV_MCU_RTI0,
365 AM6_DEV_MCU_RTI1,
366 };
367
368 /* Iterate through list of devices to put (shutdown) */
369 for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
370 u32 id = put_device_ids[i];
371
372 ret = dev_ops->put_device(ti_sci, id);
373 if (ret)
374 panic("Failed to put device %u (%d)\n", id, ret);
375 }
376
377 const u32 put_core_ids[] = {
378 AM6_DEV_MCU_ARMSS0_CPU1,
379 AM6_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
380 };
381
382 /* Iterate through list of cores to put (shutdown) */
383 for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
384 u32 id = put_core_ids[i];
385
386 /*
387 * Queue up the core shutdown request. Note that this call
388 * needs to be followed up by an actual invocation of an WFE
389 * or WFI CPU instruction.
390 */
391 ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
392 if (ret)
393 panic("Failed sending core %u shutdown message (%d)\n",
394 id, ret);
395 }
396 }
397 #endif
398