1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Toradex Colibri PXA270 Support
4 *
5 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
6 * Copyright (C) 2016-2019 Marcel Ziswiler <marcel.ziswiler@toradex.com>
7 */
8
9 #include <common.h>
10 #include <cpu_func.h>
11 #include <dm.h>
12 #include <init.h>
13 #include <net.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/pxa.h>
16 #include <asm/arch/regs-mmc.h>
17 #include <asm/arch/regs-uart.h>
18 #include <asm/global_data.h>
19 #include <asm/io.h>
20 #include <dm/platdata.h>
21 #include <dm/platform_data/pxa_mmc_gen.h>
22 #include <dm/platform_data/serial_pxa.h>
23 #include <netdev.h>
24 #include <serial.h>
25 #include <usb.h>
26 #include <asm/mach-types.h>
27 #include <linux/delay.h>
28 #include "../common/tdx-common.h"
29
30 DECLARE_GLOBAL_DATA_PTR;
31
board_init(void)32 int board_init(void)
33 {
34 /* We have RAM, disable cache */
35 dcache_disable();
36 icache_disable();
37
38 /* arch number of Toradex Colibri PXA270 */
39 gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
40
41 /* address of boot parameters */
42 gd->bd->bi_boot_params = 0xa0000100;
43
44 return 0;
45 }
46
checkboard(void)47 int checkboard(void)
48 {
49 puts("Model: Toradex Colibri PXA270\n");
50
51 return 0;
52 }
53
54 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,struct bd_info * bd)55 int ft_board_setup(void *blob, struct bd_info *bd)
56 {
57 return ft_common_board_setup(blob, bd);
58 }
59 #endif
60
dram_init(void)61 int dram_init(void)
62 {
63 pxa2xx_dram_init();
64 gd->ram_size = PHYS_SDRAM_1_SIZE;
65 return 0;
66 }
67
68 #ifdef CONFIG_CMD_USB
board_usb_init(int index,enum usb_init_type init)69 int board_usb_init(int index, enum usb_init_type init)
70 {
71 writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
72 ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
73 UHCHR);
74
75 writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
76
77 while (UHCHR & UHCHR_FSBIR)
78 ;
79
80 writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
81 writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
82
83 /* Clear any OTG Pin Hold */
84 if (readl(PSSR) & PSSR_OTGPH)
85 writel(readl(PSSR) | PSSR_OTGPH, PSSR);
86
87 writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
88 writel(readl(UHCRHDA) | 0x100, UHCRHDA);
89
90 /* Set port power control mask bits, only 3 ports. */
91 writel(readl(UHCRHDB) | (0x7 << 17), UHCRHDB);
92
93 /* enable port 2 */
94 writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
95 UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
96
97 return 0;
98 }
99
board_usb_cleanup(int index,enum usb_init_type init)100 int board_usb_cleanup(int index, enum usb_init_type init)
101 {
102 return 0;
103 }
104
usb_board_stop(void)105 void usb_board_stop(void)
106 {
107 writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
108 udelay(11);
109 writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
110
111 writel(readl(UHCCOMS) | 1, UHCCOMS);
112 udelay(10);
113
114 writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
115 }
116 #endif
117
118 #ifdef CONFIG_DRIVER_DM9000
board_eth_init(struct bd_info * bis)119 int board_eth_init(struct bd_info *bis)
120 {
121 return dm9000_initialize(bis);
122 }
123 #endif
124
125 #ifdef CONFIG_CMD_MMC
126 #if !CONFIG_IS_ENABLED(DM_MMC)
board_mmc_init(struct bd_info * bis)127 int board_mmc_init(struct bd_info *bis)
128 {
129 pxa_mmc_register(0);
130 return 0;
131 }
132 #else /* !CONFIG_IS_ENABLED(DM_MMC) */
133 static const struct pxa_mmc_plat mmc_plat = {
134 .base = (struct pxa_mmc_regs *)MMC0_BASE,
135 };
136
137 U_BOOT_DRVINFO(pxa_mmcs) = {
138 .name = "pxa_mmc",
139 .plat = &mmc_plat,
140 };
141 #endif /* !CONFIG_IS_ENABLED(DM_MMC) */
142 #endif
143
144 static const struct pxa_serial_plat serial_plat = {
145 .base = (struct pxa_uart_regs *)FFUART_BASE,
146 .port = FFUART_INDEX,
147 .baudrate = CONFIG_BAUDRATE,
148 };
149
150 U_BOOT_DRVINFO(pxa_serials) = {
151 .name = "serial_pxa",
152 .plat = &serial_plat,
153 };
154