1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MediaTek clock driver for MT7629 SoC
4 *
5 * Copyright (C) 2018 MediaTek Inc.
6 * Author: Ryder Lee <ryder.lee@mediatek.com>
7 */
8
9 #include <common.h>
10 #include <dm.h>
11 #include <log.h>
12 #include <asm/arch-mediatek/reset.h>
13 #include <asm/io.h>
14 #include <dt-bindings/clock/mt7629-clk.h>
15 #include <linux/bitops.h>
16
17 #include "clk-mtk.h"
18
19 #define MT7629_CLKSQ_STB_CON0 0x20
20 #define MT7629_PLL_ISO_CON0 0x2c
21 #define MT7629_PLL_FMAX (2500UL * MHZ)
22 #define MT7629_CON0_RST_BAR BIT(24)
23
24 #define MCU_AXI_DIV 0x640
25 #define AXI_DIV_MSK GENMASK(4, 0)
26 #define AXI_DIV_SEL(x) (x)
27
28 #define MCU_BUS_MUX 0x7c0
29 #define MCU_BUS_MSK GENMASK(10, 9)
30 #define MCU_BUS_SEL(x) ((x) << 9)
31
32 /* apmixedsys */
33 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
34 _pd_shift, _pcw_reg, _pcw_shift) { \
35 .id = _id, \
36 .reg = _reg, \
37 .pwr_reg = _pwr_reg, \
38 .en_mask = _en_mask, \
39 .rst_bar_mask = MT7629_CON0_RST_BAR, \
40 .fmax = MT7629_PLL_FMAX, \
41 .flags = _flags, \
42 .pcwbits = _pcwbits, \
43 .pd_reg = _pd_reg, \
44 .pd_shift = _pd_shift, \
45 .pcw_reg = _pcw_reg, \
46 .pcw_shift = _pcw_shift, \
47 }
48
49 static const struct mtk_pll_data apmixed_plls[] = {
50 PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0,
51 21, 0x204, 24, 0x204, 0),
52 PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR,
53 21, 0x214, 24, 0x214, 0),
54 PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR,
55 7, 0x224, 24, 0x224, 14),
56 PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0,
57 21, 0x300, 1, 0x304, 0),
58 PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0,
59 21, 0x314, 1, 0x318, 0),
60 PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0,
61 21, 0x358, 1, 0x35c, 0),
62 };
63
64 /* topckgen */
65 #define FACTOR0(_id, _parent, _mult, _div) \
66 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
67
68 #define FACTOR1(_id, _parent, _mult, _div) \
69 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
70
71 #define FACTOR2(_id, _parent, _mult, _div) \
72 FACTOR(_id, _parent, _mult, _div, 0)
73
74 static const struct mtk_fixed_clk top_fixed_clks[] = {
75 FIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 31250000),
76 FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 31250000),
77 FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, CLK_XTAL, 125000000),
78 FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, CLK_XTAL, 125000000),
79 FIXED_CLK(CLK_TOP_SSUSB_TX250M, CLK_XTAL, 250000000),
80 FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, CLK_XTAL, 250000000),
81 FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, CLK_XTAL, 33333333),
82 FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, CLK_XTAL, 50000000),
83 FIXED_CLK(CLK_TOP_SATA_ASIC, CLK_XTAL, 50000000),
84 FIXED_CLK(CLK_TOP_SATA_RBC, CLK_XTAL, 50000000),
85 };
86
87 static const struct mtk_fixed_factor top_fixed_divs[] = {
88 FACTOR0(CLK_TOP_TO_USB3_SYS, CLK_APMIXED_ETH1PLL, 1, 4),
89 FACTOR0(CLK_TOP_P1_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
90 FACTOR0(CLK_TOP_4MHZ, CLK_APMIXED_ETH1PLL, 1, 125),
91 FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
92 FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1),
93 FACTOR1(CLK_TOP_TXCLK_SRC_PRE, CLK_TOP_SGMIIPLL_D2, 1, 1),
94 FACTOR2(CLK_TOP_RTC, CLK_XTAL, 1, 1024),
95 FACTOR2(CLK_TOP_PWM_QTR_26M, CLK_XTAL, 1, 1),
96 FACTOR2(CLK_TOP_CPUM_TCK_IN, CLK_XTAL, 1, 1),
97 FACTOR2(CLK_TOP_TO_USB3_DA_TOP, CLK_XTAL, 1, 1),
98 FACTOR2(CLK_TOP_MEMPLL, CLK_XTAL, 32, 1),
99 FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1),
100 FACTOR1(CLK_TOP_DMPLL_D4, CLK_TOP_MEMPLL, 1, 4),
101 FACTOR1(CLK_TOP_DMPLL_D8, CLK_TOP_MEMPLL, 1, 8),
102 FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
103 FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4),
104 FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8),
105 FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16),
106 FACTOR0(CLK_TOP_SYSPLL1_D16, CLK_APMIXED_MAINPLL, 1, 32),
107 FACTOR0(CLK_TOP_SYSPLL2_D2, CLK_APMIXED_MAINPLL, 1, 6),
108 FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12),
109 FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24),
110 FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
111 FACTOR0(CLK_TOP_SYSPLL3_D2, CLK_APMIXED_MAINPLL, 1, 10),
112 FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20),
113 FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
114 FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14),
115 FACTOR0(CLK_TOP_SYSPLL4_D4, CLK_APMIXED_MAINPLL, 1, 28),
116 FACTOR0(CLK_TOP_SYSPLL4_D16, CLK_APMIXED_MAINPLL, 1, 112),
117 FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIV2PLL, 1, 2),
118 FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4),
119 FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8),
120 FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16),
121 FACTOR1(CLK_TOP_UNIVPLL_D3, CLK_TOP_UNIVPLL, 1, 3),
122 FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6),
123 FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12),
124 FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24),
125 FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL, 1, 48),
126 FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5),
127 FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10),
128 FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20),
129 FACTOR1(CLK_TOP_UNIVPLL3_D16, CLK_TOP_UNIVPLL, 1, 80),
130 FACTOR1(CLK_TOP_UNIVPLL_D7, CLK_TOP_UNIVPLL, 1, 7),
131 FACTOR1(CLK_TOP_UNIVPLL_D80_D4, CLK_TOP_UNIVPLL, 1, 320),
132 FACTOR1(CLK_TOP_UNIV48M, CLK_TOP_UNIVPLL, 1, 25),
133 FACTOR0(CLK_TOP_SGMIIPLL_D2, CLK_APMIXED_SGMIPLL, 1, 2),
134 FACTOR2(CLK_TOP_CLKXTAL_D4, CLK_XTAL, 1, 4),
135 FACTOR1(CLK_TOP_HD_FAXI, CLK_TOP_AXI_SEL, 1, 1),
136 FACTOR1(CLK_TOP_FAXI, CLK_TOP_AXI_SEL, 1, 1),
137 FACTOR1(CLK_TOP_F_FAUD_INTBUS, CLK_TOP_AUD_INTBUS_SEL, 1, 1),
138 FACTOR1(CLK_TOP_AP2WBHIF_HCLK, CLK_TOP_SYSPLL1_D8, 1, 1),
139 FACTOR1(CLK_TOP_10M_INFRAO, CLK_TOP_10M_SEL, 1, 1),
140 FACTOR1(CLK_TOP_MSDC30_1, CLK_TOP_MSDC30_1, 1, 1),
141 FACTOR1(CLK_TOP_SPI, CLK_TOP_SPI0_SEL, 1, 1),
142 FACTOR1(CLK_TOP_SF, CLK_TOP_NFI_INFRA_SEL, 1, 1),
143 FACTOR1(CLK_TOP_FLASH, CLK_TOP_FLASH_SEL, 1, 1),
144 FACTOR1(CLK_TOP_TO_USB3_REF, CLK_TOP_SATA_SEL, 1, 4),
145 FACTOR1(CLK_TOP_TO_USB3_MCU, CLK_TOP_AXI_SEL, 1, 1),
146 FACTOR1(CLK_TOP_TO_USB3_DMA, CLK_TOP_HIF_SEL, 1, 1),
147 FACTOR1(CLK_TOP_FROM_TOP_AHB, CLK_TOP_AXI_SEL, 1, 1),
148 FACTOR1(CLK_TOP_FROM_TOP_AXI, CLK_TOP_HIF_SEL, 1, 1),
149 FACTOR1(CLK_TOP_PCIE1_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1),
150 FACTOR1(CLK_TOP_PCIE0_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1),
151 };
152
153 static const int axi_parents[] = {
154 CLK_XTAL,
155 CLK_TOP_SYSPLL1_D2,
156 CLK_TOP_SYSPLL_D5,
157 CLK_TOP_SYSPLL1_D4,
158 CLK_TOP_UNIVPLL_D5,
159 CLK_TOP_UNIVPLL2_D2,
160 CLK_TOP_UNIVPLL_D7,
161 CLK_TOP_DMPLL
162 };
163
164 static const int mem_parents[] = {
165 CLK_XTAL,
166 CLK_TOP_DMPLL
167 };
168
169 static const int ddrphycfg_parents[] = {
170 CLK_XTAL,
171 CLK_TOP_SYSPLL1_D8
172 };
173
174 static const int eth_parents[] = {
175 CLK_XTAL,
176 CLK_TOP_SYSPLL1_D2,
177 CLK_TOP_UNIVPLL1_D2,
178 CLK_TOP_SYSPLL1_D4,
179 CLK_TOP_UNIVPLL_D5,
180 CLK_TOP_SGMIIPLL_D2,
181 CLK_TOP_UNIVPLL_D7,
182 CLK_TOP_DMPLL
183 };
184
185 static const int pwm_parents[] = {
186 CLK_XTAL,
187 CLK_TOP_UNIVPLL2_D4
188 };
189
190 static const int f10m_ref_parents[] = {
191 CLK_XTAL,
192 CLK_TOP_SGMIIPLL_D2
193 };
194
195 static const int nfi_infra_parents[] = {
196 CLK_XTAL,
197 CLK_XTAL,
198 CLK_XTAL,
199 CLK_XTAL,
200 CLK_XTAL,
201 CLK_XTAL,
202 CLK_TOP_UNIVPLL2_D8,
203 CLK_TOP_UNIVPLL3_D4,
204 CLK_TOP_SYSPLL1_D8,
205 CLK_TOP_UNIVPLL1_D8,
206 CLK_TOP_SYSPLL4_D2,
207 CLK_TOP_SYSPLL2_D4,
208 CLK_TOP_UNIVPLL2_D4,
209 CLK_TOP_UNIVPLL3_D2,
210 CLK_TOP_SYSPLL1_D4,
211 CLK_TOP_SYSPLL_D7
212 };
213
214 static const int flash_parents[] = {
215 CLK_XTAL,
216 CLK_TOP_UNIVPLL_D80_D4,
217 CLK_TOP_SYSPLL2_D8,
218 CLK_TOP_SYSPLL3_D4,
219 CLK_TOP_UNIVPLL3_D4,
220 CLK_TOP_UNIVPLL1_D8,
221 CLK_TOP_SYSPLL2_D4,
222 CLK_TOP_UNIVPLL2_D4
223 };
224
225 static const int uart_parents[] = {
226 CLK_XTAL,
227 CLK_TOP_UNIVPLL2_D8
228 };
229
230 static const int spi0_parents[] = {
231 CLK_XTAL,
232 CLK_TOP_SYSPLL3_D2,
233 CLK_XTAL,
234 CLK_TOP_SYSPLL2_D4,
235 CLK_TOP_SYSPLL4_D2,
236 CLK_TOP_UNIVPLL2_D4,
237 CLK_TOP_UNIVPLL1_D8,
238 CLK_XTAL
239 };
240
241 static const int spi1_parents[] = {
242 CLK_XTAL,
243 CLK_TOP_SYSPLL3_D2,
244 CLK_XTAL,
245 CLK_TOP_SYSPLL4_D4,
246 CLK_TOP_SYSPLL4_D2,
247 CLK_TOP_UNIVPLL2_D4,
248 CLK_TOP_UNIVPLL1_D8,
249 CLK_XTAL
250 };
251
252 static const int msdc30_0_parents[] = {
253 CLK_XTAL,
254 CLK_TOP_UNIVPLL2_D16,
255 CLK_TOP_UNIV48M
256 };
257
258 static const int msdc30_1_parents[] = {
259 CLK_XTAL,
260 CLK_TOP_UNIVPLL2_D16,
261 CLK_TOP_UNIV48M,
262 CLK_TOP_SYSPLL2_D4,
263 CLK_TOP_UNIVPLL2_D4,
264 CLK_TOP_SYSPLL_D7,
265 CLK_TOP_SYSPLL2_D2,
266 CLK_TOP_UNIVPLL2_D2
267 };
268
269 static const int ap2wbmcu_parents[] = {
270 CLK_XTAL,
271 CLK_TOP_SYSPLL1_D2,
272 CLK_TOP_UNIV48M,
273 CLK_TOP_SYSPLL1_D8,
274 CLK_TOP_UNIVPLL2_D4,
275 CLK_TOP_SYSPLL_D7,
276 CLK_TOP_SYSPLL2_D2,
277 CLK_TOP_UNIVPLL2_D2
278 };
279
280 static const int audio_parents[] = {
281 CLK_XTAL,
282 CLK_TOP_SYSPLL3_D4,
283 CLK_TOP_SYSPLL4_D4,
284 CLK_TOP_SYSPLL1_D16
285 };
286
287 static const int aud_intbus_parents[] = {
288 CLK_XTAL,
289 CLK_TOP_SYSPLL1_D4,
290 CLK_TOP_SYSPLL4_D2,
291 CLK_TOP_DMPLL_D4
292 };
293
294 static const int pmicspi_parents[] = {
295 CLK_XTAL,
296 CLK_TOP_SYSPLL1_D8,
297 CLK_TOP_SYSPLL3_D4,
298 CLK_TOP_SYSPLL1_D16,
299 CLK_TOP_UNIVPLL3_D4,
300 CLK_XTAL,
301 CLK_TOP_UNIVPLL2_D4,
302 CLK_TOP_DMPLL_D8
303 };
304
305 static const int scp_parents[] = {
306 CLK_XTAL,
307 CLK_TOP_SYSPLL1_D8,
308 CLK_TOP_UNIVPLL2_D2,
309 CLK_TOP_UNIVPLL2_D4
310 };
311
312 static const int atb_parents[] = {
313 CLK_XTAL,
314 CLK_TOP_SYSPLL1_D2,
315 CLK_TOP_SYSPLL_D5
316 };
317
318 static const int hif_parents[] = {
319 CLK_XTAL,
320 CLK_TOP_SYSPLL1_D2,
321 CLK_TOP_UNIVPLL1_D2,
322 CLK_TOP_SYSPLL1_D4,
323 CLK_TOP_UNIVPLL_D5,
324 -1,
325 CLK_TOP_UNIVPLL_D7
326 };
327
328 static const int sata_parents[] = {
329 CLK_XTAL,
330 CLK_TOP_UNIVPLL2_D4
331 };
332
333 static const int usb20_parents[] = {
334 CLK_XTAL,
335 CLK_TOP_UNIVPLL3_D4,
336 CLK_TOP_SYSPLL1_D8
337 };
338
339 static const int aud1_parents[] = {
340 CLK_XTAL
341 };
342
343 static const int irrx_parents[] = {
344 CLK_XTAL,
345 CLK_TOP_SYSPLL4_D16
346 };
347
348 static const int crypto_parents[] = {
349 CLK_XTAL,
350 CLK_TOP_UNIVPLL_D3,
351 CLK_TOP_UNIVPLL1_D2,
352 CLK_TOP_SYSPLL1_D2,
353 CLK_TOP_UNIVPLL_D5,
354 CLK_TOP_SYSPLL_D5,
355 CLK_TOP_UNIVPLL2_D2,
356 CLK_TOP_SYSPLL_D2
357 };
358
359 static const int gpt10m_parents[] = {
360 CLK_XTAL,
361 CLK_TOP_CLKXTAL_D4
362 };
363
364 static const struct mtk_composite top_muxes[] = {
365 /* CLK_CFG_0 */
366 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
367 MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
368 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
369 MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31),
370
371 /* CLK_CFG_1 */
372 MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
373 MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15),
374 MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23),
375 MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31),
376
377 /* CLK_CFG_2 */
378 MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
379 MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15),
380 MUX_GATE(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23),
381 MUX_GATE(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31),
382
383 /* CLK_CFG_3 */
384 MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7),
385 MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_1_parents, 0x70, 8, 3, 15),
386 MUX_GATE(CLK_TOP_AP2WBMCU_SEL, ap2wbmcu_parents, 0x70, 16, 3, 23),
387 MUX_GATE(CLK_TOP_AP2WBHIF_SEL, ap2wbmcu_parents, 0x70, 24, 3, 31),
388
389 /* CLK_CFG_4 */
390 MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x80, 0, 2, 7),
391 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15),
392 MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23),
393 MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x80, 24, 2, 31),
394
395 /* CLK_CFG_5 */
396 MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7),
397 MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, hif_parents, 0x90, 8, 3, 15,
398 CLK_DOMAIN_SCPSYS),
399 MUX_GATE(CLK_TOP_SATA_SEL, sata_parents, 0x90, 16, 1, 23),
400 MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31),
401
402 /* CLK_CFG_6 */
403 MUX_GATE(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7),
404 MUX_GATE(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15),
405 MUX_GATE(CLK_TOP_IRRX_SEL, irrx_parents, 0xA0, 16, 1, 23),
406 MUX_GATE(CLK_TOP_IRTX_SEL, irrx_parents, 0xA0, 24, 1, 31),
407
408 /* CLK_CFG_7 */
409 MUX_GATE(CLK_TOP_SATA_MCU_SEL, scp_parents, 0xB0, 0, 2, 7),
410 MUX_GATE(CLK_TOP_PCIE0_MCU_SEL, scp_parents, 0xB0, 8, 2, 15),
411 MUX_GATE(CLK_TOP_PCIE1_MCU_SEL, scp_parents, 0xB0, 16, 2, 23),
412 MUX_GATE(CLK_TOP_SSUSB_MCU_SEL, scp_parents, 0xB0, 24, 2, 31),
413
414 /* CLK_CFG_8 */
415 MUX_GATE(CLK_TOP_CRYPTO_SEL, crypto_parents, 0xC0, 0, 3, 7),
416 MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, f10m_ref_parents, 0xC0, 8, 1, 15),
417 MUX_GATE(CLK_TOP_10M_SEL, gpt10m_parents, 0xC0, 16, 1, 23),
418 };
419
420 /* infracfg */
421 static const struct mtk_gate_regs infra_cg_regs = {
422 .set_ofs = 0x40,
423 .clr_ofs = 0x44,
424 .sta_ofs = 0x48,
425 };
426
427 #define GATE_INFRA(_id, _parent, _shift) { \
428 .id = _id, \
429 .parent = _parent, \
430 .regs = &infra_cg_regs, \
431 .shift = _shift, \
432 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
433 }
434
435 static const struct mtk_gate infra_cgs[] = {
436 GATE_INFRA(CLK_INFRA_DBGCLK_PD, CLK_TOP_HD_FAXI, 0),
437 GATE_INFRA(CLK_INFRA_TRNG_PD, CLK_TOP_HD_FAXI, 2),
438 GATE_INFRA(CLK_INFRA_DEVAPC_PD, CLK_TOP_HD_FAXI, 4),
439 GATE_INFRA(CLK_INFRA_APXGPT_PD, CLK_TOP_10M_INFRAO, 18),
440 GATE_INFRA(CLK_INFRA_SEJ_PD, CLK_TOP_10M_INFRAO, 19),
441 };
442
443 /* pericfg */
444 static const struct mtk_gate_regs peri0_cg_regs = {
445 .set_ofs = 0x8,
446 .clr_ofs = 0x10,
447 .sta_ofs = 0x18,
448 };
449
450 static const struct mtk_gate_regs peri1_cg_regs = {
451 .set_ofs = 0xC,
452 .clr_ofs = 0x14,
453 .sta_ofs = 0x1C,
454 };
455
456 #define GATE_PERI0(_id, _parent, _shift) { \
457 .id = _id, \
458 .parent = _parent, \
459 .regs = &peri0_cg_regs, \
460 .shift = _shift, \
461 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
462 }
463
464 #define GATE_PERI1(_id, _parent, _shift) { \
465 .id = _id, \
466 .parent = _parent, \
467 .regs = &peri1_cg_regs, \
468 .shift = _shift, \
469 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
470 }
471
472 static const struct mtk_gate peri_cgs[] = {
473 GATE_PERI0(CLK_PERI_PWM1_PD, CLK_TOP_PWM_QTR_26M, 2),
474 GATE_PERI0(CLK_PERI_PWM2_PD, CLK_TOP_PWM_QTR_26M, 3),
475 GATE_PERI0(CLK_PERI_PWM3_PD, CLK_TOP_PWM_QTR_26M, 4),
476 GATE_PERI0(CLK_PERI_PWM4_PD, CLK_TOP_PWM_QTR_26M, 5),
477 GATE_PERI0(CLK_PERI_PWM5_PD, CLK_TOP_PWM_QTR_26M, 6),
478 GATE_PERI0(CLK_PERI_PWM6_PD, CLK_TOP_PWM_QTR_26M, 7),
479 GATE_PERI0(CLK_PERI_PWM7_PD, CLK_TOP_PWM_QTR_26M, 8),
480 GATE_PERI0(CLK_PERI_PWM_PD, CLK_TOP_PWM_QTR_26M, 9),
481 GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_FAXI, 12),
482 GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1, 14),
483 GATE_PERI0(CLK_PERI_UART0_PD, CLK_TOP_FAXI, 17),
484 GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_FAXI, 18),
485 GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_FAXI, 19),
486 GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_FAXI, 20),
487 GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_FAXI, 22),
488 GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_FAXI, 23),
489 GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI, 28),
490 GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_SF, 29),
491 GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_FAXI, 30),
492 GATE_PERI0(CLK_PERI_NFIECC_PD, CLK_TOP_FAXI, 31),
493 GATE_PERI1(CLK_PERI_FLASH_PD, CLK_TOP_FLASH, 1),
494 };
495
496 /* ethsys */
497 static const struct mtk_gate_regs eth_cg_regs = {
498 .sta_ofs = 0x30,
499 };
500
501 #define GATE_ETH(_id, _parent, _shift, _flag) { \
502 .id = _id, \
503 .parent = _parent, \
504 .regs = ð_cg_regs, \
505 .shift = _shift, \
506 .flags = CLK_GATE_NO_SETCLR_INV | (_flag), \
507 }
508
509 #define GATE_ETH0(_id, _parent, _shift) \
510 GATE_ETH(_id, _parent, _shift, CLK_PARENT_APMIXED)
511
512 #define GATE_ETH1(_id, _parent, _shift) \
513 GATE_ETH(_id, _parent, _shift, CLK_PARENT_TOPCKGEN)
514
515 static const struct mtk_gate eth_cgs[] = {
516 GATE_ETH0(CLK_ETH_FE_EN, CLK_APMIXED_ETH2PLL, 6),
517 GATE_ETH1(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7),
518 GATE_ETH1(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8),
519 GATE_ETH1(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9),
520 GATE_ETH1(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 16),
521 };
522
523 static const struct mtk_gate_regs sgmii_cg_regs = {
524 .set_ofs = 0xE4,
525 .clr_ofs = 0xE4,
526 .sta_ofs = 0xE4,
527 };
528
529 #define GATE_SGMII(_id, _parent, _shift) { \
530 .id = _id, \
531 .parent = _parent, \
532 .regs = &sgmii_cg_regs, \
533 .shift = _shift, \
534 .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
535 }
536
537 static const struct mtk_gate sgmii_cgs[] = {
538 GATE_SGMII(CLK_SGMII_TX_EN, CLK_TOP_SSUSB_TX250M, 2),
539 GATE_SGMII(CLK_SGMII_RX_EN, CLK_TOP_SSUSB_EQ_RX250M, 3),
540 GATE_SGMII(CLK_SGMII_CDR_REF, CLK_TOP_SSUSB_CDR_REF, 4),
541 GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5),
542 };
543
544 static const struct mtk_gate_regs ssusb_cg_regs = {
545 .set_ofs = 0x30,
546 .clr_ofs = 0x30,
547 .sta_ofs = 0x30,
548 };
549
550 #define GATE_SSUSB(_id, _parent, _shift) { \
551 .id = _id, \
552 .parent = _parent, \
553 .regs = &ssusb_cg_regs, \
554 .shift = _shift, \
555 .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
556 }
557
558 static const struct mtk_gate ssusb_cgs[] = {
559 GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, CLK_TOP_TO_U2_PHY_1P, 0),
560 GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, CLK_TOP_TO_U2_PHY, 1),
561 GATE_SSUSB(CLK_SSUSB_REF_EN, CLK_TOP_TO_USB3_REF, 5),
562 GATE_SSUSB(CLK_SSUSB_SYS_EN, CLK_TOP_TO_USB3_SYS, 6),
563 GATE_SSUSB(CLK_SSUSB_MCU_EN, CLK_TOP_TO_USB3_MCU, 7),
564 GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_TO_USB3_DMA, 8),
565 };
566
567 static const struct mtk_clk_tree mt7629_clk_tree = {
568 .xtal_rate = 40 * MHZ,
569 .xtal2_rate = 20 * MHZ,
570 .fdivs_offs = CLK_TOP_TO_USB3_SYS,
571 .muxes_offs = CLK_TOP_AXI_SEL,
572 .plls = apmixed_plls,
573 .fclks = top_fixed_clks,
574 .fdivs = top_fixed_divs,
575 .muxes = top_muxes,
576 };
577
mt7629_mcucfg_probe(struct udevice * dev)578 static int mt7629_mcucfg_probe(struct udevice *dev)
579 {
580 void __iomem *base;
581
582 base = dev_read_addr_ptr(dev);
583 if (!base)
584 return -ENOENT;
585
586 clrsetbits_le32(base + MCU_AXI_DIV, AXI_DIV_MSK,
587 AXI_DIV_SEL(0x12));
588 clrsetbits_le32(base + MCU_BUS_MUX, MCU_BUS_MSK,
589 MCU_BUS_SEL(0x1));
590
591 return 0;
592 }
593
mt7629_apmixedsys_probe(struct udevice * dev)594 static int mt7629_apmixedsys_probe(struct udevice *dev)
595 {
596 struct mtk_clk_priv *priv = dev_get_priv(dev);
597 int ret;
598
599 ret = mtk_common_clk_init(dev, &mt7629_clk_tree);
600 if (ret)
601 return ret;
602
603 /* reduce clock square disable time */
604 writel(0x501, priv->base + MT7629_CLKSQ_STB_CON0);
605 /* extend pwr/iso control timing to 1us */
606 writel(0x80008, priv->base + MT7629_PLL_ISO_CON0);
607
608 return 0;
609 }
610
mt7629_topckgen_probe(struct udevice * dev)611 static int mt7629_topckgen_probe(struct udevice *dev)
612 {
613 return mtk_common_clk_init(dev, &mt7629_clk_tree);
614 }
615
mt7629_infracfg_probe(struct udevice * dev)616 static int mt7629_infracfg_probe(struct udevice *dev)
617 {
618 return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, infra_cgs);
619 }
620
mt7629_pericfg_probe(struct udevice * dev)621 static int mt7629_pericfg_probe(struct udevice *dev)
622 {
623 return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, peri_cgs);
624 }
625
mt7629_ethsys_probe(struct udevice * dev)626 static int mt7629_ethsys_probe(struct udevice *dev)
627 {
628 return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, eth_cgs);
629 }
630
mt7629_ethsys_bind(struct udevice * dev)631 static int mt7629_ethsys_bind(struct udevice *dev)
632 {
633 int ret = 0;
634
635 #if CONFIG_IS_ENABLED(RESET_MEDIATEK)
636 ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
637 if (ret)
638 debug("Warning: failed to bind reset controller\n");
639 #endif
640
641 return ret;
642 }
643
mt7629_sgmiisys_probe(struct udevice * dev)644 static int mt7629_sgmiisys_probe(struct udevice *dev)
645 {
646 return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, sgmii_cgs);
647 }
648
mt7629_ssusbsys_probe(struct udevice * dev)649 static int mt7629_ssusbsys_probe(struct udevice *dev)
650 {
651 return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, ssusb_cgs);
652 }
653
654 static const struct udevice_id mt7629_apmixed_compat[] = {
655 { .compatible = "mediatek,mt7629-apmixedsys" },
656 { }
657 };
658
659 static const struct udevice_id mt7629_topckgen_compat[] = {
660 { .compatible = "mediatek,mt7629-topckgen" },
661 { }
662 };
663
664 static const struct udevice_id mt7629_infracfg_compat[] = {
665 { .compatible = "mediatek,mt7629-infracfg", },
666 { }
667 };
668
669 static const struct udevice_id mt7629_pericfg_compat[] = {
670 { .compatible = "mediatek,mt7629-pericfg", },
671 { }
672 };
673
674 static const struct udevice_id mt7629_ethsys_compat[] = {
675 { .compatible = "mediatek,mt7629-ethsys", },
676 { }
677 };
678
679 static const struct udevice_id mt7629_sgmiisys_compat[] = {
680 { .compatible = "mediatek,mt7629-sgmiisys", },
681 { }
682 };
683
684 static const struct udevice_id mt7629_ssusbsys_compat[] = {
685 { .compatible = "mediatek,mt7629-ssusbsys" },
686 { }
687 };
688
689 static const struct udevice_id mt7629_mcucfg_compat[] = {
690 { .compatible = "mediatek,mt7629-mcucfg" },
691 { }
692 };
693
694 U_BOOT_DRIVER(mtk_mcucfg) = {
695 .name = "mt7629-mcucfg",
696 .id = UCLASS_SYSCON,
697 .of_match = mt7629_mcucfg_compat,
698 .probe = mt7629_mcucfg_probe,
699 .flags = DM_FLAG_PRE_RELOC,
700 };
701
702 U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
703 .name = "mt7629-clock-apmixedsys",
704 .id = UCLASS_CLK,
705 .of_match = mt7629_apmixed_compat,
706 .probe = mt7629_apmixedsys_probe,
707 .priv_auto = sizeof(struct mtk_clk_priv),
708 .ops = &mtk_clk_apmixedsys_ops,
709 .flags = DM_FLAG_PRE_RELOC,
710 };
711
712 U_BOOT_DRIVER(mtk_clk_topckgen) = {
713 .name = "mt7629-clock-topckgen",
714 .id = UCLASS_CLK,
715 .of_match = mt7629_topckgen_compat,
716 .probe = mt7629_topckgen_probe,
717 .priv_auto = sizeof(struct mtk_clk_priv),
718 .ops = &mtk_clk_topckgen_ops,
719 .flags = DM_FLAG_PRE_RELOC,
720 };
721
722 U_BOOT_DRIVER(mtk_clk_infracfg) = {
723 .name = "mt7629-clock-infracfg",
724 .id = UCLASS_CLK,
725 .of_match = mt7629_infracfg_compat,
726 .probe = mt7629_infracfg_probe,
727 .priv_auto = sizeof(struct mtk_cg_priv),
728 .ops = &mtk_clk_gate_ops,
729 .flags = DM_FLAG_PRE_RELOC,
730 };
731
732 U_BOOT_DRIVER(mtk_clk_pericfg) = {
733 .name = "mt7629-clock-pericfg",
734 .id = UCLASS_CLK,
735 .of_match = mt7629_pericfg_compat,
736 .probe = mt7629_pericfg_probe,
737 .priv_auto = sizeof(struct mtk_cg_priv),
738 .ops = &mtk_clk_gate_ops,
739 .flags = DM_FLAG_PRE_RELOC,
740 };
741
742 U_BOOT_DRIVER(mtk_clk_ethsys) = {
743 .name = "mt7629-clock-ethsys",
744 .id = UCLASS_CLK,
745 .of_match = mt7629_ethsys_compat,
746 .probe = mt7629_ethsys_probe,
747 .bind = mt7629_ethsys_bind,
748 .priv_auto = sizeof(struct mtk_cg_priv),
749 .ops = &mtk_clk_gate_ops,
750 };
751
752 U_BOOT_DRIVER(mtk_clk_sgmiisys) = {
753 .name = "mt7629-clock-sgmiisys",
754 .id = UCLASS_CLK,
755 .of_match = mt7629_sgmiisys_compat,
756 .probe = mt7629_sgmiisys_probe,
757 .priv_auto = sizeof(struct mtk_cg_priv),
758 .ops = &mtk_clk_gate_ops,
759 };
760
761 U_BOOT_DRIVER(mtk_clk_ssusbsys) = {
762 .name = "mt7629-clock-ssusbsys",
763 .id = UCLASS_CLK,
764 .of_match = mt7629_ssusbsys_compat,
765 .probe = mt7629_ssusbsys_probe,
766 .priv_auto = sizeof(struct mtk_cg_priv),
767 .ops = &mtk_clk_gate_ops,
768 };
769