1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) EETS GmbH, 2017, Felix Brack <f.brack@eets.ch>
4 * Copyright (C) 2021 Dario Binacchi <dariobin@libero.it>
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <dm/device_compat.h>
10 #include <dm/devres.h>
11 #include <dm/pinctrl.h>
12 #include <linux/libfdt.h>
13 #include <linux/list.h>
14 #include <asm/io.h>
15 #include <sort.h>
16
17 /**
18 * struct single_pdata - platform data
19 * @base: first configuration register
20 * @offset: index of last configuration register
21 * @mask: configuration-value mask bits
22 * @width: configuration register bit width
23 * @bits_per_mux: true if one register controls more than one pin
24 */
25 struct single_pdata {
26 fdt_addr_t base;
27 int offset;
28 u32 mask;
29 u32 width;
30 bool bits_per_mux;
31 };
32
33 /**
34 * struct single_func - pinctrl function
35 * @node: list node
36 * @name: pinctrl function name
37 * @npins: number of entries in pins array
38 * @pins: pins array
39 */
40 struct single_func {
41 struct list_head node;
42 const char *name;
43 unsigned int npins;
44 unsigned int *pins;
45 };
46
47 /**
48 * struct single_priv - private data
49 * @bits_per_pin: number of bits per pin
50 * @npins: number of selectable pins
51 * @pin_name: temporary buffer to store the pin name
52 */
53 struct single_priv {
54 #if (IS_ENABLED(CONFIG_SANDBOX))
55 u32 *sandbox_regs;
56 #endif
57 unsigned int bits_per_pin;
58 unsigned int npins;
59 char pin_name[PINNAME_SIZE];
60 struct list_head functions;
61 };
62
63 /**
64 * struct single_fdt_pin_cfg - pin configuration
65 *
66 * This structure is used for the pin configuration parameters in case
67 * the register controls only one pin.
68 *
69 * @reg: configuration register offset
70 * @val: configuration register value
71 */
72 struct single_fdt_pin_cfg {
73 fdt32_t reg;
74 fdt32_t val;
75 };
76
77 /**
78 * struct single_fdt_bits_cfg - pin configuration
79 *
80 * This structure is used for the pin configuration parameters in case
81 * the register controls more than one pin.
82 *
83 * @reg: configuration register offset
84 * @val: configuration register value
85 * @mask: configuration register mask
86 */
87 struct single_fdt_bits_cfg {
88 fdt32_t reg;
89 fdt32_t val;
90 fdt32_t mask;
91 };
92
93 #if (!IS_ENABLED(CONFIG_SANDBOX))
94
single_read(struct udevice * dev,fdt_addr_t reg)95 static unsigned int single_read(struct udevice *dev, fdt_addr_t reg)
96 {
97 struct single_pdata *pdata = dev_get_plat(dev);
98
99 switch (pdata->width) {
100 case 8:
101 return readb(reg);
102 case 16:
103 return readw(reg);
104 default: /* 32 bits */
105 return readl(reg);
106 }
107
108 return readb(reg);
109 }
110
single_write(struct udevice * dev,unsigned int val,fdt_addr_t reg)111 static void single_write(struct udevice *dev, unsigned int val, fdt_addr_t reg)
112 {
113 struct single_pdata *pdata = dev_get_plat(dev);
114
115 switch (pdata->width) {
116 case 8:
117 writeb(val, reg);
118 break;
119 case 16:
120 writew(val, reg);
121 break;
122 default: /* 32 bits */
123 writel(val, reg);
124 }
125 }
126
127 #else /* CONFIG_SANDBOX */
128
single_read(struct udevice * dev,fdt_addr_t reg)129 static unsigned int single_read(struct udevice *dev, fdt_addr_t reg)
130 {
131 struct single_priv *priv = dev_get_priv(dev);
132
133 return priv->sandbox_regs[reg];
134 }
135
single_write(struct udevice * dev,unsigned int val,fdt_addr_t reg)136 static void single_write(struct udevice *dev, unsigned int val, fdt_addr_t reg)
137 {
138 struct single_priv *priv = dev_get_priv(dev);
139
140 priv->sandbox_regs[reg] = val;
141 }
142
143 #endif /* CONFIG_SANDBOX */
144
145 /**
146 * single_get_pin_by_offset() - get a pin based on the register offset
147 * @dev: single driver instance
148 * @offset: register offset from the base
149 */
single_get_pin_by_offset(struct udevice * dev,unsigned int offset)150 static int single_get_pin_by_offset(struct udevice *dev, unsigned int offset)
151 {
152 struct single_pdata *pdata = dev_get_plat(dev);
153 struct single_priv *priv = dev_get_priv(dev);
154
155 if (offset > pdata->offset) {
156 dev_err(dev, "mux offset out of range: 0x%x (0x%x)\n",
157 offset, pdata->offset);
158 return -EINVAL;
159 }
160
161 if (pdata->bits_per_mux)
162 return (offset * BITS_PER_BYTE) / priv->bits_per_pin;
163
164 return offset / (pdata->width / BITS_PER_BYTE);
165 }
166
single_get_offset_by_pin(struct udevice * dev,unsigned int pin)167 static int single_get_offset_by_pin(struct udevice *dev, unsigned int pin)
168 {
169 struct single_pdata *pdata = dev_get_plat(dev);
170 struct single_priv *priv = dev_get_priv(dev);
171 unsigned int mux_bytes;
172
173 if (pin >= priv->npins)
174 return -EINVAL;
175
176 mux_bytes = pdata->width / BITS_PER_BYTE;
177 if (pdata->bits_per_mux) {
178 int byte_num;
179
180 byte_num = (priv->bits_per_pin * pin) / BITS_PER_BYTE;
181 return (byte_num / mux_bytes) * mux_bytes;
182 }
183
184 return pin * mux_bytes;
185 }
186
single_get_pin_function(struct udevice * dev,unsigned int pin)187 static const char *single_get_pin_function(struct udevice *dev,
188 unsigned int pin)
189 {
190 struct single_priv *priv = dev_get_priv(dev);
191 struct single_func *func;
192 int i;
193
194 list_for_each_entry(func, &priv->functions, node) {
195 for (i = 0; i < func->npins; i++) {
196 if (pin == func->pins[i])
197 return func->name;
198
199 if (pin < func->pins[i])
200 break;
201 }
202 }
203
204 return NULL;
205 }
206
single_get_pin_muxing(struct udevice * dev,unsigned int pin,char * buf,int size)207 static int single_get_pin_muxing(struct udevice *dev, unsigned int pin,
208 char *buf, int size)
209 {
210 struct single_pdata *pdata = dev_get_plat(dev);
211 struct single_priv *priv = dev_get_priv(dev);
212 fdt_addr_t reg;
213 const char *fname;
214 unsigned int val;
215 int offset, pin_shift = 0;
216
217 offset = single_get_offset_by_pin(dev, pin);
218 if (offset < 0)
219 return offset;
220
221 reg = pdata->base + offset;
222 val = single_read(dev, reg);
223
224 if (pdata->bits_per_mux)
225 pin_shift = pin % (pdata->width / priv->bits_per_pin) *
226 priv->bits_per_pin;
227
228 val &= (pdata->mask << pin_shift);
229 fname = single_get_pin_function(dev, pin);
230 snprintf(buf, size, "%pa 0x%08x %s", ®, val,
231 fname ? fname : "UNCLAIMED");
232 return 0;
233 }
234
single_allocate_function(struct udevice * dev,unsigned int group_pins)235 static struct single_func *single_allocate_function(struct udevice *dev,
236 unsigned int group_pins)
237 {
238 struct single_func *func;
239
240 func = devm_kmalloc(dev, sizeof(*func), GFP_KERNEL);
241 if (!func)
242 return ERR_PTR(-ENOMEM);
243
244 func->pins = devm_kmalloc(dev, sizeof(unsigned int) * group_pins,
245 GFP_KERNEL);
246 if (!func->pins)
247 return ERR_PTR(-ENOMEM);
248
249 return func;
250 }
251
single_pin_compare(const void * s1,const void * s2)252 static int single_pin_compare(const void *s1, const void *s2)
253 {
254 int pin1 = *(const unsigned int *)s1;
255 int pin2 = *(const unsigned int *)s2;
256
257 return pin1 - pin2;
258 }
259
260 /**
261 * single_configure_pins() - Configure pins based on FDT data
262 *
263 * @dev: Pointer to single pin configuration device which is the parent of
264 * the pins node holding the pin configuration data.
265 * @pins: Pointer to the first element of an array of register/value pairs
266 * of type 'struct single_fdt_pin_cfg'. Each such pair describes the
267 * the pin to be configured and the value to be used for configuration.
268 * This pointer points to a 'pinctrl-single,pins' property in the
269 * device-tree.
270 * @size: Size of the 'pins' array in bytes.
271 * The number of register/value pairs in the 'pins' array therefore
272 * equals to 'size / sizeof(struct single_fdt_pin_cfg)'.
273 * @fname: Function name.
274 */
single_configure_pins(struct udevice * dev,const struct single_fdt_pin_cfg * pins,int size,const char * fname)275 static int single_configure_pins(struct udevice *dev,
276 const struct single_fdt_pin_cfg *pins,
277 int size, const char *fname)
278 {
279 struct single_pdata *pdata = dev_get_plat(dev);
280 struct single_priv *priv = dev_get_priv(dev);
281 int n, pin, count = size / sizeof(struct single_fdt_pin_cfg);
282 struct single_func *func;
283 phys_addr_t reg;
284 u32 offset, val;
285
286 /* If function mask is null, needn't enable it. */
287 if (!pdata->mask)
288 return 0;
289
290 func = single_allocate_function(dev, count);
291 if (IS_ERR(func))
292 return PTR_ERR(func);
293
294 func->name = fname;
295 func->npins = 0;
296 for (n = 0; n < count; n++, pins++) {
297 offset = fdt32_to_cpu(pins->reg);
298 if (offset > pdata->offset) {
299 dev_err(dev, " invalid register offset 0x%x\n",
300 offset);
301 continue;
302 }
303
304 reg = pdata->base + offset;
305 val = fdt32_to_cpu(pins->val) & pdata->mask;
306 pin = single_get_pin_by_offset(dev, offset);
307 if (pin < 0) {
308 dev_err(dev, " failed to get pin by offset %x\n",
309 offset);
310 continue;
311 }
312
313 single_write(dev, (single_read(dev, reg) & ~pdata->mask) | val,
314 reg);
315 dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val);
316 func->pins[func->npins] = pin;
317 func->npins++;
318 }
319
320 qsort(func->pins, func->npins, sizeof(func->pins[0]),
321 single_pin_compare);
322 list_add(&func->node, &priv->functions);
323 return 0;
324 }
325
single_configure_bits(struct udevice * dev,const struct single_fdt_bits_cfg * pins,int size,const char * fname)326 static int single_configure_bits(struct udevice *dev,
327 const struct single_fdt_bits_cfg *pins,
328 int size, const char *fname)
329 {
330 struct single_pdata *pdata = dev_get_plat(dev);
331 struct single_priv *priv = dev_get_priv(dev);
332 int n, pin, count = size / sizeof(struct single_fdt_bits_cfg);
333 int npins_in_reg, pin_num_from_lsb;
334 struct single_func *func;
335 phys_addr_t reg;
336 u32 offset, val, mask, bit_pos, val_pos, mask_pos, submask;
337
338 /* If function mask is null, needn't enable it. */
339 if (!pdata->mask)
340 return 0;
341
342 npins_in_reg = pdata->width / priv->bits_per_pin;
343 func = single_allocate_function(dev, count * npins_in_reg);
344 if (IS_ERR(func))
345 return PTR_ERR(func);
346
347 func->name = fname;
348 func->npins = 0;
349 for (n = 0; n < count; n++, pins++) {
350 offset = fdt32_to_cpu(pins->reg);
351 if (offset > pdata->offset) {
352 dev_dbg(dev, " invalid register offset 0x%x\n",
353 offset);
354 continue;
355 }
356
357 reg = pdata->base + offset;
358
359 pin = single_get_pin_by_offset(dev, offset);
360 if (pin < 0) {
361 dev_err(dev, " failed to get pin by offset 0x%pa\n",
362 ®);
363 continue;
364 }
365
366 mask = fdt32_to_cpu(pins->mask);
367 val = fdt32_to_cpu(pins->val) & mask;
368 single_write(dev, (single_read(dev, reg) & ~mask) | val, reg);
369 dev_dbg(dev, " reg/val %pa/0x%08x\n", ®, val);
370
371 while (mask) {
372 bit_pos = __ffs(mask);
373 pin_num_from_lsb = bit_pos / priv->bits_per_pin;
374 mask_pos = pdata->mask << bit_pos;
375 val_pos = val & mask_pos;
376 submask = mask & mask_pos;
377
378 if ((mask & mask_pos) == 0) {
379 dev_err(dev, "Invalid mask at 0x%x\n", offset);
380 break;
381 }
382
383 mask &= ~mask_pos;
384
385 if (submask != mask_pos) {
386 dev_warn(dev,
387 "Invalid submask 0x%x at 0x%x\n",
388 submask, offset);
389 continue;
390 }
391
392 func->pins[func->npins] = pin + pin_num_from_lsb;
393 func->npins++;
394 }
395 }
396
397 qsort(func->pins, func->npins, sizeof(func->pins[0]),
398 single_pin_compare);
399 list_add(&func->node, &priv->functions);
400 return 0;
401 }
single_set_state(struct udevice * dev,struct udevice * config)402 static int single_set_state(struct udevice *dev,
403 struct udevice *config)
404 {
405 const struct single_fdt_pin_cfg *prop;
406 const struct single_fdt_bits_cfg *prop_bits;
407 int len;
408
409 prop = dev_read_prop(config, "pinctrl-single,pins", &len);
410
411 if (prop) {
412 dev_dbg(dev, "configuring pins for %s\n", config->name);
413 if (len % sizeof(struct single_fdt_pin_cfg)) {
414 dev_dbg(dev, " invalid pin configuration in fdt\n");
415 return -FDT_ERR_BADSTRUCTURE;
416 }
417 single_configure_pins(dev, prop, len, config->name);
418 return 0;
419 }
420
421 /* pinctrl-single,pins not found so check for pinctrl-single,bits */
422 prop_bits = dev_read_prop(config, "pinctrl-single,bits", &len);
423 if (prop_bits) {
424 dev_dbg(dev, "configuring pins for %s\n", config->name);
425 if (len % sizeof(struct single_fdt_bits_cfg)) {
426 dev_dbg(dev, " invalid bits configuration in fdt\n");
427 return -FDT_ERR_BADSTRUCTURE;
428 }
429 single_configure_bits(dev, prop_bits, len, config->name);
430 return 0;
431 }
432
433 /* Neither 'pinctrl-single,pins' nor 'pinctrl-single,bits' were found */
434 return len;
435 }
436
single_get_pin_name(struct udevice * dev,unsigned int selector)437 static const char *single_get_pin_name(struct udevice *dev,
438 unsigned int selector)
439 {
440 struct single_priv *priv = dev_get_priv(dev);
441
442 if (selector >= priv->npins)
443 snprintf(priv->pin_name, PINNAME_SIZE, "Error");
444 else
445 snprintf(priv->pin_name, PINNAME_SIZE, "PIN%u", selector);
446
447 return priv->pin_name;
448 }
449
single_get_pins_count(struct udevice * dev)450 static int single_get_pins_count(struct udevice *dev)
451 {
452 struct single_priv *priv = dev_get_priv(dev);
453
454 return priv->npins;
455 }
456
single_probe(struct udevice * dev)457 static int single_probe(struct udevice *dev)
458 {
459 struct single_pdata *pdata = dev_get_plat(dev);
460 struct single_priv *priv = dev_get_priv(dev);
461 u32 size;
462
463 INIT_LIST_HEAD(&priv->functions);
464
465 size = pdata->offset + pdata->width / BITS_PER_BYTE;
466 #if (CONFIG_IS_ENABLED(SANDBOX))
467 priv->sandbox_regs =
468 devm_kzalloc(dev, size * sizeof(*priv->sandbox_regs),
469 GFP_KERNEL);
470 if (!priv->sandbox_regs)
471 return -ENOMEM;
472 #endif
473
474 priv->npins = size / (pdata->width / BITS_PER_BYTE);
475 if (pdata->bits_per_mux) {
476 if (!pdata->mask) {
477 dev_err(dev, "function mask needs to be non-zero\n");
478 return -EINVAL;
479 }
480
481 priv->bits_per_pin = fls(pdata->mask);
482 priv->npins *= (pdata->width / priv->bits_per_pin);
483 }
484
485 dev_dbg(dev, "%d pins\n", priv->npins);
486 return 0;
487 }
488
single_of_to_plat(struct udevice * dev)489 static int single_of_to_plat(struct udevice *dev)
490 {
491 fdt_addr_t addr;
492 fdt_size_t size;
493 struct single_pdata *pdata = dev_get_plat(dev);
494 int ret;
495
496 ret = dev_read_u32(dev, "pinctrl-single,register-width", &pdata->width);
497 if (ret) {
498 dev_err(dev, "missing register width\n");
499 return ret;
500 }
501
502 switch (pdata->width) {
503 case 8:
504 case 16:
505 case 32:
506 break;
507 default:
508 dev_err(dev, "wrong register width\n");
509 return -EINVAL;
510 }
511
512 addr = dev_read_addr_size_index(dev, 0, &size);
513 if (addr == FDT_ADDR_T_NONE) {
514 dev_err(dev, "failed to get base register address\n");
515 return -EINVAL;
516 }
517
518 pdata->offset = size - pdata->width / BITS_PER_BYTE;
519 pdata->base = addr;
520
521 ret = dev_read_u32(dev, "pinctrl-single,function-mask", &pdata->mask);
522 if (ret) {
523 pdata->mask = 0;
524 dev_warn(dev, "missing function register mask\n");
525 }
526
527 pdata->bits_per_mux = dev_read_bool(dev, "pinctrl-single,bit-per-mux");
528
529 return 0;
530 }
531
532 const struct pinctrl_ops single_pinctrl_ops = {
533 .get_pins_count = single_get_pins_count,
534 .get_pin_name = single_get_pin_name,
535 .set_state = single_set_state,
536 .get_pin_muxing = single_get_pin_muxing,
537 };
538
539 static const struct udevice_id single_pinctrl_match[] = {
540 { .compatible = "pinctrl-single" },
541 { /* sentinel */ }
542 };
543
544 U_BOOT_DRIVER(single_pinctrl) = {
545 .name = "single-pinctrl",
546 .id = UCLASS_PINCTRL,
547 .of_match = single_pinctrl_match,
548 .ops = &single_pinctrl_ops,
549 .plat_auto = sizeof(struct single_pdata),
550 .priv_auto = sizeof(struct single_priv),
551 .of_to_plat = single_of_to_plat,
552 .probe = single_probe,
553 };
554