1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
4 *
5 * Based on original Kirkwood support which is
6 * (C) Copyright 2009
7 * Marvell Semiconductor <www.marvell.com>
8 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
9 */
10
11 #include <common.h>
12 #include <cpu_func.h>
13 #include <init.h>
14 #include <net.h>
15 #include <netdev.h>
16 #include <asm/cache.h>
17 #include <asm/io.h>
18 #include <u-boot/md5.h>
19 #include <asm/arch/cpu.h>
20
21 #define BUFLEN 16
22
reset_cpu(void)23 void reset_cpu(void)
24 {
25 struct orion5x_cpu_registers *cpureg =
26 (struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE;
27
28 writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
29 &cpureg->rstoutn_mask);
30 writel(readl(&cpureg->sys_soft_rst) | 1,
31 &cpureg->sys_soft_rst);
32 while (1)
33 ;
34 }
35
36 /*
37 * Compute Window Size field value from size expressed in bytes
38 * Used with the Base register to set the address window size and location.
39 * Must be programmed from LSB to MSB as sequence of ones followed by
40 * sequence of zeros. The number of ones specifies the size of the window in
41 * 64 KiB granularity (e.g., a value of 0x00FF specifies 256 = 16 MiB).
42 * NOTES:
43 * 1) A sizeval equal to 0x0 specifies 4 GiB.
44 * 2) A return value of 0x0 specifies 64 KiB.
45 */
orion5x_winctrl_calcsize(unsigned int sizeval)46 unsigned int orion5x_winctrl_calcsize(unsigned int sizeval)
47 {
48 /*
49 * Calculate the number of 64 KiB blocks needed minus one (rounding up).
50 * For sizeval > 0 this is equivalent to:
51 * sizeval = (u32) ceil((double) sizeval / 65536.0) - 1
52 */
53 sizeval = (sizeval - 1) >> 16;
54
55 /*
56 * Propagate 'one' bits to the right by 'oring' them.
57 * We need only treat bits 15-0.
58 */
59 sizeval |= sizeval >> 1; /* 'Or' bit 15 onto bit 14 */
60 sizeval |= sizeval >> 2; /* 'Or' bits 15-14 onto bits 13-12 */
61 sizeval |= sizeval >> 4; /* 'Or' bits 15-12 onto bits 11-8 */
62 sizeval |= sizeval >> 8; /* 'Or' bits 15-8 onto bits 7-0*/
63
64 return sizeval;
65 }
66
67 /*
68 * orion5x_config_adr_windows - Configure address Windows
69 *
70 * There are 8 address windows supported by Orion5x Soc to addess different
71 * devices. Each window can be configured for size, BAR and remap addr
72 * Below configuration is standard for most of the cases
73 *
74 * If remap function not used, remap_lo must be set as base
75 *
76 * NOTES:
77 *
78 * 1) in order to avoid windows with inconsistent control and base values
79 * (which could prevent access to BOOTCS and hence execution from FLASH)
80 * always disable window before writing the base value then reenable it
81 * by writing the control value.
82 *
83 * 2) in order to avoid losing access to BOOTCS when disabling window 7,
84 * first configure window 6 for BOOTCS, then configure window 7 for BOOTCS,
85 * then configure windows 6 for its own target.
86 *
87 * Reference Documentation:
88 * Mbus-L to Mbus Bridge Registers Configuration.
89 * (Sec 25.1 and 25.3 of Datasheet)
90 */
orion5x_config_adr_windows(void)91 int orion5x_config_adr_windows(void)
92 {
93 struct orion5x_win_registers *winregs =
94 (struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;
95
96 /* Disable window 0, configure it for its intended target, enable it. */
97 writel(0, &winregs[0].ctrl);
98 writel(ORION5X_ADR_PCIE_MEM, &winregs[0].base);
99 writel(ORION5X_ADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
100 writel(ORION5X_ADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
101 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM,
102 ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
103 ORION5X_WIN_ENABLE), &winregs[0].ctrl);
104 /* Disable window 1, configure it for its intended target, enable it. */
105 writel(0, &winregs[1].ctrl);
106 writel(ORION5X_ADR_PCIE_IO, &winregs[1].base);
107 writel(ORION5X_ADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
108 writel(ORION5X_ADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
109 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO,
110 ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
111 ORION5X_WIN_ENABLE), &winregs[1].ctrl);
112 /* Disable window 2, configure it for its intended target, enable it. */
113 writel(0, &winregs[2].ctrl);
114 writel(ORION5X_ADR_PCI_MEM, &winregs[2].base);
115 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_MEM,
116 ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM,
117 ORION5X_WIN_ENABLE), &winregs[2].ctrl);
118 /* Disable window 3, configure it for its intended target, enable it. */
119 writel(0, &winregs[3].ctrl);
120 writel(ORION5X_ADR_PCI_IO, &winregs[3].base);
121 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_IO,
122 ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO,
123 ORION5X_WIN_ENABLE), &winregs[3].ctrl);
124 /* Disable window 4, configure it for its intended target, enable it. */
125 writel(0, &winregs[4].ctrl);
126 writel(ORION5X_ADR_DEV_CS0, &winregs[4].base);
127 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS0,
128 ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0,
129 ORION5X_WIN_ENABLE), &winregs[4].ctrl);
130 /* Disable window 5, configure it for its intended target, enable it. */
131 writel(0, &winregs[5].ctrl);
132 writel(ORION5X_ADR_DEV_CS1, &winregs[5].base);
133 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS1,
134 ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1,
135 ORION5X_WIN_ENABLE), &winregs[5].ctrl);
136 /* Disable window 6, configure it for FLASH, enable it. */
137 writel(0, &winregs[6].ctrl);
138 writel(ORION5X_ADR_BOOTROM, &winregs[6].base);
139 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
140 ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
141 ORION5X_WIN_ENABLE), &winregs[6].ctrl);
142 /* Disable window 7, configure it for FLASH, enable it. */
143 writel(0, &winregs[7].ctrl);
144 writel(ORION5X_ADR_BOOTROM, &winregs[7].base);
145 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
146 ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
147 ORION5X_WIN_ENABLE), &winregs[7].ctrl);
148 /* Disable window 6, configure it for its intended target, enable it. */
149 writel(0, &winregs[6].ctrl);
150 writel(ORION5X_ADR_DEV_CS2, &winregs[6].base);
151 writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2,
152 ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
153 ORION5X_WIN_ENABLE), &winregs[6].ctrl);
154
155 return 0;
156 }
157
158 /*
159 * Orion5x identification is done through PCIE space.
160 */
161
orion5x_device_id(void)162 u32 orion5x_device_id(void)
163 {
164 return readl(PCIE_DEV_ID_OFF) >> 16;
165 }
166
orion5x_device_rev(void)167 u32 orion5x_device_rev(void)
168 {
169 return readl(PCIE_DEV_REV_OFF) & 0xff;
170 }
171
172 #if defined(CONFIG_DISPLAY_CPUINFO)
173
174 /* Display device and revision IDs.
175 * This function must cover all known device/revision
176 * combinations, not only the one for which u-boot is
177 * compiled; this way, one can identify actual HW in
178 * case of a mismatch.
179 */
print_cpuinfo(void)180 int print_cpuinfo(void)
181 {
182 char dev_str[7]; /* room enough for 0x0000 plus null byte */
183 char rev_str[5]; /* room enough for 0x00 plus null byte */
184 char *dev_name = NULL;
185 char *rev_name = NULL;
186
187 u32 dev = orion5x_device_id();
188 u32 rev = orion5x_device_rev();
189
190 if (dev == MV88F5181_DEV_ID) {
191 dev_name = "MV88F5181";
192 if (rev == MV88F5181_REV_B1)
193 rev_name = "B1";
194 else if (rev == MV88F5181L_REV_A1) {
195 dev_name = "MV88F5181L";
196 rev_name = "A1";
197 } else if (rev == MV88F5181L_REV_A0) {
198 dev_name = "MV88F5181L";
199 rev_name = "A0";
200 }
201 } else if (dev == MV88F5182_DEV_ID) {
202 dev_name = "MV88F5182";
203 if (rev == MV88F5182_REV_A2)
204 rev_name = "A2";
205 } else if (dev == MV88F5281_DEV_ID) {
206 dev_name = "MV88F5281";
207 if (rev == MV88F5281_REV_D2)
208 rev_name = "D2";
209 else if (rev == MV88F5281_REV_D1)
210 rev_name = "D1";
211 else if (rev == MV88F5281_REV_D0)
212 rev_name = "D0";
213 } else if (dev == MV88F6183_DEV_ID) {
214 dev_name = "MV88F6183";
215 if (rev == MV88F6183_REV_B0)
216 rev_name = "B0";
217 }
218 if (dev_name == NULL) {
219 sprintf(dev_str, "0x%04x", dev);
220 dev_name = dev_str;
221 }
222 if (rev_name == NULL) {
223 sprintf(rev_str, "0x%02x", rev);
224 rev_name = rev_str;
225 }
226
227 printf("SoC: Orion5x %s-%s\n", dev_name, rev_name);
228
229 return 0;
230 }
231 #endif /* CONFIG_DISPLAY_CPUINFO */
232
233 #ifdef CONFIG_ARCH_CPU_INIT
arch_cpu_init(void)234 int arch_cpu_init(void)
235 {
236 /* Enable and invalidate L2 cache in write through mode */
237 invalidate_l2_cache();
238
239 #ifdef CONFIG_SPL_BUILD
240 orion5x_config_adr_windows();
241 #endif
242
243 return 0;
244 }
245 #endif /* CONFIG_ARCH_CPU_INIT */
246
247 /*
248 * SOC specific misc init
249 */
250 #if defined(CONFIG_ARCH_MISC_INIT)
arch_misc_init(void)251 int arch_misc_init(void)
252 {
253 u32 temp;
254
255 /*CPU streaming & write allocate */
256 temp = readfr_extra_feature_reg();
257 temp &= ~(1 << 28); /* disable wr alloc */
258 writefr_extra_feature_reg(temp);
259
260 temp = readfr_extra_feature_reg();
261 temp &= ~(1 << 29); /* streaming disabled */
262 writefr_extra_feature_reg(temp);
263
264 /* L2Cache settings */
265 temp = readfr_extra_feature_reg();
266 /* Disable L2C pre fetch - Set bit 24 */
267 temp |= (1 << 24);
268 /* enable L2C - Set bit 22 */
269 temp |= (1 << 22);
270 writefr_extra_feature_reg(temp);
271
272 icache_enable();
273 /* Change reset vector to address 0x0 */
274 temp = get_cr();
275 set_cr(temp & ~CR_V);
276
277 /* Set CPIOs and MPPs - values provided by board
278 include file */
279 writel(ORION5X_MPP0_7, ORION5X_MPP_BASE+0x00);
280 writel(ORION5X_MPP8_15, ORION5X_MPP_BASE+0x04);
281 writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50);
282 writel(ORION5X_GPIO_OUT_VALUE, ORION5X_GPIO_BASE+0x00);
283 writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04);
284 writel(ORION5X_GPIO_IN_POLARITY, ORION5X_GPIO_BASE+0x0c);
285
286 /* initialize timer */
287 timer_init_r();
288 return 0;
289 }
290 #endif /* CONFIG_ARCH_MISC_INIT */
291
292 #ifdef CONFIG_MVGBE
cpu_eth_init(struct bd_info * bis)293 int cpu_eth_init(struct bd_info *bis)
294 {
295 mvgbe_initialize(bis);
296 return 0;
297 }
298 #endif
299