1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (c) 2014 Google, Inc 4 * 5 * From Coreboot file of the same name 6 */ 7 8 #ifndef _ASM_MTRR_H 9 #define _ASM_MTRR_H 10 11 /* MTRR region types */ 12 #define MTRR_TYPE_UNCACHEABLE 0 13 #define MTRR_TYPE_WRCOMB 1 14 #define MTRR_TYPE_WRTHROUGH 4 15 #define MTRR_TYPE_WRPROT 5 16 #define MTRR_TYPE_WRBACK 6 17 18 #define MTRR_TYPE_COUNT 7 19 20 #define MTRR_CAP_MSR 0x0fe 21 #define MTRR_DEF_TYPE_MSR 0x2ff 22 23 #define MTRR_CAP_SMRR (1 << 11) 24 #define MTRR_CAP_WC (1 << 10) 25 #define MTRR_CAP_FIX (1 << 8) 26 #define MTRR_CAP_VCNT_MASK 0xff 27 28 #define MTRR_DEF_TYPE_MASK 0xff 29 #define MTRR_DEF_TYPE_EN (1 << 11) 30 #define MTRR_DEF_TYPE_FIX_EN (1 << 10) 31 32 #define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg)) 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) 34 35 #define MTRR_PHYS_MASK_VALID (1 << 11) 36 37 #define MTRR_BASE_TYPE_MASK 0x7 38 39 /* Maximum number of MTRRs supported - see also mtrr_get_var_count() */ 40 #define MTRR_MAX_COUNT 10 41 42 #define NUM_FIXED_MTRRS 11 43 #define RANGES_PER_FIXED_MTRR 8 44 #define NUM_FIXED_RANGES (NUM_FIXED_MTRRS * RANGES_PER_FIXED_MTRR) 45 46 #define MTRR_FIX_64K_00000_MSR 0x250 47 #define MTRR_FIX_16K_80000_MSR 0x258 48 #define MTRR_FIX_16K_A0000_MSR 0x259 49 #define MTRR_FIX_4K_C0000_MSR 0x268 50 #define MTRR_FIX_4K_C8000_MSR 0x269 51 #define MTRR_FIX_4K_D0000_MSR 0x26a 52 #define MTRR_FIX_4K_D8000_MSR 0x26b 53 #define MTRR_FIX_4K_E0000_MSR 0x26c 54 #define MTRR_FIX_4K_E8000_MSR 0x26d 55 #define MTRR_FIX_4K_F0000_MSR 0x26e 56 #define MTRR_FIX_4K_F8000_MSR 0x26f 57 58 #define MTRR_FIX_TYPE(t) ((t << 24) | (t << 16) | (t << 8) | t) 59 60 #if !defined(__ASSEMBLY__) 61 62 /** 63 * Information about the previous MTRR state, set up by mtrr_open() 64 * 65 * @deftype: Previous value of MTRR_DEF_TYPE_MSR 66 * @enable_cache: true if cache was enabled 67 */ 68 struct mtrr_state { 69 uint64_t deftype; 70 bool enable_cache; 71 }; 72 73 /** 74 * struct mtrr - Information about a single MTRR 75 * 76 * @base: Base address and MTRR_BASE_TYPE_MASK 77 * @mask: Mask and MTRR_PHYS_MASK_VALID 78 */ 79 struct mtrr { 80 u64 base; 81 u64 mask; 82 }; 83 84 /** 85 * struct mtrr_info - Information about all MTRRs 86 * 87 * @mtrr: Information about each mtrr 88 */ 89 struct mtrr_info { 90 struct mtrr mtrr[MTRR_MAX_COUNT]; 91 }; 92 93 /** 94 * mtrr_open() - Prepare to adjust MTRRs 95 * 96 * Use mtrr_open() passing in a structure - this function will init it. Then 97 * when done, pass the same structure to mtrr_close() to re-enable MTRRs and 98 * possibly the cache. 99 * 100 * @state: Empty structure to pass in to hold settings 101 * @do_caches: true to disable caches before opening 102 */ 103 void mtrr_open(struct mtrr_state *state, bool do_caches); 104 105 /** 106 * mtrr_close() - Clean up after adjusting MTRRs, and enable them 107 * 108 * This uses the structure containing information returned from mtrr_open(). 109 * 110 * @state: Structure from mtrr_open() 111 * @state: true to restore cache state to that before mtrr_open() 112 */ 113 void mtrr_close(struct mtrr_state *state, bool do_caches); 114 115 /** 116 * mtrr_add_request() - Add a new MTRR request 117 * 118 * This adds a request for a memory region to be set up in a particular way. 119 * 120 * @type: Requested type (MTRR_TYPE_) 121 * @start: Start address 122 * @size: Size 123 * 124 * @return: 0 on success, non-zero on failure 125 */ 126 int mtrr_add_request(int type, uint64_t start, uint64_t size); 127 128 /** 129 * mtrr_commit() - set up the MTRR registers based on current requests 130 * 131 * This sets up MTRRs for the available DRAM and the requests received so far. 132 * It must be called with caches disabled. 133 * 134 * @do_caches: true if caches are currently on 135 * 136 * @return: 0 on success, non-zero on failure 137 */ 138 int mtrr_commit(bool do_caches); 139 140 /** 141 * mtrr_set_next_var() - set up a variable MTRR 142 * 143 * This finds the first free variable MTRR and sets to the given area 144 * 145 * @type: Requested type (MTRR_TYPE_) 146 * @start: Start address 147 * @size: Size 148 * @return 0 on success, -ENOSPC if there are no more MTRRs 149 */ 150 int mtrr_set_next_var(uint type, uint64_t base, uint64_t size); 151 152 /** 153 * mtrr_read_all() - Save all the MTRRs 154 * 155 * This reads all MTRRs from the boot CPU into a struct so they can be loaded 156 * onto other CPUs 157 * 158 * @info: Place to put the MTRR info 159 */ 160 void mtrr_read_all(struct mtrr_info *info); 161 162 /** 163 * mtrr_set_valid() - Set the valid flag for a selected MTRR and CPU(s) 164 * 165 * @cpu_select: Selected CPUs (either a CPU number or MP_SELECT_...) 166 * @reg: MTRR register to write (0-7) 167 * @valid: Valid flag to write 168 * @return 0 on success, -ve on error 169 */ 170 int mtrr_set_valid(int cpu_select, int reg, bool valid); 171 172 /** 173 * mtrr_set() - Set the base address and mask for a selected MTRR and CPU(s) 174 * 175 * @cpu_select: Selected CPUs (either a CPU number or MP_SELECT_...) 176 * @reg: MTRR register to write (0-7) 177 * @base: Base address and MTRR_BASE_TYPE_MASK 178 * @mask: Mask and MTRR_PHYS_MASK_VALID 179 * @return 0 on success, -ve on error 180 */ 181 int mtrr_set(int cpu_select, int reg, u64 base, u64 mask); 182 183 /** 184 * mtrr_get_var_count() - Get the number of variable MTRRs 185 * 186 * Some CPUs have more than 8 MTRRs. This function returns the actual number 187 * 188 * @return number of variable MTRRs 189 */ 190 int mtrr_get_var_count(void); 191 192 #endif 193 194 #if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0) 195 # error "CONFIG_XIP_ROM_SIZE is not a power of 2" 196 #endif 197 198 #if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE - 1)) != 0) 199 # error "CONFIG_CACHE_ROM_SIZE is not a power of 2" 200 #endif 201 202 #define CACHE_ROM_BASE (((1 << 20) - (CONFIG_CACHE_ROM_SIZE >> 12)) << 12) 203 204 #endif 205