1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
4 */
5
6 #include <asm/arch/psu_init_gpl.h>
7 #include <xil_io.h>
8
9 static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate,
10 u32 lane2_protocol, u32 lane2_rate,
11 u32 lane1_protocol, u32 lane1_rate,
12 u32 lane0_protocol, u32 lane0_rate);
13
psu_pll_init_data(void)14 static unsigned long psu_pll_init_data(void)
15 {
16 psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C82U);
17 psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00015A00U);
18 psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
19 psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
20 psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
21 mask_poll(0xFF5E0040, 0x00000002U);
22 psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
23 psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
24 psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
25 psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
26 psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
27 psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
28 psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
29 psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
30 mask_poll(0xFF5E0040, 0x00000001U);
31 psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
32 psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
33 psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
34 psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
35 psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
36 psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
37 psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
38 mask_poll(0xFD1A0044, 0x00000001U);
39 psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
40 psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
41 psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
42 psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00013F00U);
43 psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
44 psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
45 psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
46 mask_poll(0xFD1A0044, 0x00000002U);
47 psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
48 psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000200U);
49 psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
50 psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00015A00U);
51 psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
52 psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
53 psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
54 mask_poll(0xFD1A0044, 0x00000004U);
55 psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
56 psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
57
58 return 1;
59 }
60
psu_clock_init_data(void)61 static unsigned long psu_clock_init_data(void)
62 {
63 psu_mask_write(0xFF5E005C, 0x063F3F07U, 0x06010C00U);
64 psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
65 psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
66 psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
67 psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
68 psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
69 psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
70 psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
71 psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
72 psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
73 psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
74 psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
75 psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
76 psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
77 psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
78 psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
79 psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
80 psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
81 psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
82 psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
83 psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
84 psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
85 psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
86 psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
87 psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
88 psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
89 psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
90 psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
91 psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
92 psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
93 psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
94 psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
95 psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
96 psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
97
98 return 1;
99 }
100
psu_ddr_init_data(void)101 static unsigned long psu_ddr_init_data(void)
102 {
103 psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
104 psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040010U);
105 psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
106 psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
107 psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
108 psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
109 psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408210U);
110 psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
111 psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
112 psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
113 psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x007F80B8U);
114 psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
115 psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
116 psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
117 psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0040051FU);
118 psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020102U);
119 psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
120 psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002205U);
121 psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x07300301U);
122 psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00100200U);
123 psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
124 psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000006C0U);
125 psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x08190000U);
126 psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
127 psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
128 psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0F102311U);
129 psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040419U);
130 psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0608070CU);
131 psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
132 psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x08030409U);
133 psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
134 psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
135 psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
136 psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040D07U);
137 psu_mask_write(0xFD070124, 0x40070F3FU, 0x00020309U);
138 psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x1207010EU);
139 psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
140 psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
141 psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x0201908AU);
142 psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048B8208U);
143 psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
144 psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
145 psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
146 psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
147 psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
148 psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
149 psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000906U);
150 psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
151 psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
152 psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0909U);
153 psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U);
154 psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U);
155 psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
156 psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
157 psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x07070707U);
158 psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
159 psu_mask_write(0xFD070220, 0x00001F1FU, 0x00001F01U);
160 psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
161 psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
162 psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
163 psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x0600060CU);
164 psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
165 psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
166 psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
167 psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
168 psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
169 psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
170 psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
171 psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
172 psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
173 psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
174 psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
175 psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
176 psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
177 psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
178 psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
179 psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
180 psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
181 psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
182 psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
183 psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
184 psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
185 psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
186 psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
187 psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
188 psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
189 psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
190 psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
191 psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
192 psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
193 psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
194 psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
195 psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
196 psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
197 psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
198 psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
199 psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
200 psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
201 psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
202 psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
203 psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
204 psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
205 psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
206 psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
207 psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
208 psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
209 psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
210 psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
211 psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
212 psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
213 psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
214 psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
215 psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
216 psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
217 psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
218 psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
219 psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
220 psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
221 psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F0FC00U);
222 psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
223 psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
224 psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x41A20D10U);
225 psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xCD141275U);
226 psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
227 psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
228 psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
229 psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E3U);
230 psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
231 psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x07220F08U);
232 psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200008U);
233 psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0300U);
234 psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x83000800U);
235 psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01702B07U);
236 psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00310F08U);
237 psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000B0FU);
238 psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
239 psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
240 psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
241 psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000200U);
242 psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000630U);
243 psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
244 psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000010U);
245 psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
246 psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
247 psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
248 psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000819U);
249 psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
250 psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
251 psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
252 psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
253 psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
254 psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
255 psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
256 psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
257 psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
258 psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
259 psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
260 psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
261 psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
262 psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
263 psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
264 psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
265 psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
266 psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
267 psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
268 psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
269 psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
270 psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
271 psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
272 psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
273 psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008A8A58U);
274 psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
275 psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
276 psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
277 psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
278 psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
279 psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
280 psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
281 psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
282 psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09095555U);
283 psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
284 psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
285 psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
286 psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
287 psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
288 psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09095555U);
289 psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
290 psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
291 psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
292 psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
293 psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U);
294 psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09095555U);
295 psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
296 psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
297 psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
298 psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
299 psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U);
300 psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09095555U);
301 psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
302 psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
303 psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
304 psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
305 psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
306 psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
307 psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09095555U);
308 psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
309 psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
310 psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
311 psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
312 psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
313 psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
314 psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09095555U);
315 psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
316 psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
317 psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
318 psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
319 psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
320 psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
321 psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09095555U);
322 psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
323 psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
324 psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
325 psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
326 psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
327 psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
328 psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09095555U);
329 psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
330 psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
331 psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
332 psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
333 psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
334 psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
335 psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09095555U);
336 psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
337 psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
338 psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
339 psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
340 psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
341 psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
342 psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
343 psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
344 psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
345 psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
346 psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
347 psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
348 psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
349 psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
350 psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
351 psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
352 psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
353 psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
354 psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
355 psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
356 psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
357 psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
358 psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
359 psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
360 psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
361 psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
362 psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
363
364 return 1;
365 }
366
psu_ddr_qos_init_data(void)367 static unsigned long psu_ddr_qos_init_data(void)
368 {
369 psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
370 psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
371 psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
372 psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
373 psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
374 psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
375 psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
376 psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
377 psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
378 psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
379 psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
380 psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
381 psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
382 psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
383
384 return 1;
385 }
386
psu_mio_init_data(void)387 static unsigned long psu_mio_init_data(void)
388 {
389 psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
390 psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
391 psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
392 psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
393 psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
394 psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
395 psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
396 psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000002U);
397 psu_mask_write(0xFF180020, 0x000000FEU, 0x00000002U);
398 psu_mask_write(0xFF180024, 0x000000FEU, 0x00000002U);
399 psu_mask_write(0xFF180028, 0x000000FEU, 0x00000002U);
400 psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000002U);
401 psu_mask_write(0xFF180030, 0x000000FEU, 0x00000002U);
402 psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
403 psu_mask_write(0xFF180038, 0x000000FEU, 0x00000040U);
404 psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000040U);
405 psu_mask_write(0xFF180040, 0x000000FEU, 0x00000040U);
406 psu_mask_write(0xFF180044, 0x000000FEU, 0x00000040U);
407 psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
408 psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U);
409 psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U);
410 psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U);
411 psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U);
412 psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U);
413 psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U);
414 psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U);
415 psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U);
416 psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U);
417 psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U);
418 psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U);
419 psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U);
420 psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U);
421 psu_mask_write(0xFF180080, 0x000000FEU, 0x00000008U);
422 psu_mask_write(0xFF180084, 0x000000FEU, 0x00000008U);
423 psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
424 psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
425 psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
426 psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
427 psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
428 psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U);
429 psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
430 psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
431 psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
432 psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
433 psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
434 psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
435 psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
436 psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
437 psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
438 psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
439 psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
440 psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
441 psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
442 psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
443 psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
444 psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
445 psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
446 psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
447 psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
448 psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
449 psu_mask_write(0xFF180100, 0x000000FEU, 0x00000002U);
450 psu_mask_write(0xFF180104, 0x000000FEU, 0x00000002U);
451 psu_mask_write(0xFF180108, 0x000000FEU, 0x00000002U);
452 psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000002U);
453 psu_mask_write(0xFF180110, 0x000000FEU, 0x00000002U);
454 psu_mask_write(0xFF180114, 0x000000FEU, 0x00000002U);
455 psu_mask_write(0xFF180118, 0x000000FEU, 0x00000002U);
456 psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000002U);
457 psu_mask_write(0xFF180120, 0x000000FEU, 0x00000002U);
458 psu_mask_write(0xFF180124, 0x000000FEU, 0x00000002U);
459 psu_mask_write(0xFF180128, 0x000000FEU, 0x00000002U);
460 psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000002U);
461 psu_mask_write(0xFF180130, 0x000000FEU, 0x000000C0U);
462 psu_mask_write(0xFF180134, 0x000000FEU, 0x000000C0U);
463 psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x00040000U);
464 psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B02000U);
465 psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000FC0U);
466 psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
467 psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
468 psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
469 psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
470 psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
471 psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
472 psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
473 psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
474 psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
475 psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
476 psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
477 psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
478 psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
479 psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
480 psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
481 psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
482 psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
483 psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
484 psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
485
486 return 1;
487 }
488
psu_peripherals_pre_init_data(void)489 static unsigned long psu_peripherals_pre_init_data(void)
490 {
491 psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
492 psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U);
493
494 return 1;
495 }
496
psu_peripherals_init_data(void)497 static unsigned long psu_peripherals_init_data(void)
498 {
499 psu_mask_write(0xFD1A0100, 0x00008046U, 0x00000000U);
500 psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
501 psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
502 psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
503 psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
504 psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
505 psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
506 psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
507 psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
508 psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U);
509 psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
510 psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
511 psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
512 psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
513 psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
514 psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
515 psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
516 psu_mask_write(0xFF000034, 0x000000FFU, 0x00000006U);
517 psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000007CU);
518 psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
519 psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
520 psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
521 psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
522 psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
523 psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
524 psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
525 psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U);
526 psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
527 psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
528
529 mask_delay(1);
530 psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
531
532 mask_delay(5);
533 psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
534
535 return 1;
536 }
537
psu_serdes_init_data(void)538 static unsigned long psu_serdes_init_data(void)
539 {
540 psu_mask_write(0xFD410008, 0x0000001FU, 0x00000008U);
541 psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000FU);
542 psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
543 psu_mask_write(0xFD40286C, 0x00000080U, 0x00000080U);
544 psu_mask_write(0xFD40A094, 0x00000010U, 0x00000010U);
545 psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000038U);
546 psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
547 psu_mask_write(0xFD40E368, 0x000000FFU, 0x000000E0U);
548 psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
549 psu_mask_write(0xFD40A370, 0x000000FFU, 0x000000F4U);
550 psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000031U);
551 psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
552 psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
553 psu_mask_write(0xFD40E370, 0x000000FFU, 0x000000C9U);
554 psu_mask_write(0xFD40E374, 0x000000FFU, 0x000000D2U);
555 psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000001U);
556 psu_mask_write(0xFD40E37C, 0x000000B3U, 0x000000B0U);
557 psu_mask_write(0xFD40906C, 0x00000003U, 0x00000003U);
558 psu_mask_write(0xFD4080F4, 0x00000003U, 0x00000003U);
559 psu_mask_write(0xFD40E360, 0x00000040U, 0x00000040U);
560 psu_mask_write(0xFD40D06C, 0x0000000FU, 0x0000000FU);
561 psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x0000000BU);
562 psu_mask_write(0xFD4090CC, 0x00000020U, 0x00000020U);
563 psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
564 psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
565 psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
566 psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
567 psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
568 psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
569 psu_mask_write(0xFD40989C, 0x00000080U, 0x00000080U);
570 psu_mask_write(0xFD4098F8, 0x000000FFU, 0x0000001AU);
571 psu_mask_write(0xFD4098FC, 0x000000FFU, 0x0000001AU);
572 psu_mask_write(0xFD409990, 0x000000FFU, 0x00000010U);
573 psu_mask_write(0xFD409924, 0x000000FFU, 0x000000FEU);
574 psu_mask_write(0xFD409928, 0x000000FFU, 0x00000000U);
575 psu_mask_write(0xFD409900, 0x000000FFU, 0x0000001AU);
576 psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000000U);
577 psu_mask_write(0xFD409980, 0x000000FFU, 0x000000FFU);
578 psu_mask_write(0xFD409914, 0x000000FFU, 0x000000F7U);
579 psu_mask_write(0xFD409918, 0x00000001U, 0x00000001U);
580 psu_mask_write(0xFD409940, 0x000000FFU, 0x000000F7U);
581 psu_mask_write(0xFD409944, 0x00000001U, 0x00000001U);
582 psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
583 psu_mask_write(0xFD40D89C, 0x00000080U, 0x00000080U);
584 psu_mask_write(0xFD40D8F8, 0x000000FFU, 0x0000007DU);
585 psu_mask_write(0xFD40D8FC, 0x000000FFU, 0x0000007DU);
586 psu_mask_write(0xFD40D990, 0x000000FFU, 0x00000001U);
587 psu_mask_write(0xFD40D924, 0x000000FFU, 0x0000009CU);
588 psu_mask_write(0xFD40D928, 0x000000FFU, 0x00000039U);
589 psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
590 psu_mask_write(0xFD40D900, 0x000000FFU, 0x0000007DU);
591 psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000064U);
592 psu_mask_write(0xFD40D980, 0x000000FFU, 0x000000FFU);
593 psu_mask_write(0xFD40D914, 0x000000FFU, 0x000000F7U);
594 psu_mask_write(0xFD40D918, 0x00000001U, 0x00000001U);
595 psu_mask_write(0xFD40D940, 0x000000FFU, 0x000000F7U);
596 psu_mask_write(0xFD40D944, 0x00000001U, 0x00000001U);
597 psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
598 psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
599 psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
600 psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
601 psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
602 psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
603 psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
604 psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
605 psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
606 psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
607 psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
608 psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
609 psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
610 psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
611 psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
612 psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
613 psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
614 psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
615 psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
616 psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
617 psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
618 psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
619 psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
620 psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
621 psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
622
623 serdes_illcalib(2, 3, 3, 0, 0, 0, 0, 0);
624 psu_mask_write(0xFD410014, 0x00000077U, 0x00000023U);
625 psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
626 psu_mask_write(0xFD40DC14, 0x000000FFU, 0x000000E6U);
627 psu_mask_write(0xFD40DC40, 0x0000001FU, 0x0000000CU);
628 psu_mask_write(0xFD40D94C, 0x00000020U, 0x00000020U);
629 psu_mask_write(0xFD40D950, 0x00000007U, 0x00000006U);
630 psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000001U);
631
632 return 1;
633 }
634
psu_resetout_init_data(void)635 static unsigned long psu_resetout_init_data(void)
636 {
637 psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
638 psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
639 psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
640 psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
641 psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000000U);
642 psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000003U);
643 psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
644 psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
645 psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
646 psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
647 psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
648 psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
649 mask_poll(0xFD40A3E4, 0x00000010U);
650 mask_poll(0xFD40E3E4, 0x00000010U);
651 psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
652 psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
653 psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
654 psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
655
656 return 1;
657 }
658
psu_resetin_init_data(void)659 static unsigned long psu_resetin_init_data(void)
660 {
661 psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
662 psu_mask_write(0xFF5E0230, 0x00000008U, 0x00000008U);
663 psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
664
665 return 1;
666 }
667
psu_afi_config(void)668 static unsigned long psu_afi_config(void)
669 {
670 psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
671 psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
672 psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U);
673 psu_mask_write(0xFD360000, 0x00000003U, 0x00000002U);
674 psu_mask_write(0xFD370000, 0x00000003U, 0x00000002U);
675 psu_mask_write(0xFD360014, 0x00000003U, 0x00000002U);
676 psu_mask_write(0xFD370014, 0x00000003U, 0x00000002U);
677
678 return 1;
679 }
680
psu_ddr_phybringup_data(void)681 static unsigned long psu_ddr_phybringup_data(void)
682 {
683 unsigned int regval = 0;
684 unsigned int pll_retry = 10;
685 unsigned int pll_locked = 0;
686 int cur_R006_tREFPRD;
687
688 while ((pll_retry > 0) && (!pll_locked)) {
689 Xil_Out32(0xFD080004, 0x00040010);
690 Xil_Out32(0xFD080004, 0x00040011);
691
692 while ((Xil_In32(0xFD080030) & 0x1) != 1)
693 ;
694 pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
695 >> 31;
696 pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
697 >> 16;
698 pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
699 pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
700 >> 16;
701 pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
702 >> 16;
703 pll_retry--;
704 }
705 Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
706 if (!pll_locked)
707 return 0;
708
709 Xil_Out32(0xFD080004U, 0x00040063U);
710
711 while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
712 ;
713 prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
714
715 while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
716 ;
717 Xil_Out32(0xFD0701B0U, 0x00000001U);
718 Xil_Out32(0xFD070320U, 0x00000001U);
719 while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
720 ;
721 prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
722 Xil_Out32(0xFD080004, 0x0004FE01);
723 regval = Xil_In32(0xFD080030);
724 while (regval != 0x80000FFF)
725 regval = Xil_In32(0xFD080030);
726 regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
727 if (regval != 0)
728 return 0;
729
730 Xil_Out32(0xFD080200U, 0x100091C7U);
731
732 cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
733 prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
734
735 prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
736 prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
737 prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
738 prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
739 prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
740 prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
741
742 Xil_Out32(0xFD080004, 0x00060001);
743 regval = Xil_In32(0xFD080030);
744 while ((regval & 0x80004001) != 0x80004001)
745 regval = Xil_In32(0xFD080030);
746
747 regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
748 if (regval != 0)
749 return 0;
750
751 prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
752 prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
753 prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
754 prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
755 prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
756 prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
757
758 Xil_Out32(0xFD080200U, 0x800091C7U);
759 prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
760
761 Xil_Out32(0xFD080004, 0x0000C001);
762 regval = Xil_In32(0xFD080030);
763 while ((regval & 0x80000C01) != 0x80000C01)
764 regval = Xil_In32(0xFD080030);
765
766 Xil_Out32(0xFD070180U, 0x01000040U);
767 Xil_Out32(0xFD070060U, 0x00000000U);
768 prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
769
770 return 1;
771 }
772
serdes_rst_seq(u32 lane3_protocol,u32 lane3_rate,u32 lane2_protocol,u32 lane2_rate,u32 lane1_protocol,u32 lane1_rate,u32 lane0_protocol,u32 lane0_rate)773 static int serdes_rst_seq(u32 lane3_protocol, u32 lane3_rate,
774 u32 lane2_protocol, u32 lane2_rate,
775 u32 lane1_protocol, u32 lane1_rate,
776 u32 lane0_protocol, u32 lane0_rate)
777 {
778 Xil_Out32(0xFD410098, 0x00000000);
779 Xil_Out32(0xFD401010, 0x00000040);
780 Xil_Out32(0xFD405010, 0x00000040);
781 Xil_Out32(0xFD409010, 0x00000040);
782 Xil_Out32(0xFD40D010, 0x00000040);
783 Xil_Out32(0xFD402084, 0x00000080);
784 Xil_Out32(0xFD406084, 0x00000080);
785 Xil_Out32(0xFD40A084, 0x00000080);
786 Xil_Out32(0xFD40E084, 0x00000080);
787 Xil_Out32(0xFD410098, 0x00000004);
788 mask_delay(50);
789 if (lane0_rate == 1)
790 Xil_Out32(0xFD410098, 0x0000000E);
791 Xil_Out32(0xFD410098, 0x00000006);
792 if (lane0_rate == 1) {
793 Xil_Out32(0xFD40000C, 0x00000004);
794 Xil_Out32(0xFD40400C, 0x00000004);
795 Xil_Out32(0xFD40800C, 0x00000004);
796 Xil_Out32(0xFD40C00C, 0x00000004);
797 Xil_Out32(0xFD410098, 0x00000007);
798 mask_delay(400);
799 Xil_Out32(0xFD40000C, 0x0000000C);
800 Xil_Out32(0xFD40400C, 0x0000000C);
801 Xil_Out32(0xFD40800C, 0x0000000C);
802 Xil_Out32(0xFD40C00C, 0x0000000C);
803 mask_delay(15);
804 Xil_Out32(0xFD410098, 0x0000000F);
805 mask_delay(100);
806 }
807 if (lane0_protocol != 0)
808 mask_poll(0xFD4023E4, 0x00000010U);
809 if (lane1_protocol != 0)
810 mask_poll(0xFD4063E4, 0x00000010U);
811 if (lane2_protocol != 0)
812 mask_poll(0xFD40A3E4, 0x00000010U);
813 if (lane3_protocol != 0)
814 mask_poll(0xFD40E3E4, 0x00000010U);
815 mask_delay(50);
816 Xil_Out32(0xFD401010, 0x000000C0);
817 Xil_Out32(0xFD405010, 0x000000C0);
818 Xil_Out32(0xFD409010, 0x000000C0);
819 Xil_Out32(0xFD40D010, 0x000000C0);
820 Xil_Out32(0xFD401010, 0x00000080);
821 Xil_Out32(0xFD405010, 0x00000080);
822 Xil_Out32(0xFD409010, 0x00000080);
823 Xil_Out32(0xFD40D010, 0x00000080);
824
825 Xil_Out32(0xFD402084, 0x000000C0);
826 Xil_Out32(0xFD406084, 0x000000C0);
827 Xil_Out32(0xFD40A084, 0x000000C0);
828 Xil_Out32(0xFD40E084, 0x000000C0);
829 mask_delay(50);
830 Xil_Out32(0xFD402084, 0x00000080);
831 Xil_Out32(0xFD406084, 0x00000080);
832 Xil_Out32(0xFD40A084, 0x00000080);
833 Xil_Out32(0xFD40E084, 0x00000080);
834 mask_delay(50);
835 Xil_Out32(0xFD401010, 0x00000000);
836 Xil_Out32(0xFD405010, 0x00000000);
837 Xil_Out32(0xFD409010, 0x00000000);
838 Xil_Out32(0xFD40D010, 0x00000000);
839 Xil_Out32(0xFD402084, 0x00000000);
840 Xil_Out32(0xFD406084, 0x00000000);
841 Xil_Out32(0xFD40A084, 0x00000000);
842 Xil_Out32(0xFD40E084, 0x00000000);
843 mask_delay(500);
844 return 1;
845 }
846
serdes_bist_static_settings(u32 lane_active)847 static int serdes_bist_static_settings(u32 lane_active)
848 {
849 if (lane_active == 0) {
850 Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F));
851 Xil_Out32(0xFD403068, 0x1);
852 Xil_Out32(0xFD40306C, 0x1);
853 Xil_Out32(0xFD4010AC, 0x0020);
854 Xil_Out32(0xFD403008, 0x0);
855 Xil_Out32(0xFD40300C, 0xF4);
856 Xil_Out32(0xFD403010, 0x0);
857 Xil_Out32(0xFD403014, 0x0);
858 Xil_Out32(0xFD403018, 0x00);
859 Xil_Out32(0xFD40301C, 0xFB);
860 Xil_Out32(0xFD403020, 0xFF);
861 Xil_Out32(0xFD403024, 0x0);
862 Xil_Out32(0xFD403028, 0x00);
863 Xil_Out32(0xFD40302C, 0x00);
864 Xil_Out32(0xFD403030, 0x4A);
865 Xil_Out32(0xFD403034, 0x4A);
866 Xil_Out32(0xFD403038, 0x4A);
867 Xil_Out32(0xFD40303C, 0x4A);
868 Xil_Out32(0xFD403040, 0x0);
869 Xil_Out32(0xFD403044, 0x14);
870 Xil_Out32(0xFD403048, 0x02);
871 Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F));
872 }
873 if (lane_active == 1) {
874 Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F));
875 Xil_Out32(0xFD407068, 0x1);
876 Xil_Out32(0xFD40706C, 0x1);
877 Xil_Out32(0xFD4050AC, 0x0020);
878 Xil_Out32(0xFD407008, 0x0);
879 Xil_Out32(0xFD40700C, 0xF4);
880 Xil_Out32(0xFD407010, 0x0);
881 Xil_Out32(0xFD407014, 0x0);
882 Xil_Out32(0xFD407018, 0x00);
883 Xil_Out32(0xFD40701C, 0xFB);
884 Xil_Out32(0xFD407020, 0xFF);
885 Xil_Out32(0xFD407024, 0x0);
886 Xil_Out32(0xFD407028, 0x00);
887 Xil_Out32(0xFD40702C, 0x00);
888 Xil_Out32(0xFD407030, 0x4A);
889 Xil_Out32(0xFD407034, 0x4A);
890 Xil_Out32(0xFD407038, 0x4A);
891 Xil_Out32(0xFD40703C, 0x4A);
892 Xil_Out32(0xFD407040, 0x0);
893 Xil_Out32(0xFD407044, 0x14);
894 Xil_Out32(0xFD407048, 0x02);
895 Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F));
896 }
897
898 if (lane_active == 2) {
899 Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F));
900 Xil_Out32(0xFD40B068, 0x1);
901 Xil_Out32(0xFD40B06C, 0x1);
902 Xil_Out32(0xFD4090AC, 0x0020);
903 Xil_Out32(0xFD40B008, 0x0);
904 Xil_Out32(0xFD40B00C, 0xF4);
905 Xil_Out32(0xFD40B010, 0x0);
906 Xil_Out32(0xFD40B014, 0x0);
907 Xil_Out32(0xFD40B018, 0x00);
908 Xil_Out32(0xFD40B01C, 0xFB);
909 Xil_Out32(0xFD40B020, 0xFF);
910 Xil_Out32(0xFD40B024, 0x0);
911 Xil_Out32(0xFD40B028, 0x00);
912 Xil_Out32(0xFD40B02C, 0x00);
913 Xil_Out32(0xFD40B030, 0x4A);
914 Xil_Out32(0xFD40B034, 0x4A);
915 Xil_Out32(0xFD40B038, 0x4A);
916 Xil_Out32(0xFD40B03C, 0x4A);
917 Xil_Out32(0xFD40B040, 0x0);
918 Xil_Out32(0xFD40B044, 0x14);
919 Xil_Out32(0xFD40B048, 0x02);
920 Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F));
921 }
922
923 if (lane_active == 3) {
924 Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F));
925 Xil_Out32(0xFD40F068, 0x1);
926 Xil_Out32(0xFD40F06C, 0x1);
927 Xil_Out32(0xFD40D0AC, 0x0020);
928 Xil_Out32(0xFD40F008, 0x0);
929 Xil_Out32(0xFD40F00C, 0xF4);
930 Xil_Out32(0xFD40F010, 0x0);
931 Xil_Out32(0xFD40F014, 0x0);
932 Xil_Out32(0xFD40F018, 0x00);
933 Xil_Out32(0xFD40F01C, 0xFB);
934 Xil_Out32(0xFD40F020, 0xFF);
935 Xil_Out32(0xFD40F024, 0x0);
936 Xil_Out32(0xFD40F028, 0x00);
937 Xil_Out32(0xFD40F02C, 0x00);
938 Xil_Out32(0xFD40F030, 0x4A);
939 Xil_Out32(0xFD40F034, 0x4A);
940 Xil_Out32(0xFD40F038, 0x4A);
941 Xil_Out32(0xFD40F03C, 0x4A);
942 Xil_Out32(0xFD40F040, 0x0);
943 Xil_Out32(0xFD40F044, 0x14);
944 Xil_Out32(0xFD40F048, 0x02);
945 Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F));
946 }
947 return 1;
948 }
949
serdes_bist_run(u32 lane_active)950 static int serdes_bist_run(u32 lane_active)
951 {
952 if (lane_active == 0) {
953 psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U);
954 psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U);
955 psu_mask_write(0xFD410038, 0x00000007U, 0x00000001U);
956 Xil_Out32(0xFD4010AC, 0x0020);
957 Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) | 0x1));
958 }
959 if (lane_active == 1) {
960 psu_mask_write(0xFD410044, 0x0000000CU, 0x00000000U);
961 psu_mask_write(0xFD410040, 0x0000000CU, 0x00000000U);
962 psu_mask_write(0xFD410038, 0x00000070U, 0x00000010U);
963 Xil_Out32(0xFD4050AC, 0x0020);
964 Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) | 0x1));
965 }
966 if (lane_active == 2) {
967 psu_mask_write(0xFD410044, 0x00000030U, 0x00000000U);
968 psu_mask_write(0xFD410040, 0x00000030U, 0x00000000U);
969 psu_mask_write(0xFD41003C, 0x00000007U, 0x00000001U);
970 Xil_Out32(0xFD4090AC, 0x0020);
971 Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) | 0x1));
972 }
973 if (lane_active == 3) {
974 psu_mask_write(0xFD410040, 0x000000C0U, 0x00000000U);
975 psu_mask_write(0xFD410044, 0x000000C0U, 0x00000000U);
976 psu_mask_write(0xFD41003C, 0x00000070U, 0x00000010U);
977 Xil_Out32(0xFD40D0AC, 0x0020);
978 Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) | 0x1));
979 }
980 mask_delay(100);
981 return 1;
982 }
983
serdes_bist_result(u32 lane_active)984 static int serdes_bist_result(u32 lane_active)
985 {
986 u32 pkt_cnt_l0, pkt_cnt_h0, err_cnt_l0, err_cnt_h0;
987
988 if (lane_active == 0) {
989 pkt_cnt_l0 = Xil_In32(0xFD40304C);
990 pkt_cnt_h0 = Xil_In32(0xFD403050);
991 err_cnt_l0 = Xil_In32(0xFD403054);
992 err_cnt_h0 = Xil_In32(0xFD403058);
993 }
994 if (lane_active == 1) {
995 pkt_cnt_l0 = Xil_In32(0xFD40704C);
996 pkt_cnt_h0 = Xil_In32(0xFD407050);
997 err_cnt_l0 = Xil_In32(0xFD407054);
998 err_cnt_h0 = Xil_In32(0xFD407058);
999 }
1000 if (lane_active == 2) {
1001 pkt_cnt_l0 = Xil_In32(0xFD40B04C);
1002 pkt_cnt_h0 = Xil_In32(0xFD40B050);
1003 err_cnt_l0 = Xil_In32(0xFD40B054);
1004 err_cnt_h0 = Xil_In32(0xFD40B058);
1005 }
1006 if (lane_active == 3) {
1007 pkt_cnt_l0 = Xil_In32(0xFD40F04C);
1008 pkt_cnt_h0 = Xil_In32(0xFD40F050);
1009 err_cnt_l0 = Xil_In32(0xFD40F054);
1010 err_cnt_h0 = Xil_In32(0xFD40F058);
1011 }
1012 if (lane_active == 0)
1013 Xil_Out32(0xFD403004, 0x0);
1014 if (lane_active == 1)
1015 Xil_Out32(0xFD407004, 0x0);
1016 if (lane_active == 2)
1017 Xil_Out32(0xFD40B004, 0x0);
1018 if (lane_active == 3)
1019 Xil_Out32(0xFD40F004, 0x0);
1020 if (err_cnt_l0 > 0 || err_cnt_h0 > 0 ||
1021 (pkt_cnt_l0 == 0 && pkt_cnt_h0 == 0))
1022 return 0;
1023 return 1;
1024 }
1025
serdes_illcalib_pcie_gen1(u32 lane3_protocol,u32 lane3_rate,u32 lane2_protocol,u32 lane2_rate,u32 lane1_protocol,u32 lane1_rate,u32 lane0_protocol,u32 lane0_rate,u32 gen2_calib)1026 static int serdes_illcalib_pcie_gen1(u32 lane3_protocol, u32 lane3_rate,
1027 u32 lane2_protocol, u32 lane2_rate,
1028 u32 lane1_protocol, u32 lane1_rate,
1029 u32 lane0_protocol, u32 lane0_rate,
1030 u32 gen2_calib)
1031 {
1032 u64 tempbistresult;
1033 u32 currbistresult[4];
1034 u32 prevbistresult[4];
1035 u32 itercount = 0;
1036 u32 ill12_val[4], ill1_val[4];
1037 u32 loop = 0;
1038 u32 iterresult[8];
1039 u32 meancount[4];
1040 u32 bistpasscount[4];
1041 u32 meancountalt[4];
1042 u32 meancountalt_bistpasscount[4];
1043 u32 lane0_active;
1044 u32 lane1_active;
1045 u32 lane2_active;
1046 u32 lane3_active;
1047
1048 lane0_active = (lane0_protocol == 1);
1049 lane1_active = (lane1_protocol == 1);
1050 lane2_active = (lane2_protocol == 1);
1051 lane3_active = (lane3_protocol == 1);
1052 for (loop = 0; loop <= 3; loop++) {
1053 iterresult[loop] = 0;
1054 iterresult[loop + 4] = 0;
1055 meancountalt[loop] = 0;
1056 meancountalt_bistpasscount[loop] = 0;
1057 meancount[loop] = 0;
1058 prevbistresult[loop] = 0;
1059 bistpasscount[loop] = 0;
1060 }
1061 itercount = 0;
1062 if (lane0_active)
1063 serdes_bist_static_settings(0);
1064 if (lane1_active)
1065 serdes_bist_static_settings(1);
1066 if (lane2_active)
1067 serdes_bist_static_settings(2);
1068 if (lane3_active)
1069 serdes_bist_static_settings(3);
1070 do {
1071 if (gen2_calib != 1) {
1072 if (lane0_active == 1)
1073 ill1_val[0] = ((0x04 + itercount * 8) % 0x100);
1074 if (lane0_active == 1)
1075 ill12_val[0] =
1076 ((0x04 + itercount * 8) >=
1077 0x100) ? 0x10 : 0x00;
1078 if (lane1_active == 1)
1079 ill1_val[1] = ((0x04 + itercount * 8) % 0x100);
1080 if (lane1_active == 1)
1081 ill12_val[1] =
1082 ((0x04 + itercount * 8) >=
1083 0x100) ? 0x10 : 0x00;
1084 if (lane2_active == 1)
1085 ill1_val[2] = ((0x04 + itercount * 8) % 0x100);
1086 if (lane2_active == 1)
1087 ill12_val[2] =
1088 ((0x04 + itercount * 8) >=
1089 0x100) ? 0x10 : 0x00;
1090 if (lane3_active == 1)
1091 ill1_val[3] = ((0x04 + itercount * 8) % 0x100);
1092 if (lane3_active == 1)
1093 ill12_val[3] =
1094 ((0x04 + itercount * 8) >=
1095 0x100) ? 0x10 : 0x00;
1096
1097 if (lane0_active == 1)
1098 Xil_Out32(0xFD401924, ill1_val[0]);
1099 if (lane0_active == 1)
1100 psu_mask_write(0xFD401990, 0x000000F0U,
1101 ill12_val[0]);
1102 if (lane1_active == 1)
1103 Xil_Out32(0xFD405924, ill1_val[1]);
1104 if (lane1_active == 1)
1105 psu_mask_write(0xFD405990, 0x000000F0U,
1106 ill12_val[1]);
1107 if (lane2_active == 1)
1108 Xil_Out32(0xFD409924, ill1_val[2]);
1109 if (lane2_active == 1)
1110 psu_mask_write(0xFD409990, 0x000000F0U,
1111 ill12_val[2]);
1112 if (lane3_active == 1)
1113 Xil_Out32(0xFD40D924, ill1_val[3]);
1114 if (lane3_active == 1)
1115 psu_mask_write(0xFD40D990, 0x000000F0U,
1116 ill12_val[3]);
1117 }
1118 if (gen2_calib == 1) {
1119 if (lane0_active == 1)
1120 ill1_val[0] = ((0x104 + itercount * 8) % 0x100);
1121 if (lane0_active == 1)
1122 ill12_val[0] =
1123 ((0x104 + itercount * 8) >=
1124 0x200) ? 0x02 : 0x01;
1125 if (lane1_active == 1)
1126 ill1_val[1] = ((0x104 + itercount * 8) % 0x100);
1127 if (lane1_active == 1)
1128 ill12_val[1] =
1129 ((0x104 + itercount * 8) >=
1130 0x200) ? 0x02 : 0x01;
1131 if (lane2_active == 1)
1132 ill1_val[2] = ((0x104 + itercount * 8) % 0x100);
1133 if (lane2_active == 1)
1134 ill12_val[2] =
1135 ((0x104 + itercount * 8) >=
1136 0x200) ? 0x02 : 0x01;
1137 if (lane3_active == 1)
1138 ill1_val[3] = ((0x104 + itercount * 8) % 0x100);
1139 if (lane3_active == 1)
1140 ill12_val[3] =
1141 ((0x104 + itercount * 8) >=
1142 0x200) ? 0x02 : 0x01;
1143
1144 if (lane0_active == 1)
1145 Xil_Out32(0xFD401928, ill1_val[0]);
1146 if (lane0_active == 1)
1147 psu_mask_write(0xFD401990, 0x0000000FU,
1148 ill12_val[0]);
1149 if (lane1_active == 1)
1150 Xil_Out32(0xFD405928, ill1_val[1]);
1151 if (lane1_active == 1)
1152 psu_mask_write(0xFD405990, 0x0000000FU,
1153 ill12_val[1]);
1154 if (lane2_active == 1)
1155 Xil_Out32(0xFD409928, ill1_val[2]);
1156 if (lane2_active == 1)
1157 psu_mask_write(0xFD409990, 0x0000000FU,
1158 ill12_val[2]);
1159 if (lane3_active == 1)
1160 Xil_Out32(0xFD40D928, ill1_val[3]);
1161 if (lane3_active == 1)
1162 psu_mask_write(0xFD40D990, 0x0000000FU,
1163 ill12_val[3]);
1164 }
1165
1166 if (lane0_active == 1)
1167 psu_mask_write(0xFD401018, 0x00000030U, 0x00000010U);
1168 if (lane1_active == 1)
1169 psu_mask_write(0xFD405018, 0x00000030U, 0x00000010U);
1170 if (lane2_active == 1)
1171 psu_mask_write(0xFD409018, 0x00000030U, 0x00000010U);
1172 if (lane3_active == 1)
1173 psu_mask_write(0xFD40D018, 0x00000030U, 0x00000010U);
1174 if (lane0_active == 1)
1175 currbistresult[0] = 0;
1176 if (lane1_active == 1)
1177 currbistresult[1] = 0;
1178 if (lane2_active == 1)
1179 currbistresult[2] = 0;
1180 if (lane3_active == 1)
1181 currbistresult[3] = 0;
1182 serdes_rst_seq(lane3_protocol, lane3_rate, lane2_protocol,
1183 lane2_rate, lane1_protocol, lane1_rate,
1184 lane0_protocol, lane0_rate);
1185 if (lane3_active == 1)
1186 serdes_bist_run(3);
1187 if (lane2_active == 1)
1188 serdes_bist_run(2);
1189 if (lane1_active == 1)
1190 serdes_bist_run(1);
1191 if (lane0_active == 1)
1192 serdes_bist_run(0);
1193 tempbistresult = 0;
1194 if (lane3_active == 1)
1195 tempbistresult = tempbistresult | serdes_bist_result(3);
1196 tempbistresult = tempbistresult << 1;
1197 if (lane2_active == 1)
1198 tempbistresult = tempbistresult | serdes_bist_result(2);
1199 tempbistresult = tempbistresult << 1;
1200 if (lane1_active == 1)
1201 tempbistresult = tempbistresult | serdes_bist_result(1);
1202 tempbistresult = tempbistresult << 1;
1203 if (lane0_active == 1)
1204 tempbistresult = tempbistresult | serdes_bist_result(0);
1205 Xil_Out32(0xFD410098, 0x0);
1206 Xil_Out32(0xFD410098, 0x2);
1207
1208 if (itercount < 32) {
1209 iterresult[0] =
1210 ((iterresult[0] << 1) |
1211 ((tempbistresult & 0x1) == 0x1));
1212 iterresult[1] =
1213 ((iterresult[1] << 1) |
1214 ((tempbistresult & 0x2) == 0x2));
1215 iterresult[2] =
1216 ((iterresult[2] << 1) |
1217 ((tempbistresult & 0x4) == 0x4));
1218 iterresult[3] =
1219 ((iterresult[3] << 1) |
1220 ((tempbistresult & 0x8) == 0x8));
1221 } else {
1222 iterresult[4] =
1223 ((iterresult[4] << 1) |
1224 ((tempbistresult & 0x1) == 0x1));
1225 iterresult[5] =
1226 ((iterresult[5] << 1) |
1227 ((tempbistresult & 0x2) == 0x2));
1228 iterresult[6] =
1229 ((iterresult[6] << 1) |
1230 ((tempbistresult & 0x4) == 0x4));
1231 iterresult[7] =
1232 ((iterresult[7] << 1) |
1233 ((tempbistresult & 0x8) == 0x8));
1234 }
1235 currbistresult[0] =
1236 currbistresult[0] | ((tempbistresult & 0x1) == 1);
1237 currbistresult[1] =
1238 currbistresult[1] | ((tempbistresult & 0x2) == 0x2);
1239 currbistresult[2] =
1240 currbistresult[2] | ((tempbistresult & 0x4) == 0x4);
1241 currbistresult[3] =
1242 currbistresult[3] | ((tempbistresult & 0x8) == 0x8);
1243
1244 for (loop = 0; loop <= 3; loop++) {
1245 if (currbistresult[loop] == 1 && prevbistresult[loop] == 1)
1246 bistpasscount[loop] = bistpasscount[loop] + 1;
1247 if (bistpasscount[loop] < 4 &&
1248 currbistresult[loop] == 0 && itercount > 2) {
1249 if (meancountalt_bistpasscount[loop] <
1250 bistpasscount[loop]) {
1251 meancountalt_bistpasscount[loop] =
1252 bistpasscount[loop];
1253 meancountalt[loop] =
1254 ((itercount - 1) -
1255 ((bistpasscount[loop] + 1) / 2));
1256 }
1257 bistpasscount[loop] = 0;
1258 }
1259 if (meancount[loop] == 0 && bistpasscount[loop] >= 4 &&
1260 (currbistresult[loop] == 0 || itercount == 63) &&
1261 prevbistresult[loop] == 1)
1262 meancount[loop] =
1263 (itercount - 1) -
1264 ((bistpasscount[loop] + 1) / 2);
1265 prevbistresult[loop] = currbistresult[loop];
1266 }
1267 } while (++itercount < 64);
1268
1269 for (loop = 0; loop <= 3; loop++) {
1270 if (lane0_active == 0 && loop == 0)
1271 continue;
1272 if (lane1_active == 0 && loop == 1)
1273 continue;
1274 if (lane2_active == 0 && loop == 2)
1275 continue;
1276 if (lane3_active == 0 && loop == 3)
1277 continue;
1278
1279 if (meancount[loop] == 0)
1280 meancount[loop] = meancountalt[loop];
1281
1282 if (gen2_calib != 1) {
1283 ill1_val[loop] = ((0x04 + meancount[loop] * 8) % 0x100);
1284 ill12_val[loop] =
1285 ((0x04 + meancount[loop] * 8) >=
1286 0x100) ? 0x10 : 0x00;
1287 Xil_Out32(0xFFFE0000 + loop * 4, iterresult[loop]);
1288 Xil_Out32(0xFFFE0010 + loop * 4, iterresult[loop + 4]);
1289 Xil_Out32(0xFFFE0020 + loop * 4, bistpasscount[loop]);
1290 Xil_Out32(0xFFFE0030 + loop * 4, meancount[loop]);
1291 }
1292 if (gen2_calib == 1) {
1293 ill1_val[loop] =
1294 ((0x104 + meancount[loop] * 8) % 0x100);
1295 ill12_val[loop] =
1296 ((0x104 + meancount[loop] * 8) >=
1297 0x200) ? 0x02 : 0x01;
1298 Xil_Out32(0xFFFE0040 + loop * 4, iterresult[loop]);
1299 Xil_Out32(0xFFFE0050 + loop * 4, iterresult[loop + 4]);
1300 Xil_Out32(0xFFFE0060 + loop * 4, bistpasscount[loop]);
1301 Xil_Out32(0xFFFE0070 + loop * 4, meancount[loop]);
1302 }
1303 }
1304 if (gen2_calib != 1) {
1305 if (lane0_active == 1)
1306 Xil_Out32(0xFD401924, ill1_val[0]);
1307 if (lane0_active == 1)
1308 psu_mask_write(0xFD401990, 0x000000F0U, ill12_val[0]);
1309 if (lane1_active == 1)
1310 Xil_Out32(0xFD405924, ill1_val[1]);
1311 if (lane1_active == 1)
1312 psu_mask_write(0xFD405990, 0x000000F0U, ill12_val[1]);
1313 if (lane2_active == 1)
1314 Xil_Out32(0xFD409924, ill1_val[2]);
1315 if (lane2_active == 1)
1316 psu_mask_write(0xFD409990, 0x000000F0U, ill12_val[2]);
1317 if (lane3_active == 1)
1318 Xil_Out32(0xFD40D924, ill1_val[3]);
1319 if (lane3_active == 1)
1320 psu_mask_write(0xFD40D990, 0x000000F0U, ill12_val[3]);
1321 }
1322 if (gen2_calib == 1) {
1323 if (lane0_active == 1)
1324 Xil_Out32(0xFD401928, ill1_val[0]);
1325 if (lane0_active == 1)
1326 psu_mask_write(0xFD401990, 0x0000000FU, ill12_val[0]);
1327 if (lane1_active == 1)
1328 Xil_Out32(0xFD405928, ill1_val[1]);
1329 if (lane1_active == 1)
1330 psu_mask_write(0xFD405990, 0x0000000FU, ill12_val[1]);
1331 if (lane2_active == 1)
1332 Xil_Out32(0xFD409928, ill1_val[2]);
1333 if (lane2_active == 1)
1334 psu_mask_write(0xFD409990, 0x0000000FU, ill12_val[2]);
1335 if (lane3_active == 1)
1336 Xil_Out32(0xFD40D928, ill1_val[3]);
1337 if (lane3_active == 1)
1338 psu_mask_write(0xFD40D990, 0x0000000FU, ill12_val[3]);
1339 }
1340
1341 if (lane0_active == 1)
1342 psu_mask_write(0xFD401018, 0x00000030U, 0x00000000U);
1343 if (lane1_active == 1)
1344 psu_mask_write(0xFD405018, 0x00000030U, 0x00000000U);
1345 if (lane2_active == 1)
1346 psu_mask_write(0xFD409018, 0x00000030U, 0x00000000U);
1347 if (lane3_active == 1)
1348 psu_mask_write(0xFD40D018, 0x00000030U, 0x00000000U);
1349
1350 Xil_Out32(0xFD410098, 0);
1351 if (lane0_active == 1) {
1352 Xil_Out32(0xFD403004, 0);
1353 Xil_Out32(0xFD403008, 0);
1354 Xil_Out32(0xFD40300C, 0);
1355 Xil_Out32(0xFD403010, 0);
1356 Xil_Out32(0xFD403014, 0);
1357 Xil_Out32(0xFD403018, 0);
1358 Xil_Out32(0xFD40301C, 0);
1359 Xil_Out32(0xFD403020, 0);
1360 Xil_Out32(0xFD403024, 0);
1361 Xil_Out32(0xFD403028, 0);
1362 Xil_Out32(0xFD40302C, 0);
1363 Xil_Out32(0xFD403030, 0);
1364 Xil_Out32(0xFD403034, 0);
1365 Xil_Out32(0xFD403038, 0);
1366 Xil_Out32(0xFD40303C, 0);
1367 Xil_Out32(0xFD403040, 0);
1368 Xil_Out32(0xFD403044, 0);
1369 Xil_Out32(0xFD403048, 0);
1370 Xil_Out32(0xFD40304C, 0);
1371 Xil_Out32(0xFD403050, 0);
1372 Xil_Out32(0xFD403054, 0);
1373 Xil_Out32(0xFD403058, 0);
1374 Xil_Out32(0xFD403068, 1);
1375 Xil_Out32(0xFD40306C, 0);
1376 Xil_Out32(0xFD4010AC, 0);
1377 psu_mask_write(0xFD410044, 0x00000003U, 0x00000001U);
1378 psu_mask_write(0xFD410040, 0x00000003U, 0x00000001U);
1379 psu_mask_write(0xFD410038, 0x00000007U, 0x00000000U);
1380 }
1381 if (lane1_active == 1) {
1382 Xil_Out32(0xFD407004, 0);
1383 Xil_Out32(0xFD407008, 0);
1384 Xil_Out32(0xFD40700C, 0);
1385 Xil_Out32(0xFD407010, 0);
1386 Xil_Out32(0xFD407014, 0);
1387 Xil_Out32(0xFD407018, 0);
1388 Xil_Out32(0xFD40701C, 0);
1389 Xil_Out32(0xFD407020, 0);
1390 Xil_Out32(0xFD407024, 0);
1391 Xil_Out32(0xFD407028, 0);
1392 Xil_Out32(0xFD40702C, 0);
1393 Xil_Out32(0xFD407030, 0);
1394 Xil_Out32(0xFD407034, 0);
1395 Xil_Out32(0xFD407038, 0);
1396 Xil_Out32(0xFD40703C, 0);
1397 Xil_Out32(0xFD407040, 0);
1398 Xil_Out32(0xFD407044, 0);
1399 Xil_Out32(0xFD407048, 0);
1400 Xil_Out32(0xFD40704C, 0);
1401 Xil_Out32(0xFD407050, 0);
1402 Xil_Out32(0xFD407054, 0);
1403 Xil_Out32(0xFD407058, 0);
1404 Xil_Out32(0xFD407068, 1);
1405 Xil_Out32(0xFD40706C, 0);
1406 Xil_Out32(0xFD4050AC, 0);
1407 psu_mask_write(0xFD410044, 0x0000000CU, 0x00000004U);
1408 psu_mask_write(0xFD410040, 0x0000000CU, 0x00000004U);
1409 psu_mask_write(0xFD410038, 0x00000070U, 0x00000000U);
1410 }
1411 if (lane2_active == 1) {
1412 Xil_Out32(0xFD40B004, 0);
1413 Xil_Out32(0xFD40B008, 0);
1414 Xil_Out32(0xFD40B00C, 0);
1415 Xil_Out32(0xFD40B010, 0);
1416 Xil_Out32(0xFD40B014, 0);
1417 Xil_Out32(0xFD40B018, 0);
1418 Xil_Out32(0xFD40B01C, 0);
1419 Xil_Out32(0xFD40B020, 0);
1420 Xil_Out32(0xFD40B024, 0);
1421 Xil_Out32(0xFD40B028, 0);
1422 Xil_Out32(0xFD40B02C, 0);
1423 Xil_Out32(0xFD40B030, 0);
1424 Xil_Out32(0xFD40B034, 0);
1425 Xil_Out32(0xFD40B038, 0);
1426 Xil_Out32(0xFD40B03C, 0);
1427 Xil_Out32(0xFD40B040, 0);
1428 Xil_Out32(0xFD40B044, 0);
1429 Xil_Out32(0xFD40B048, 0);
1430 Xil_Out32(0xFD40B04C, 0);
1431 Xil_Out32(0xFD40B050, 0);
1432 Xil_Out32(0xFD40B054, 0);
1433 Xil_Out32(0xFD40B058, 0);
1434 Xil_Out32(0xFD40B068, 1);
1435 Xil_Out32(0xFD40B06C, 0);
1436 Xil_Out32(0xFD4090AC, 0);
1437 psu_mask_write(0xFD410044, 0x00000030U, 0x00000010U);
1438 psu_mask_write(0xFD410040, 0x00000030U, 0x00000010U);
1439 psu_mask_write(0xFD41003C, 0x00000007U, 0x00000000U);
1440 }
1441 if (lane3_active == 1) {
1442 Xil_Out32(0xFD40F004, 0);
1443 Xil_Out32(0xFD40F008, 0);
1444 Xil_Out32(0xFD40F00C, 0);
1445 Xil_Out32(0xFD40F010, 0);
1446 Xil_Out32(0xFD40F014, 0);
1447 Xil_Out32(0xFD40F018, 0);
1448 Xil_Out32(0xFD40F01C, 0);
1449 Xil_Out32(0xFD40F020, 0);
1450 Xil_Out32(0xFD40F024, 0);
1451 Xil_Out32(0xFD40F028, 0);
1452 Xil_Out32(0xFD40F02C, 0);
1453 Xil_Out32(0xFD40F030, 0);
1454 Xil_Out32(0xFD40F034, 0);
1455 Xil_Out32(0xFD40F038, 0);
1456 Xil_Out32(0xFD40F03C, 0);
1457 Xil_Out32(0xFD40F040, 0);
1458 Xil_Out32(0xFD40F044, 0);
1459 Xil_Out32(0xFD40F048, 0);
1460 Xil_Out32(0xFD40F04C, 0);
1461 Xil_Out32(0xFD40F050, 0);
1462 Xil_Out32(0xFD40F054, 0);
1463 Xil_Out32(0xFD40F058, 0);
1464 Xil_Out32(0xFD40F068, 1);
1465 Xil_Out32(0xFD40F06C, 0);
1466 Xil_Out32(0xFD40D0AC, 0);
1467 psu_mask_write(0xFD410044, 0x000000C0U, 0x00000040U);
1468 psu_mask_write(0xFD410040, 0x000000C0U, 0x00000040U);
1469 psu_mask_write(0xFD41003C, 0x00000070U, 0x00000000U);
1470 }
1471 return 1;
1472 }
1473
serdes_illcalib(u32 lane3_protocol,u32 lane3_rate,u32 lane2_protocol,u32 lane2_rate,u32 lane1_protocol,u32 lane1_rate,u32 lane0_protocol,u32 lane0_rate)1474 static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate,
1475 u32 lane2_protocol, u32 lane2_rate,
1476 u32 lane1_protocol, u32 lane1_rate,
1477 u32 lane0_protocol, u32 lane0_rate)
1478 {
1479 unsigned int rdata = 0;
1480 unsigned int sata_gen2 = 1;
1481 unsigned int temp_ill12 = 0;
1482 unsigned int temp_PLL_REF_SEL_OFFSET;
1483 unsigned int temp_TM_IQ_ILL1;
1484 unsigned int temp_TM_E_ILL1;
1485 unsigned int temp_tx_dig_tm_61;
1486 unsigned int temp_tm_dig_6;
1487 unsigned int temp_pll_fbdiv_frac_3_msb_offset;
1488
1489 if (lane0_protocol == 2 || lane0_protocol == 1) {
1490 Xil_Out32(0xFD401910, 0xF3);
1491 Xil_Out32(0xFD40193C, 0xF3);
1492 Xil_Out32(0xFD401914, 0xF3);
1493 Xil_Out32(0xFD401940, 0xF3);
1494 }
1495 if (lane1_protocol == 2 || lane1_protocol == 1) {
1496 Xil_Out32(0xFD405910, 0xF3);
1497 Xil_Out32(0xFD40593C, 0xF3);
1498 Xil_Out32(0xFD405914, 0xF3);
1499 Xil_Out32(0xFD405940, 0xF3);
1500 }
1501 if (lane2_protocol == 2 || lane2_protocol == 1) {
1502 Xil_Out32(0xFD409910, 0xF3);
1503 Xil_Out32(0xFD40993C, 0xF3);
1504 Xil_Out32(0xFD409914, 0xF3);
1505 Xil_Out32(0xFD409940, 0xF3);
1506 }
1507 if (lane3_protocol == 2 || lane3_protocol == 1) {
1508 Xil_Out32(0xFD40D910, 0xF3);
1509 Xil_Out32(0xFD40D93C, 0xF3);
1510 Xil_Out32(0xFD40D914, 0xF3);
1511 Xil_Out32(0xFD40D940, 0xF3);
1512 }
1513
1514 if (sata_gen2 == 1) {
1515 if (lane0_protocol == 2) {
1516 temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD402360);
1517 Xil_Out32(0xFD402360, 0x0);
1518 temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410000);
1519 psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU);
1520 temp_TM_IQ_ILL1 = Xil_In32(0xFD4018F8);
1521 temp_TM_E_ILL1 = Xil_In32(0xFD401924);
1522 Xil_Out32(0xFD4018F8, 0x78);
1523 temp_tx_dig_tm_61 = Xil_In32(0xFD4000F4);
1524 temp_tm_dig_6 = Xil_In32(0xFD40106C);
1525 psu_mask_write(0xFD4000F4, 0x0000000BU, 0x00000000U);
1526 psu_mask_write(0xFD40106C, 0x0000000FU, 0x00000000U);
1527 temp_ill12 = Xil_In32(0xFD401990) & 0xF0;
1528
1529 serdes_illcalib_pcie_gen1(0, 0, 0, 0, 0, 0, 1, 0, 0);
1530
1531 Xil_Out32(0xFD402360, temp_pll_fbdiv_frac_3_msb_offset);
1532 Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET);
1533 Xil_Out32(0xFD4018F8, temp_TM_IQ_ILL1);
1534 Xil_Out32(0xFD4000F4, temp_tx_dig_tm_61);
1535 Xil_Out32(0xFD40106C, temp_tm_dig_6);
1536 Xil_Out32(0xFD401928, Xil_In32(0xFD401924));
1537 temp_ill12 =
1538 temp_ill12 | (Xil_In32(0xFD401990) >> 4 & 0xF);
1539 Xil_Out32(0xFD401990, temp_ill12);
1540 Xil_Out32(0xFD401924, temp_TM_E_ILL1);
1541 }
1542 if (lane1_protocol == 2) {
1543 temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD406360);
1544 Xil_Out32(0xFD406360, 0x0);
1545 temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410004);
1546 psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU);
1547 temp_TM_IQ_ILL1 = Xil_In32(0xFD4058F8);
1548 temp_TM_E_ILL1 = Xil_In32(0xFD405924);
1549 Xil_Out32(0xFD4058F8, 0x78);
1550 temp_tx_dig_tm_61 = Xil_In32(0xFD4040F4);
1551 temp_tm_dig_6 = Xil_In32(0xFD40506C);
1552 psu_mask_write(0xFD4040F4, 0x0000000BU, 0x00000000U);
1553 psu_mask_write(0xFD40506C, 0x0000000FU, 0x00000000U);
1554 temp_ill12 = Xil_In32(0xFD405990) & 0xF0;
1555
1556 serdes_illcalib_pcie_gen1(0, 0, 0, 0, 1, 0, 0, 0, 0);
1557
1558 Xil_Out32(0xFD406360, temp_pll_fbdiv_frac_3_msb_offset);
1559 Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET);
1560 Xil_Out32(0xFD4058F8, temp_TM_IQ_ILL1);
1561 Xil_Out32(0xFD4040F4, temp_tx_dig_tm_61);
1562 Xil_Out32(0xFD40506C, temp_tm_dig_6);
1563 Xil_Out32(0xFD405928, Xil_In32(0xFD405924));
1564 temp_ill12 =
1565 temp_ill12 | (Xil_In32(0xFD405990) >> 4 & 0xF);
1566 Xil_Out32(0xFD405990, temp_ill12);
1567 Xil_Out32(0xFD405924, temp_TM_E_ILL1);
1568 }
1569 if (lane2_protocol == 2) {
1570 temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40A360);
1571 Xil_Out32(0xFD40A360, 0x0);
1572 temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410008);
1573 psu_mask_write(0xFD410008, 0x0000001FU, 0x0000000DU);
1574 temp_TM_IQ_ILL1 = Xil_In32(0xFD4098F8);
1575 temp_TM_E_ILL1 = Xil_In32(0xFD409924);
1576 Xil_Out32(0xFD4098F8, 0x78);
1577 temp_tx_dig_tm_61 = Xil_In32(0xFD4080F4);
1578 temp_tm_dig_6 = Xil_In32(0xFD40906C);
1579 psu_mask_write(0xFD4080F4, 0x0000000BU, 0x00000000U);
1580 psu_mask_write(0xFD40906C, 0x0000000FU, 0x00000000U);
1581 temp_ill12 = Xil_In32(0xFD409990) & 0xF0;
1582
1583 serdes_illcalib_pcie_gen1(0, 0, 1, 0, 0, 0, 0, 0, 0);
1584
1585 Xil_Out32(0xFD40A360, temp_pll_fbdiv_frac_3_msb_offset);
1586 Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET);
1587 Xil_Out32(0xFD4098F8, temp_TM_IQ_ILL1);
1588 Xil_Out32(0xFD4080F4, temp_tx_dig_tm_61);
1589 Xil_Out32(0xFD40906C, temp_tm_dig_6);
1590 Xil_Out32(0xFD409928, Xil_In32(0xFD409924));
1591 temp_ill12 =
1592 temp_ill12 | (Xil_In32(0xFD409990) >> 4 & 0xF);
1593 Xil_Out32(0xFD409990, temp_ill12);
1594 Xil_Out32(0xFD409924, temp_TM_E_ILL1);
1595 }
1596 if (lane3_protocol == 2) {
1597 temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40E360);
1598 Xil_Out32(0xFD40E360, 0x0);
1599 temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD41000C);
1600 psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000DU);
1601 temp_TM_IQ_ILL1 = Xil_In32(0xFD40D8F8);
1602 temp_TM_E_ILL1 = Xil_In32(0xFD40D924);
1603 Xil_Out32(0xFD40D8F8, 0x78);
1604 temp_tx_dig_tm_61 = Xil_In32(0xFD40C0F4);
1605 temp_tm_dig_6 = Xil_In32(0xFD40D06C);
1606 psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x00000000U);
1607 psu_mask_write(0xFD40D06C, 0x0000000FU, 0x00000000U);
1608 temp_ill12 = Xil_In32(0xFD40D990) & 0xF0;
1609
1610 serdes_illcalib_pcie_gen1(1, 0, 0, 0, 0, 0, 0, 0, 0);
1611
1612 Xil_Out32(0xFD40E360, temp_pll_fbdiv_frac_3_msb_offset);
1613 Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET);
1614 Xil_Out32(0xFD40D8F8, temp_TM_IQ_ILL1);
1615 Xil_Out32(0xFD40C0F4, temp_tx_dig_tm_61);
1616 Xil_Out32(0xFD40D06C, temp_tm_dig_6);
1617 Xil_Out32(0xFD40D928, Xil_In32(0xFD40D924));
1618 temp_ill12 =
1619 temp_ill12 | (Xil_In32(0xFD40D990) >> 4 & 0xF);
1620 Xil_Out32(0xFD40D990, temp_ill12);
1621 Xil_Out32(0xFD40D924, temp_TM_E_ILL1);
1622 }
1623 rdata = Xil_In32(0xFD410098);
1624 rdata = (rdata & 0xDF);
1625 Xil_Out32(0xFD410098, rdata);
1626 }
1627
1628 if (lane0_protocol == 2 && lane0_rate == 3) {
1629 psu_mask_write(0xFD40198C, 0x000000F0U, 0x00000020U);
1630 psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000094U);
1631 }
1632 if (lane1_protocol == 2 && lane1_rate == 3) {
1633 psu_mask_write(0xFD40598C, 0x000000F0U, 0x00000020U);
1634 psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000094U);
1635 }
1636 if (lane2_protocol == 2 && lane2_rate == 3) {
1637 psu_mask_write(0xFD40998C, 0x000000F0U, 0x00000020U);
1638 psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000094U);
1639 }
1640 if (lane3_protocol == 2 && lane3_rate == 3) {
1641 psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U);
1642 psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000094U);
1643 }
1644
1645 if (lane0_protocol == 1) {
1646 if (lane0_rate == 0) {
1647 serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate,
1648 lane2_protocol, lane2_rate,
1649 lane1_protocol, lane1_rate,
1650 lane0_protocol, 0, 0);
1651 } else {
1652 serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate,
1653 lane2_protocol, lane2_rate,
1654 lane1_protocol, lane1_rate,
1655 lane0_protocol, 0, 0);
1656 serdes_illcalib_pcie_gen1(lane3_protocol, lane3_rate,
1657 lane2_protocol, lane2_rate,
1658 lane1_protocol, lane1_rate,
1659 lane0_protocol, lane0_rate,
1660 1);
1661 }
1662 }
1663
1664 if (lane0_protocol == 3)
1665 Xil_Out32(0xFD401914, 0xF3);
1666 if (lane0_protocol == 3)
1667 Xil_Out32(0xFD401940, 0xF3);
1668 if (lane0_protocol == 3)
1669 Xil_Out32(0xFD401990, 0x20);
1670 if (lane0_protocol == 3)
1671 Xil_Out32(0xFD401924, 0x37);
1672
1673 if (lane1_protocol == 3)
1674 Xil_Out32(0xFD405914, 0xF3);
1675 if (lane1_protocol == 3)
1676 Xil_Out32(0xFD405940, 0xF3);
1677 if (lane1_protocol == 3)
1678 Xil_Out32(0xFD405990, 0x20);
1679 if (lane1_protocol == 3)
1680 Xil_Out32(0xFD405924, 0x37);
1681
1682 if (lane2_protocol == 3)
1683 Xil_Out32(0xFD409914, 0xF3);
1684 if (lane2_protocol == 3)
1685 Xil_Out32(0xFD409940, 0xF3);
1686 if (lane2_protocol == 3)
1687 Xil_Out32(0xFD409990, 0x20);
1688 if (lane2_protocol == 3)
1689 Xil_Out32(0xFD409924, 0x37);
1690
1691 if (lane3_protocol == 3)
1692 Xil_Out32(0xFD40D914, 0xF3);
1693 if (lane3_protocol == 3)
1694 Xil_Out32(0xFD40D940, 0xF3);
1695 if (lane3_protocol == 3)
1696 Xil_Out32(0xFD40D990, 0x20);
1697 if (lane3_protocol == 3)
1698 Xil_Out32(0xFD40D924, 0x37);
1699
1700 return 1;
1701 }
1702
serdes_enb_coarse_saturation(void)1703 static int serdes_enb_coarse_saturation(void)
1704 {
1705 Xil_Out32(0xFD402094, 0x00000010);
1706 Xil_Out32(0xFD406094, 0x00000010);
1707 Xil_Out32(0xFD40A094, 0x00000010);
1708 Xil_Out32(0xFD40E094, 0x00000010);
1709 return 1;
1710 }
1711
serdes_fixcal_code(void)1712 static int serdes_fixcal_code(void)
1713 {
1714 int maskstatus = 1;
1715 unsigned int rdata = 0;
1716 unsigned int match_pmos_code[23];
1717 unsigned int match_nmos_code[23];
1718 unsigned int match_ical_code[7];
1719 unsigned int match_rcal_code[7];
1720 unsigned int p_code = 0;
1721 unsigned int n_code = 0;
1722 unsigned int i_code = 0;
1723 unsigned int r_code = 0;
1724 unsigned int repeat_count = 0;
1725 unsigned int L3_TM_CALIB_DIG20 = 0;
1726 unsigned int L3_TM_CALIB_DIG19 = 0;
1727 unsigned int L3_TM_CALIB_DIG18 = 0;
1728 unsigned int L3_TM_CALIB_DIG16 = 0;
1729 unsigned int L3_TM_CALIB_DIG15 = 0;
1730 unsigned int L3_TM_CALIB_DIG14 = 0;
1731 int i = 0;
1732 int count = 0;
1733
1734 rdata = Xil_In32(0xFD40289C);
1735 rdata = rdata & ~0x03;
1736 rdata = rdata | 0x1;
1737 Xil_Out32(0xFD40289C, rdata);
1738
1739 do {
1740 if (count == 1100000)
1741 break;
1742 rdata = Xil_In32(0xFD402B1C);
1743 count++;
1744 } while ((rdata & 0x0000000E) != 0x0000000E);
1745
1746 for (i = 0; i < 23; i++) {
1747 match_pmos_code[i] = 0;
1748 match_nmos_code[i] = 0;
1749 }
1750 for (i = 0; i < 7; i++) {
1751 match_ical_code[i] = 0;
1752 match_rcal_code[i] = 0;
1753 }
1754
1755 do {
1756 Xil_Out32(0xFD410010, 0x00000000);
1757 Xil_Out32(0xFD410014, 0x00000000);
1758
1759 Xil_Out32(0xFD410010, 0x00000001);
1760 Xil_Out32(0xFD410014, 0x00000000);
1761
1762 maskstatus = mask_poll(0xFD40EF14, 0x2);
1763 if (maskstatus == 0) {
1764 xil_printf("#SERDES initialization timed out\n\r");
1765 return maskstatus;
1766 }
1767
1768 p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
1769 n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
1770 ;
1771 i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
1772 r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
1773 ;
1774
1775 if (p_code >= 0x26 && p_code <= 0x3C)
1776 match_pmos_code[p_code - 0x26] += 1;
1777
1778 if (n_code >= 0x26 && n_code <= 0x3C)
1779 match_nmos_code[n_code - 0x26] += 1;
1780
1781 if (i_code >= 0xC && i_code <= 0x12)
1782 match_ical_code[i_code - 0xc] += 1;
1783
1784 if (r_code >= 0x6 && r_code <= 0xC)
1785 match_rcal_code[r_code - 0x6] += 1;
1786
1787 } while (repeat_count++ < 10);
1788
1789 for (i = 0; i < 23; i++) {
1790 if (match_pmos_code[i] >= match_pmos_code[0]) {
1791 match_pmos_code[0] = match_pmos_code[i];
1792 p_code = 0x26 + i;
1793 }
1794 if (match_nmos_code[i] >= match_nmos_code[0]) {
1795 match_nmos_code[0] = match_nmos_code[i];
1796 n_code = 0x26 + i;
1797 }
1798 }
1799
1800 for (i = 0; i < 7; i++) {
1801 if (match_ical_code[i] >= match_ical_code[0]) {
1802 match_ical_code[0] = match_ical_code[i];
1803 i_code = 0xC + i;
1804 }
1805 if (match_rcal_code[i] >= match_rcal_code[0]) {
1806 match_rcal_code[0] = match_rcal_code[i];
1807 r_code = 0x6 + i;
1808 }
1809 }
1810
1811 L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
1812 L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
1813
1814 L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
1815 L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
1816 | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
1817
1818 L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
1819 L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
1820
1821 L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
1822 L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
1823
1824 L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
1825 L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
1826 | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
1827
1828 L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
1829 L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
1830
1831 Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
1832 Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
1833 Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
1834 Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
1835 Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
1836 Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
1837 return maskstatus;
1838 }
1839
init_serdes(void)1840 static int init_serdes(void)
1841 {
1842 int status = 1;
1843
1844 status &= psu_resetin_init_data();
1845
1846 status &= serdes_fixcal_code();
1847 status &= serdes_enb_coarse_saturation();
1848
1849 status &= psu_serdes_init_data();
1850 status &= psu_resetout_init_data();
1851
1852 return status;
1853 }
1854
init_peripheral(void)1855 static void init_peripheral(void)
1856 {
1857 psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
1858 }
1859
psu_init(void)1860 int psu_init(void)
1861 {
1862 int status = 1;
1863
1864 status &= psu_mio_init_data();
1865 status &= psu_peripherals_pre_init_data();
1866 status &= psu_pll_init_data();
1867 status &= psu_clock_init_data();
1868 status &= psu_ddr_init_data();
1869 status &= psu_ddr_phybringup_data();
1870 status &= psu_peripherals_init_data();
1871 status &= init_serdes();
1872 init_peripheral();
1873
1874 status &= psu_afi_config();
1875 psu_ddr_qos_init_data();
1876
1877 if (status == 0)
1878 return 1;
1879 return 0;
1880 }
1881